In order to fully support SPL_OF_CONTROL, we need BSS to be a bit
larger. This patch relocates BSS to SDRAM instead of SRAM which
is similar to how ARMv7 boards (like OMAP2+) do it.
This means two new variables are required:
CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE
CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte
before the location where U-Boot will load.
Signed-off-by: Adam Ford <aford...@gmail.com>
---
V2: No Change
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index 7b5fab7756..8f04911306 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -10,6 +10,9 @@
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
@@ -42,6 +45,15 @@ SECTIONS
__rel_dyn_end = .;
} >.sram
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
.bss :
{
. = ALIGN(4);
@@ -49,12 +61,5 @@ SECTIONS
*(.bss*)
. = ALIGN(4);
__bss_end = .;
- } >.sram
-
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
+ } >.sdram
}
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 14a3046f19..bb549e363a 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -48,7 +48,8 @@
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
+#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
--
2.17.1
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