Hi Aneesh,
On 08/08/2011 12:27, Aneesh V wrote:
> Hi Reinhard,
>
> On Monday 08 August 2011 03:55 PM, Reinhard Meyer wrote:
>> Hi Aneesh,
>>> On Monday 08 August 2011 03:29 PM, Reinhard Meyer wrote:
Dear Albert, Aneesh, Hong,
There seem to be functions of type
xxx(start, e
Hi Reinhard,
On Monday 08 August 2011 03:55 PM, Reinhard Meyer wrote:
> Hi Aneesh,
>> On Monday 08 August 2011 03:29 PM, Reinhard Meyer wrote:
>>> Dear Albert, Aneesh, Hong,
>>>
>>> There seem to be functions of type
>>>
>>> xxx(start, end) and xxx(start, size).
>>>
>>> Can't it be somehow decided
Hi Aneesh,
> On Monday 08 August 2011 03:29 PM, Reinhard Meyer wrote:
>> Dear Albert, Aneesh, Hong,
>>
>> There seem to be functions of type
>>
>> xxx(start, end) and xxx(start, size).
>>
>> Can't it be somehow decided to use only one variant
>> in all cases (flush, invalidate)?
>
> The u-boot sta
Hi Reinhard,
On Monday 08 August 2011 03:29 PM, Reinhard Meyer wrote:
> Dear Albert, Aneesh, Hong,
>
> There seem to be functions of type
>
> xxx(start, end) and xxx(start, size).
>
> Can't it be somehow decided to use only one variant
> in all cases (flush, invalidate)?
The u-boot standard seems
Dear Albert, Aneesh, Hong,
There seem to be functions of type
xxx(start, end) and xxx(start, size).
Can't it be somehow decided to use only one variant
in all cases (flush, invalidate)?
On a personal taste, I'd prefer (start, size) :)
Best Regards,
Reinhard
Hi Albert,
On Monday 08 August 2011 03:09 PM, Albert ARIBAUD wrote:
> Le 08/08/2011 10:24, Aneesh V a écrit :
>> Hi Albert,
>>
>> On Sunday 07 August 2011 12:25 PM, Albert ARIBAUD wrote:
>>> Hi Aneesh,
>>>
>>> (cutting quotation for readability)
>>>
>>> Le 05/08/2011 16:59, Aneesh V a écrit :
Le 08/08/2011 10:24, Aneesh V a écrit :
> Hi Albert,
>
> On Sunday 07 August 2011 12:25 PM, Albert ARIBAUD wrote:
>> Hi Aneesh,
>>
>> (cutting quotation for readability)
>>
>> Le 05/08/2011 16:59, Aneesh V a écrit :
>>> Hi Albert,
>>
>>> I don't dispute that having buffers aligned is the ideal scen
Hi Albert,
On Sunday 07 August 2011 12:25 PM, Albert ARIBAUD wrote:
> Hi Aneesh,
>
> (cutting quotation for readability)
>
> Le 05/08/2011 16:59, Aneesh V a écrit :
>> Hi Albert,
>
>> I don't dispute that having buffers aligned is the ideal scenario. The
>> question is about error-handling the sit
Hi Bill,
Le 06/08/2011 01:04, J. William Campbell a écrit :
> Hi All,
> I am interested in this last statement in particular, that
> Linux allows non-cache aligned buffers for DMA. In a previous discussion
> series, we demonstrated why it was IMPOSSIBLE for a non-cache aligned
> DMA buf
Hi Aneesh,
(cutting quotation for readability)
Le 05/08/2011 16:59, Aneesh V a écrit :
> Hi Albert,
> I don't dispute that having buffers aligned is the ideal scenario. The
> question is about error-handling the situation when this requirement is
> not met.
I understand what you're trying to ac
On 8/5/2011 4:51 AM, Aneesh V wrote:
> Hi Albert,
>
> On Friday 05 August 2011 04:33 PM, Albert ARIBAUD wrote:
>> Hi Aneesh,
>>
>> On 05/08/2011 12:47, Aneesh V wrote:
>>> Hi Eric,
>>>
>>> On Friday 05 August 2011 04:03 PM, Hong Xu wrote:
Hi Aneesh,
>>> [snip ..]
> IMHO, Hong's approach is
Hi Albert,
On Friday 05 August 2011 06:47 PM, Albert ARIBAUD wrote:
> (BTW: responders to this thread please stop using my @free.fr address. I
> just noticed the big pile of U-Boot related messages that went to an
> account which I do not use for U-Boot any more)
>
> On 05/08/2011 13:51, Aneesh V
(BTW: responders to this thread please stop using my @free.fr address. I
just noticed the big pile of U-Boot related messages that went to an
account which I do not use for U-Boot any more)
On 05/08/2011 13:51, Aneesh V wrote:
> Hi Albert,
>
> On Friday 05 August 2011 04:33 PM, Albert ARIBAUD wr
Hi Albert,
On Friday 05 August 2011 04:33 PM, Albert ARIBAUD wrote:
> Hi Aneesh,
>
> On 05/08/2011 12:47, Aneesh V wrote:
>> Hi Eric,
>>
>> On Friday 05 August 2011 04:03 PM, Hong Xu wrote:
>>> Hi Aneesh,
>> [snip ..]
IMHO, Hong's approach is correct. If the buffer that is invalidated is
Hi Reinhard,
On 05/08/2011 13:23, Reinhard Meyer wrote:
> Dear Albert, Aneesh, Eric,
>>> We have a fundamental problem when it comes to invalidating an
>>> un-aligned buffer. Either you flush the boundary lines and corrupt your
>>> buffer at boundaries OR you invalidate without flushing and corrup
Dear Albert, Aneesh, Eric,
> > We have a fundamental problem when it comes to invalidating an
> > un-aligned buffer. Either you flush the boundary lines and corrupt your
> > buffer at boundaries OR you invalidate without flushing and corrupt
> > memory around your buffer. Both are not good! The onl
Hi Aneesh,
On 05/08/2011 12:47, Aneesh V wrote:
> Hi Eric,
>
> On Friday 05 August 2011 04:03 PM, Hong Xu wrote:
>> Hi Aneesh,
> [snip ..]
>>>
>>> IMHO, Hong's approach is correct. If the buffer that is invalidated is
>>> not aligned to cache-line, one cache-line at the respective boundary
>>> may
Hi Eric,
On Friday 05 August 2011 04:03 PM, Hong Xu wrote:
> Hi Aneesh,
[snip ..]
>>
>> IMHO, Hong's approach is correct. If the buffer that is invalidated is
>> not aligned to cache-line, one cache-line at the respective boundary
>> may have to be flushed to make sure the invalidation doesn't aff
Hi Aneesh,
On 08/05/2011 03:10 PM, Aneesh V wrote:
> Hi Hong, Albert,
>
> On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote:
>> Le 05/08/2011 08:38, Hong Xu a écrit :
>>> Hi Albert,
>>>
>>> I've tried to deal with the case that the (start, stop) is not aligned.
>>> If mis-align happens, the
Hi Albert,
On Friday 05 August 2011 02:50 PM, Albert ARIBAUD wrote:
> Hi Aneesh,
>
> On 05/08/2011 09:10, Aneesh V wrote:
>> Hi Hong, Albert,
>>
>> On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote:
>>> Le 05/08/2011 08:38, Hong Xu a écrit :
Hi Albert,
I've tried to deal with
Hi Aneesh,
On 05/08/2011 09:10, Aneesh V wrote:
> Hi Hong, Albert,
>
> On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote:
>> Le 05/08/2011 08:38, Hong Xu a écrit :
>>> Hi Albert,
>>>
>>> I've tried to deal with the case that the (start, stop) is not aligned.
>>> If mis-align happens, the adj
Hi Hong, Albert,
On Friday 05 August 2011 12:16 PM, Albert ARIBAUD wrote:
> Le 05/08/2011 08:38, Hong Xu a écrit :
>> Hi Albert,
>>
>> I've tried to deal with the case that the (start, stop) is not aligned.
>> If mis-align happens, the adjacent lines will be cleaned before
>> invalidating. And fro
On 08/05/2011 02:46 PM, Albert ARIBAUD wrote:
> Le 05/08/2011 08:38, Hong Xu a écrit :
>> Hi Albert,
>>
>> On 08/05/2011 02:13 PM, Albert ARIBAUD wrote:
>>> Hi Hong Xu,
>>>
>>> Le 05/08/2011 06:44, Hong Xu a écrit :
After DMA operation, we need to maintain D-Cache coherency.
We need to cl
Le 05/08/2011 08:38, Hong Xu a écrit :
> Hi Albert,
>
> On 08/05/2011 02:13 PM, Albert ARIBAUD wrote:
>> Hi Hong Xu,
>>
>> Le 05/08/2011 06:44, Hong Xu a écrit :
>>> After DMA operation, we need to maintain D-Cache coherency.
>>> We need to clean cache (write back the dirty lines) and then
>>> make
Hi Albert,
On 08/05/2011 02:13 PM, Albert ARIBAUD wrote:
> Hi Hong Xu,
>
> Le 05/08/2011 06:44, Hong Xu a écrit :
>> After DMA operation, we need to maintain D-Cache coherency.
>> We need to clean cache (write back the dirty lines) and then
>> make the cache invalidate as well(hence CPU will fetch
Hi Hong Xu,
Le 05/08/2011 08:17, Hong Xu a écrit :
>> Why so complicated?
>
> In case of mis-aligned (start, stop), this is to clean the cache line,
> aka. write back the potential dirty lines before successive invalidating
How do you know the dirty data should be flushed rather than invalidated
H Reinhard,
On 08/05/2011 01:11 PM, Reinhard Meyer wrote:
> Dear Hong Xu,
>> After DMA operation, we need to maintain D-Cache coherency.
>> We need to clean cache (write back the dirty lines) and then
>> make the cache invalidate as well(hence CPU will fetch data
>> written by DMA controller from
Hi Hong Xu,
Le 05/08/2011 06:44, Hong Xu a écrit :
> After DMA operation, we need to maintain D-Cache coherency.
> We need to clean cache (write back the dirty lines) and then
> make the cache invalidate as well(hence CPU will fetch data
> written by DMA controller from RAM).
>
> Tested on AT91SAM
Dear Hong Xu,
> After DMA operation, we need to maintain D-Cache coherency.
> We need to clean cache (write back the dirty lines) and then
> make the cache invalidate as well(hence CPU will fetch data
> written by DMA controller from RAM).
>
> Tested on AT91SAM9261EK with Peripheral DMA controller.
After DMA operation, we need to maintain D-Cache coherency.
We need to clean cache (write back the dirty lines) and then
make the cache invalidate as well(hence CPU will fetch data
written by DMA controller from RAM).
Tested on AT91SAM9261EK with Peripheral DMA controller.
Signed-off-by: Hong Xu
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