Hi Dipen,
On Thu, Oct 1, 2009 at 12:48 PM, Dudhat Dipen-B09055
dipen.dud...@freescale.com wrote:
Hi Bin,
We can know the block transfer complete using IRQSTAT(Transfer
Complete).
But reading writing in PIO mode takes time for byte by byte transfers
and there is no way to poll that
-Original Message-
From: Bin Meng [mailto:bmeng...@gmail.com]
Sent: Monday, October 05, 2009 1:59 PM
To: Dudhat Dipen-B09055
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC
Controller Driver
Hi Dipen,
On Thu, Oct 1, 2009 at 12:48 PM, Dudhat
complete *\
Is that ok ??
Regards,
Dipen
-Original Message-
From: Bin Meng [mailto:bmeng...@gmail.com]
Sent: Monday, September 28, 2009 4:41 AM
To: Dudhat Dipen-B09055
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC
Controller Driver
On Thu
On Thu, Sep 10, 2009 at 9:37 PM, Dipen Dudhat
dipen.dud...@freescale.com wrote:
+ while (size (!(irqstat IRQSTAT_TC))) {
+ udelay(100);
+ irqstat = in_be32(regs-irqstat);
+ databuf
-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC
Controller Driver
Dear Dipen Dudhat,
In message 1252589856-4970-1-git-send-email-dipen.dud...@freescale.com
you wrote:
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has introduced to do data transfer using CPU
Dear Dipen Dudhat,
In message 1252589856-4970-1-git-send-email-dipen.dud...@freescale.com you
wrote:
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has introduced to do data transfer using CPU.
In PIO mode data transfer performance will be degraded by a large
Dear Dipen Dudhat,
In message 1252904203-9129-1-git-send-email-dipen.dud...@freescale.com you
wrote:
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has introduced to do data transfer using CPU.
In PIO mode data transfer performance will be degraded by a large
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has introduced to do data transfer using CPU.
In PIO mode data transfer performance will be degraded by a large extent.
Note:
In PIO mode multiple block read/write requires delay to complete the transfer.
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has introduced to do data transfer using CPU.
In PIO mode data transfer performance will be degraded by a large extent.
Note:
In PIO mode multiple block read/write requires delay to complete the transfer.
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