On Wed, Apr 4, 2018 at 7:40 AM, Ivan Gorinov wrote:
> On Wed, Apr 04, 2018 at 12:15:24PM +0800, Bin Meng wrote:
>> > Doesn't readX/writeX imply a single I/O operation?
>> > It may be misleading to define it as two.
>> >
>> > Assuming MMX or SSE2 to be supported by all x86
On Wed, Apr 4, 2018 at 2:26 AM, Ivan Gorinov wrote:
> On Tue, Apr 03, 2018 at 06:17:42AM -0600, Andy Shevchenko wrote:
>> >> > If readq() is defined as two read operations in 32-bit code, main
>> >> > counter
>> >> > rollover (low part overflow, high part increment) can
On Wed, Apr 04, 2018 at 12:15:24PM +0800, Bin Meng wrote:
> > Doesn't readX/writeX imply a single I/O operation?
> > It may be misleading to define it as two.
> >
> > Assuming MMX or SSE2 to be supported by all x86 processors, 64-bit I/O
> > registers can be accessed as a single operation even in
On Wed, Apr 4, 2018 at 7:26 AM, Ivan Gorinov wrote:
> On Tue, Apr 03, 2018 at 06:17:42AM -0600, Andy Shevchenko wrote:
>> >> > If readq() is defined as two read operations in 32-bit code, main
>> >> > counter
>> >> > rollover (low part overflow, high part increment) can
On Tue, Apr 03, 2018 at 06:17:42AM -0600, Andy Shevchenko wrote:
> >> > If readq() is defined as two read operations in 32-bit code, main counter
> >> > rollover (low part overflow, high part increment) can happen between
> >> > them.
> >> And how this contradicts ther current code?
> > It just
On Tue, Apr 3, 2018 at 2:00 AM, Ivan Gorinov wrote:
> On Sat, Mar 31, 2018 at 06:31:03AM -0600, Andy Shevchenko wrote:
>> >> > + tl = readl(regs + HPET_MAIN_COUNT_L);
>> >> > + th = readl(regs + HPET_MAIN_COUNT_H);
>> >>
>> >> Ditto.
>> >
>> >
On Sat, Mar 31, 2018 at 06:31:03AM -0600, Andy Shevchenko wrote:
> >> > + tl = readl(regs + HPET_MAIN_COUNT_L);
> >> > + th = readl(regs + HPET_MAIN_COUNT_H);
> >>
> >> Ditto.
> >
> > If readq() is defined as two read operations in 32-bit code, main counter
> > rollover
On Sat, Mar 31, 2018 at 4:03 AM, Ivan Gorinov wrote:
> On Fri, Mar 30, 2018 at 10:46:40PM +0300, Andy Shevchenko wrote:
>
>> > + writel(0, regs + HPET_MAIN_COUNT_L);
>> > + writel(0, regs + HPET_MAIN_COUNT_H);
>>
>> Can we use writeq() here?
>
> I don't see
On Fri, Mar 30, 2018 at 10:46:40PM +0300, Andy Shevchenko wrote:
> > + writel(0, regs + HPET_MAIN_COUNT_L);
> > + writel(0, regs + HPET_MAIN_COUNT_H);
>
> Can we use writeq() here?
I don't see readq/writeq defined for x86, even x86_64.
> > + tl = readl(regs +
On Fri, Mar 30, 2018 at 1:29 AM, Ivan Gorinov wrote:
> Adding HPET as an alternative timer for x86 (default is TSC).
> HPET counter has constant frequency and does not need calibration.
> This change also makes TSC timer driver optional on x86.
> If X86_TSC is disabled,
Hi Ivan,
On Fri, Mar 30, 2018 at 6:29 AM, Ivan Gorinov wrote:
> Adding HPET as an alternative timer for x86 (default is TSC).
> HPET counter has constant frequency and does not need calibration.
> This change also makes TSC timer driver optional on x86.
> If X86_TSC is
Adding HPET as an alternative timer for x86 (default is TSC).
HPET counter has constant frequency and does not need calibration.
This change also makes TSC timer driver optional on x86.
If X86_TSC is disabled, early timer functions are provided by HPET.
Signed-off-by: Ivan Gorinov
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