Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-17 Thread Marek Vasut
On 10/17/2017 01:10 PM, Faiz Abbas wrote: > Hey, > > On Tuesday 17 October 2017 03:31 PM, Marek Vasut wrote: >> On 10/17/2017 07:25 AM, Faiz Abbas wrote: >>> >>> >>> On Monday 16 October 2017 08:52 PM, Marek Vasut wrote: On 10/16/2017 04:51 PM, Felipe Balbi wrote: > > Hi, > >

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-17 Thread Faiz Abbas
Hey, On Tuesday 17 October 2017 03:31 PM, Marek Vasut wrote: > On 10/17/2017 07:25 AM, Faiz Abbas wrote: >> >> >> On Monday 16 October 2017 08:52 PM, Marek Vasut wrote: >>> On 10/16/2017 04:51 PM, Felipe Balbi wrote: Hi, Faiz Abbas writes: Marek

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-17 Thread Marek Vasut
On 10/17/2017 07:25 AM, Faiz Abbas wrote: > > > On Monday 16 October 2017 08:52 PM, Marek Vasut wrote: >> On 10/16/2017 04:51 PM, Felipe Balbi wrote: >>> >>> Hi, >>> >>> Faiz Abbas writes: >>> Marek Vasut writes: On 10/16/2017 07:21 AM, Faiz Abbas

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Faiz Abbas
On Monday 16 October 2017 08:52 PM, Marek Vasut wrote: > On 10/16/2017 04:51 PM, Felipe Balbi wrote: >> >> Hi, >> >> Faiz Abbas writes: >> Marek Vasut writes: >>> On 10/16/2017 07:21 AM, Faiz Abbas wrote: A flush of the cache is required

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Marek Vasut
On 10/16/2017 04:20 PM, Felipe Balbi wrote: > > Hi, > > Faiz Abbas writes: >> Hi Felipe, >> >> On Monday 16 October 2017 07:25 PM, Felipe Balbi wrote: >>> >>> Hi, >>> >>> Marek Vasut writes: On 10/16/2017 07:21 AM, Faiz Abbas wrote: > A flush of the

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Marek Vasut
On 10/16/2017 04:51 PM, Felipe Balbi wrote: > > Hi, > > Faiz Abbas writes: > Marek Vasut writes: >> On 10/16/2017 07:21 AM, Faiz Abbas wrote: >>> A flush of the cache is required before any outbound DMA access can >>> take place. The minimum

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Felipe Balbi
Hi, Faiz Abbas writes: Marek Vasut writes: > On 10/16/2017 07:21 AM, Faiz Abbas wrote: >> A flush of the cache is required before any outbound DMA access can >> take place. The minimum size that can be flushed from the cache is >> one

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Faiz Abbas
Hi, On Monday 16 October 2017 07:50 PM, Felipe Balbi wrote: > > Hi, > > Faiz Abbas writes: >> Hi Felipe, >> >> On Monday 16 October 2017 07:25 PM, Felipe Balbi wrote: >>> >>> Hi, >>> >>> Marek Vasut writes: On 10/16/2017 07:21 AM, Faiz Abbas wrote: >

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Felipe Balbi
Hi, Faiz Abbas writes: > Hi Felipe, > > On Monday 16 October 2017 07:25 PM, Felipe Balbi wrote: >> >> Hi, >> >> Marek Vasut writes: >>> On 10/16/2017 07:21 AM, Faiz Abbas wrote: A flush of the cache is required before any outbound DMA access can

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Faiz Abbas
Hi Felipe, On Monday 16 October 2017 07:25 PM, Felipe Balbi wrote: > > Hi, > > Marek Vasut writes: >> On 10/16/2017 07:21 AM, Faiz Abbas wrote: >>> A flush of the cache is required before any outbound DMA access can >>> take place. The minimum size that can be flushed from the

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Felipe Balbi
Hi, Marek Vasut writes: > On 10/16/2017 07:21 AM, Faiz Abbas wrote: >> A flush of the cache is required before any outbound DMA access can >> take place. The minimum size that can be flushed from the cache is >> one cache line size. Therefore, any buffer allocated for DMA should

Re: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-16 Thread Marek Vasut
On 10/16/2017 07:21 AM, Faiz Abbas wrote: > A flush of the cache is required before any outbound DMA access can > take place. The minimum size that can be flushed from the cache is > one cache line size. Therefore, any buffer allocated for DMA should > be in multiples of cache line size. > >

[U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

2017-10-15 Thread Faiz Abbas
A flush of the cache is required before any outbound DMA access can take place. The minimum size that can be flushed from the cache is one cache line size. Therefore, any buffer allocated for DMA should be in multiples of cache line size. Thus, allocate memory for ep0_trb in multiples of cache