This patch series addresses two problems with reads/writes not working with the Cadence QSPI device on the socfpga arch.
The first issue is reads/writes to the Cadence QSPI device do not work correctly with caching enabled on the socfpga. This problem was introduced with previous commits that use a bounce buffer to support unaligned read/writes. Patches 1-3 address this issue by replacing the bounce buffer with a non-cached version. The second issue with the Cadence QSPI device on the socfpga device is that the indaddrtrig register needs a different value than the ahbbase address. Adopting the trigger-address DT bindings from the Linux kernel allows the indaddrtrig reg to be set correctly for the socfpga arch. Jason A. Rush (7): Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible" Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" spi: cadence_qspi: Cleanup register loading/accesses spi: cadence_spi: Add cdns,trigger-address DT property dts: socfpga: Add trigger-address property to QSPI device dts: k2g: Add trigger-address property to QSPI device dts: stv0991: Add trigger-address property to QSPI device Vignesh R (1): spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible arch/arm/dts/keystone-k2g.dtsi | 1 + arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 1 + drivers/spi/cadence_qspi.c | 26 ++++++----- drivers/spi/cadence_qspi.h | 29 ++++++------ drivers/spi/cadence_qspi_apb.c | 99 +++++++++++++++++++--------------------- include/configs/k2g_evm.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stv0991.h | 1 - 9 files changed, 81 insertions(+), 79 deletions(-) -- 2.11.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/listinfo/u-boot