ul Walmsley ; Atish
> Patra ; Christoph Hellwig ; U-
> Boot Mailing List
> Subject: Re: [PATCH v2 03/11] riscv: generic: Ensure that U-Boot runs within
> 4GB for 64bit systems
>
> On Fri, Jan 18, 2019 at 7:19 PM Anup Patel wrote:
> >
> > On 64bit systems, the DRAM top c
On Fri, Jan 18, 2019 at 7:19 PM Anup Patel wrote:
>
> On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
> DMA mapping APIs will generate DMA addresses beyond 4GB. This
> breaks DMA programming in 32bit DMA capable devices (such as
> Cadence MACB ethernet). For example, If DRAM is
l.walms...@sifive.com; pal...@sifive.com; h...@infradead.org; u-
> b...@lists.denx.de; ag...@suse.de; Atish Patra
> Subject: Re: [PATCH v2 03/11] riscv: generic: Ensure that U-Boot runs within
> 4GB for 64bit systems
>
> On Fri, 2019-01-18 at 11:18 +, Anup Patel wrote:
&g
On Fri, 2019-01-18 at 11:18 +, Anup Patel wrote:
> On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
> DMA mapping APIs will generate DMA addresses beyond 4GB. This
> breaks DMA programming in 32bit DMA capable devices (such as
> Cadence MACB ethernet). For example, If DRAM is
On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB
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