The SFR (special function registers) can be shared bwteen
sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.s...@atmel.com>
---
Changes in v2: None
arch/arm/include/asm/arch-at91/sama5_sfr.h | 38 ++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 arch/arm/include/asm/arch-at91/sama5_sfr.h
diff --git a/arch/arm/include/asm/arch-at91/sama5_sfr.h
b/arch/arm/include/asm/arch-at91/sama5_sfr.h
new file mode 100644
index 0000000..d3d2439
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5_sfr.h
@@ -0,0 +1,38 @@
+/*
+ * Special Function Register (SFR)
+ *
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.s...@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5_SFR_H
+#define __SAMA5_SFR_H
+
+struct atmel_sfr {
+ u32 reserved1; /* 0x00 */
+ u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ u32 reserved2; /* 0x08 */
+ u32 reserved3; /* 0x0c */
+ u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register
*/
+ u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */
+ u32 reserved4[4]; /* 0x18 ~ 0x24 */
+ u32 secure; /* 0x28: Security Configuration Register */
+ u32 reserved5[5]; /* 0x2c ~ 0x3c */
+ u32 ebicfg; /* 0x40: EBI Configuration Register */
+ u32 reserved6[2]; /* 0x44 ~ 0x48 */
+ u32 sn0; /* 0x4c */
+ u32 sn1; /* 0x50 */
+ u32 aicredir; /* 0x54 */
+};
+
+/* Bit field in DDRCFG */
+#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
+#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
+
+/* Bit field in AICREDIR */
+#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
+#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
+
+#endif
--
2.1.0.24.g4109c28
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