On Mon, Apr 22, 2019 at 09:43:32PM +0530, Vignesh Raghavendra wrote:
> On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
> maintenance operations being done to support non-coherent platforms
> causes issues.
>
> For example, here is how U-Boot prepares/handles a buffer to receive
On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
maintenance operations being done to support non-coherent platforms
causes issues.
For example, here is how U-Boot prepares/handles a buffer to receive
data from a device (DMA Write). This may vary slightly depending on the
driver
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