The SAMAA5D4 SoC can access DDR in interleave mode.
Signed-off-by: Bo Shen <voice.s...@atmel.com>
---
Changes in v2: None
arch/arm/cpu/at91-common/mpddrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/at91-common/mpddrc.c
b/arch/arm/cpu/at91-common/mpddrc.c
index 44798e6..beec13d 100644
--- a/arch/arm/cpu/at91-common/mpddrc.c
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static int ddr2_decodtype_is_seq(u32 cr)
{
-#if defined(CONFIG_SAMA5D3)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
return 0;
#endif
--
2.1.0.24.g4109c28
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