subject:"\[U\-Boot\] \[PATCH v2 15\/26\] arm\: dts\: k3\-j721e\-main\: Add C71x DSP node"

Re: [U-Boot] [PATCH v2 15/26] arm: dts: k3-j721e-main: Add C71x DSP node

2019-10-12 Thread Tom Rini

On Wed, Sep 04, 2019 at 04:01:40PM +0530, Lokesh Vutla wrote: > The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN > voltage domain containing the next-generation C711 CPU core. The > subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of > L2 configurable SRAM/Cache.

[U-Boot] [PATCH v2 15/26] arm: dts: k3-j721e-main: Add C71x DSP node

2019-09-04 Thread Lokesh Vutla

The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN voltage domain containing the next-generation C711 CPU core. The subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of L2 configurable SRAM/Cache. This subsystem has a CMMU but is not used currently. The inter-processor