On Mon, Apr 22, 2019 at 09:43:33PM +0530, Vignesh Raghavendra wrote:
> AM654 SoC is IO coherent wrt A53 cores, therefore enable
> SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
> SPL/U-Boot.
>
> Signed-off-by: Vignesh Raghavendra
Applied to u-boot/master, thanks!
--
Tom
signature.a
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra
---
board/ti/am65x/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index d4b
2 matches
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