The socfpga arch uses a different value for the indaddrtrig reg than
the ahbbase address. Adopting the trigger-address DT bindings from
the Linux kernel allows the indaddrtrig reg to be set correctly on
the socfpga arch.
Tested on Terasic SoCKit dev board (Altera Cyclone V)
Signed-off-by: Jason A. Rush <jason.r...@gd-ms.com>
---
Changed in v2:
- renamed DT property to trigger-address
- load trigger-address as a u32
drivers/spi/cadence_qspi.c | 1 +
drivers/spi/cadence_qspi.h | 1 +
drivers/spi/cadence_qspi_apb.c | 4 ++--
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 09f2ec3528..92d08eb3c6 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -300,6 +300,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
*bus)
}
plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
+ plat->trigger_address = fdtdec_get_uint(blob, node, "trigger-address",
0);
/* All other paramters are embedded in the child node */
subnode = fdt_first_subnode(blob, node);
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index da21b1346d..d607974cbe 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -26,6 +26,7 @@ struct cadence_spi_platdata {
u32 tchsh_ns;
u32 tslch_ns;
u32 sram_size;
+ u32 trigger_address;
};
struct cadence_spi_priv {
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 52ec892c4a..89fa3eaa21 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -559,7 +559,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
cadence_spi_platdata *plat,
addr_bytes = cmdlen - 1;
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
@@ -699,7 +699,7 @@ int cadence_qspi_apb_indirect_write_setup(struct
cadence_spi_platdata *plat,
return -EINVAL;
}
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
--
2.11.0
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