Since dra7x platforms address bus is define as 64 bits to support
LAPE, fdtdec_get_addr() returns a invalid address for mdio based
and gmii_sel register address. Fixing this by using
fdtdec_get_addr_size_auto_noparent() which will derive address
cell and size cell from its parent.
Signed-off-by: Mugunthan V N <mugunthan...@ti.com>
Reviewed-by: Tom Rini <tr...@konsulko.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
---
drivers/net/cpsw.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 971ebf0..9b1e37b 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -1137,6 +1137,11 @@ static const struct eth_ops cpsw_eth_ops = {
.stop = cpsw_eth_stop,
};
+static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
+{
+ return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL);
+}
+
static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -1202,8 +1207,14 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice
*dev)
name = fdt_get_name(fdt, subnode, &len);
if (!strncmp(name, "mdio", 4)) {
- priv->data.mdio_base = fdtdec_get_addr(fdt, subnode,
- "reg");
+ u32 mdio_base;
+
+ mdio_base = cpsw_get_addr_by_node(fdt, subnode);
+ if (mdio_base == FDT_ADDR_T_NONE) {
+ error("Not able to get MDIO address space\n");
+ return -ENOENT;
+ }
+ priv->data.mdio_base = mdio_base;
}
if (!strncmp(name, "slave", 5)) {
@@ -1221,8 +1232,13 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice
*dev)
}
if (!strncmp(name, "cpsw-phy-sel", 12)) {
- priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode,
- "reg");
+ priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
+ subnode);
+
+ if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
+ error("Not able to get gmii_sel reg address\n");
+ return -ENOENT;
+ }
}
}
--
2.8.1.339.g3ad15fd
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