mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by:
On Thursday, August 21, 2014 at 06:12:08 PM, Fabio Estevam wrote:
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs
On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut ma...@denx.de wrote:
Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't there
something completely else broken on MX6SX ?
Thanks for the review, Marek.
Inspecting this further I think the correct fix would be:
On Thursday, August 21, 2014 at 06:41:26 PM, Fabio Estevam wrote:
On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut ma...@denx.de wrote:
Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't
there something completely else broken on MX6SX ?
Thanks for the review, Marek.
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