Re: [U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working

2017-10-23 Thread Chee, Tien Fong
On Jum, 2017-10-20 at 10:11 -0500, Dinh Nguyen wrote: > Please update your commit header. > > On 10/13/2017 03:08 AM, tien.fong.c...@intel.com wrote: > > > > From: Tien Fong Chee > > > > SPL configures DDR by programming peripheral raw binary file > > and calibrating

Re: [U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working

2017-10-20 Thread Dinh Nguyen
Please update your commit header. On 10/13/2017 03:08 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > SPL configures DDR by programming peripheral raw binary file > and calibrating DDR. > > Signed-off-by: Tien Fong Chee > ---

[U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working

2017-10-13 Thread tien . fong . chee
From: Tien Fong Chee SPL configures DDR by programming peripheral raw binary file and calibrating DDR. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/spl.c | 56 + 1 file changed, 56