Re: [U-Boot] [PATCH v4 17/28] arm: socfpga: arria10: update dwmac reset function to support Arria10

2017-01-22 Thread Marek Vasut
On 01/10/2017 06:20 AM, Chee Tien Fong wrote: > From: Tien Fong Chee > > On the Arria10, the EMAC phy mode configuration for each EMACs is located > in separate registers versus being in 1 register for the GEN5 devices. The > Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. > > Updat

[U-Boot] [PATCH v4 17/28] arm: socfpga: arria10: update dwmac reset function to support Arria10

2017-01-09 Thread Chee Tien Fong
From: Tien Fong Chee On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset function to support both GEN5 and