On Mon, 2019-02-11 at 04:32 +, Anup Patel wrote:
> > -Original Message-
> > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Monday, February 11, 2019 12:10 AM
> > To: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com;
> > joe.hershber...@ni.com;
> -Original Message-
> From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> Sent: Monday, February 11, 2019 12:10 AM
> To: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com;
> joe.hershber...@ni.com; r...@andestech.com;
> yamada.masah...@socionext.com;
On Sat, 2019-02-09 at 06:32 +, Anup Patel wrote:
> Add driver code for the SiFive FU540 PRCI IP block. This IP block
> handles reset and clock control for the SiFive FU540 device and
> implements SoC-level clock tree controls and dividers.
>
> Based on code written by Wesley Terpstra
>
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
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