Vignesh,
> On 05.02.2019, at 09:08, Vignesh R wrote:
>
>
>
> On 01/02/19 10:45 PM, Philipp Tomsich wrote:
>> Tom,
>>
>> I am a little late this time with our changes for rc1. Hope this doesn’t
>> impact your workflow too much.
>> Things got a bit messy this time, as some of the series
On 01/02/19 10:45 PM, Philipp Tomsich wrote:
> Tom,
>
> I am a little late this time with our changes for rc1. Hope this doesn’t
> impact your workflow too much.
> Things got a bit messy this time, as some of the series introduced unexpected
> isses during testing
> (such as the debug UART
On Fri, Feb 01, 2019 at 06:15:20PM +0100, Philipp Tomsich wrote:
> Tom,
>
> I am a little late this time with our changes for rc1. Hope this doesn’t
> impact your workflow too much.
> Things got a bit messy this time, as some of the series introduced unexpected
> isses during testing
> (such
Travis-CI finally completed the build-test:
https://travis-ci.org/ptomsich/u-boot-rockchip/builds/487509207
> On 01.02.2019, at 18:15, Philipp Tomsich
> wrote:
>
> Tom,
>
> I am a little late this time with our changes for rc1. Hope this doesn’t
> impact your workflow too much.
>
Tom,
I am a little late this time with our changes for rc1. Hope this doesn’t
impact your workflow too much.
Things got a bit messy this time, as some of the series introduced unexpected
isses during testing
(such as the debug UART not being available).
Travis is still running
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