Re: [U-Boot] [Patch v4 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-05 Thread Kumar Gala
On Mar 2, 2011, at 4:24 PM, York Sun wrote: The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun york...@freescale.com ---

[U-Boot] [Patch v4 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-02 Thread York Sun
The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun york...@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++-- 1 files