Hello Wolfgang,
2011/3/13 Wolfgang Denk w...@denx.de:
Dear Daniel Schwierzeck,
In message 4d7c147a.5060...@gmail.com you wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc
and capable of 64-bit,
Dear Daniel Schwierzeck,
In message aanlktinp-3rvxvkcxi8_xtra8mkobztv88vu2t1yk...@mail.gmail.com you
wrote:
OTOH, the purple board has not been actively maintained for several
years, and I'm not aware of anybody who still has access to the
hardware. =C2=A0If it should cause trouble, it
Seperating the SOCs solves most of my problems with the exception of board.c,
but then again, we're rather a special case there due to some of the stuff we
do.
Not counting our SDK we have around 27Kloc for our platform, a large chunk of
that being DDR2/3 memory initialization code. Our SDK
Dear Daniel Schwierzeck,
In message 4d7c147a.5060...@gmail.com you wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc
and capable of 64-bit, which MIPS32 is 32-bit only architecture.
that was an
On 3/9/11 10:16 PM, daniel.schwierz...@googlemail.com wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc
and capable of 64-bit, which MIPS32 is 32-bit only architecture.
code resides in the global
Hi Shinya,
On 03/12/2011 03:43 PM, Shinya Kuribayashi wrote:
On 3/9/11 10:16 PM, daniel.schwierz...@googlemail.com wrote:
All current CPUs and SoCs are based on Mips32 arch. The complete
Is that true? What about purple SoC? IIUC It's based on MIPS 5Kc
and capable of 64-bit, which MIPS32 is
All current CPUs and SoCs are based on Mips32 arch. The complete
code resides in the global arch/mips/cpu directory. This is not
suitable if other Mips architectures like Mips64 or Octeon should
be supported in the future.
To achieve this the current CPU code is moved to its own mips32
7 matches
Mail list logo