Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-13 Thread vikasm
Hi Marek, On 08/12/2015 07:15 PM, Marek Vasut wrote: On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: This patch is to separate the base trigger from the read/write transfer start addresses. This patch breaks the QSPI support on SoCFPGA. ok, can you please try to debug the

Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-13 Thread Marek Vasut
On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: Hi Marek, Hi! On 08/13/2015 09:42 AM, vikasm wrote: Hi Marek, On 08/12/2015 07:15 PM, Marek Vasut wrote: On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: This patch is to separate the base trigger from the

Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-13 Thread vikas
Hi Marek, On 08/13/2015 09:42 AM, vikasm wrote: Hi Marek, On 08/12/2015 07:15 PM, Marek Vasut wrote: On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: This patch is to separate the base trigger from the read/write transfer start addresses. This patch breaks the QSPI support

Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-13 Thread vikas
Hi, On 08/13/2015 03:48 PM, Marek Vasut wrote: On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: Hi Marek, Hi! On 08/13/2015 09:42 AM, vikasm wrote: Hi Marek, On 08/12/2015 07:15 PM, Marek Vasut wrote: On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: This patch

Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-13 Thread Marek Vasut
On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote: Hi, On 08/13/2015 03:48 PM, Marek Vasut wrote: On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: Hi Marek, Hi! On 08/13/2015 09:42 AM, vikasm wrote: Hi Marek, On 08/12/2015 07:15 PM, Marek Vasut wrote: On

Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-13 Thread vikas
Hi Marek, On 08/13/2015 06:04 PM, Marek Vasut wrote: On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote: Hi, On 08/13/2015 03:48 PM, Marek Vasut wrote: On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: Hi Marek, Hi! On 08/13/2015 09:42 AM, vikasm wrote: Hi Marek, On

Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-13 Thread Marek Vasut
On Friday, August 14, 2015 at 03:39:22 AM, vikas wrote: Hi Marek, On 08/13/2015 06:04 PM, Marek Vasut wrote: On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote: Hi, On 08/13/2015 03:48 PM, Marek Vasut wrote: On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: Hi Marek,

Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-13 Thread Vikas MANOCHA
Hi, On Aug 13, 2015, at 6:57 PM, Marek Vasut ma...@denx.de wrote: On Friday, August 14, 2015 at 03:39:22 AM, vikas wrote: Hi Marek, On 08/13/2015 06:04 PM, Marek Vasut wrote: On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote: Hi, On 08/13/2015 03:48 PM, Marek Vasut wrote: On

Re: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-08-12 Thread Marek Vasut
On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: This patch is to separate the base trigger from the read/write transfer start addresses. This patch breaks the QSPI support on SoCFPGA. Base trigger register address (0x1c register) corresponds to the address which should be put

[U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address transfer start address

2015-07-15 Thread Vikas Manocha
This patch is to separate the base trigger from the read/write transfer start addresses. Base trigger register address (0x1c register) corresponds to the address which should be put on AHB bus to handle indirect transfer triggered before. To handle indirect transfer we need to issue addresses