On Wed, Sep 19, 2012 at 12:44:27AM +0200, Marek Vasut wrote:
> Dear Simon Glass,
>
> > Hi,
> >
> > On Tue, Sep 18, 2012 at 2:21 PM, Marek Vasut wrote:
> > > Dear Simon Glass,
> > >
> > >> Hi,
> > >>
> > >> On Tue, Sep 18, 2012 at 1:04 PM, Thierry Reding
> > >>
> > >> wrote:
> > >> > On Tue,
On Tue, Sep 18, 2012 at 11:20:30PM +0200, Marek Vasut wrote:
> Dear Thierry Reding,
>
> > On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
> > > Dear Thierry Reding,
> > >
> > > [...]
> > >
> > > > > Sure, but after you apply the bounce buffer, you can safely
> > > > > invalidate the
Dear Simon Glass,
> Hi,
>
> On Tue, Sep 18, 2012 at 2:21 PM, Marek Vasut wrote:
> > Dear Simon Glass,
> >
> >> Hi,
> >>
> >> On Tue, Sep 18, 2012 at 1:04 PM, Thierry Reding
> >>
> >> wrote:
> >> > On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
> >> >> Dear Thierry Reding,
> >>
Hi,
On Tue, Sep 18, 2012 at 2:21 PM, Marek Vasut wrote:
> Dear Simon Glass,
>
>> Hi,
>>
>> On Tue, Sep 18, 2012 at 1:04 PM, Thierry Reding
>>
>> wrote:
>> > On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
>> >> Dear Thierry Reding,
>> >>
>> >> [...]
>> >>
>> >> > > Sure, but after y
Dear Simon Glass,
> Hi,
>
> On Tue, Sep 18, 2012 at 1:04 PM, Thierry Reding
>
> wrote:
> > On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
> >> Dear Thierry Reding,
> >>
> >> [...]
> >>
> >> > > Sure, but after you apply the bounce buffer, you can safely
> >> > > invalidate the w
Dear Thierry Reding,
> On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
> > Dear Thierry Reding,
> >
> > [...]
> >
> > > > Sure, but after you apply the bounce buffer, you can safely
> > > > invalidate the whole cacheline, so align it up and be done with it.
> > >
> > > That's what
Hi,
On Tue, Sep 18, 2012 at 1:04 PM, Thierry Reding
wrote:
> On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
>> Dear Thierry Reding,
>>
>> [...]
>>
>> > > Sure, but after you apply the bounce buffer, you can safely invalidate
>> > > the whole cacheline, so align it up and be done wit
On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
> Dear Thierry Reding,
>
> [...]
>
> > > Sure, but after you apply the bounce buffer, you can safely invalidate
> > > the whole cacheline, so align it up and be done with it.
> >
> > That's what I proposed to do last time around but it
Dear Thierry Reding,
[...]
> > Sure, but after you apply the bounce buffer, you can safely invalidate
> > the whole cacheline, so align it up and be done with it.
>
> That's what I proposed to do last time around but it was NAK'ed.
By who?
> At the
> time I didn't ensure that the buffer was ac
On Tue, Sep 18, 2012 at 09:21:14PM +0200, Marek Vasut wrote:
> Dear Thierry Reding,
>
> > On Tue, Sep 18, 2012 at 08:37:44PM +0200, Marek Vasut wrote:
> > > Dear Simon Glass,
> > >
> > > > Hi Thierry,
> > > >
> > > > On Tue, Sep 18, 2012 at 7:54 AM, Thierry Reding
> > > >
> > > > wrote:
> > >
Dear Thierry Reding,
> On Tue, Sep 18, 2012 at 08:37:44PM +0200, Marek Vasut wrote:
> > Dear Simon Glass,
> >
> > > Hi Thierry,
> > >
> > > On Tue, Sep 18, 2012 at 7:54 AM, Thierry Reding
> > >
> > > wrote:
> > > > On Mon, Sep 17, 2012 at 02:39:01PM -0700, Simon Glass wrote:
> > > >> Hi Thierr
On Tue, Sep 18, 2012 at 08:37:44PM +0200, Marek Vasut wrote:
> Dear Simon Glass,
>
> > Hi Thierry,
> >
> > On Tue, Sep 18, 2012 at 7:54 AM, Thierry Reding
> >
> > wrote:
> > > On Mon, Sep 17, 2012 at 02:39:01PM -0700, Simon Glass wrote:
> > >> Hi Thierry,
> > >>
> > >> On Sat, Sep 15, 2012 at
Dear Simon Glass,
> Hi Thierry,
>
> On Tue, Sep 18, 2012 at 7:54 AM, Thierry Reding
>
> wrote:
> > On Mon, Sep 17, 2012 at 02:39:01PM -0700, Simon Glass wrote:
> >> Hi Thierry,
> >>
> >> On Sat, Sep 15, 2012 at 11:49 PM, Thierry Reding
> >>
> >> wrote:
> >> > On Sat, Sep 15, 2012 at 07:45:30
Hi Thierry,
On Tue, Sep 18, 2012 at 7:54 AM, Thierry Reding
wrote:
> On Mon, Sep 17, 2012 at 02:39:01PM -0700, Simon Glass wrote:
>> Hi Thierry,
>>
>> On Sat, Sep 15, 2012 at 11:49 PM, Thierry Reding
>> wrote:
>> > On Sat, Sep 15, 2012 at 07:45:30PM -0700, Simon Glass wrote:
>> >> Hi,
>> >>
>> >
On Mon, Sep 17, 2012 at 02:39:01PM -0700, Simon Glass wrote:
> Hi Thierry,
>
> On Sat, Sep 15, 2012 at 11:49 PM, Thierry Reding
> wrote:
> > On Sat, Sep 15, 2012 at 07:45:30PM -0700, Simon Glass wrote:
> >> Hi,
> >>
> >> On Sat, Sep 15, 2012 at 1:41 PM, Thierry Reding
> >> wrote:
> >> > On Sat,
Hi Thierry,
On Sat, Sep 15, 2012 at 11:49 PM, Thierry Reding
wrote:
> On Sat, Sep 15, 2012 at 07:45:30PM -0700, Simon Glass wrote:
>> Hi,
>>
>> On Sat, Sep 15, 2012 at 1:41 PM, Thierry Reding
>> wrote:
>> > On Sat, Sep 15, 2012 at 10:11:54PM +0200, Marek Vasut wrote:
>> >> Dear Thierry Reding,
>
On Sat, Sep 15, 2012 at 07:45:30PM -0700, Simon Glass wrote:
> Hi,
>
> On Sat, Sep 15, 2012 at 1:41 PM, Thierry Reding
> wrote:
> > On Sat, Sep 15, 2012 at 10:11:54PM +0200, Marek Vasut wrote:
> >> Dear Thierry Reding,
> >>
> >> > On Fri, Sep 14, 2012 at 08:53:32AM -0700, Simon Glass wrote:
> >>
Hi,
On Sat, Sep 15, 2012 at 1:41 PM, Thierry Reding
wrote:
> On Sat, Sep 15, 2012 at 10:11:54PM +0200, Marek Vasut wrote:
>> Dear Thierry Reding,
>>
>> > On Fri, Sep 14, 2012 at 08:53:32AM -0700, Simon Glass wrote:
>> > > Hi,
>> > >
>> > > On Wed, Sep 12, 2012 at 4:42 PM, Marek Vasut wrote:
>> >
Dear Thierry Reding,
> On Sat, Sep 15, 2012 at 10:11:54PM +0200, Marek Vasut wrote:
> > Dear Thierry Reding,
> >
> > > On Fri, Sep 14, 2012 at 08:53:32AM -0700, Simon Glass wrote:
> > > > Hi,
> > > >
> > > > On Wed, Sep 12, 2012 at 4:42 PM, Marek Vasut wrote:
> > > > > Dear Stephen Warren,
> >
On Sat, Sep 15, 2012 at 10:11:54PM +0200, Marek Vasut wrote:
> Dear Thierry Reding,
>
> > On Fri, Sep 14, 2012 at 08:53:32AM -0700, Simon Glass wrote:
> > > Hi,
> > >
> > > On Wed, Sep 12, 2012 at 4:42 PM, Marek Vasut wrote:
> > > > Dear Stephen Warren,
> > > >
> > > >> On 09/12/2012 04:38 PM,
On Sat, Sep 15, 2012 at 10:01:47PM +0200, Thierry Reding wrote:
> I think I traced this to the copying of CSD a while back. The problem is
> that the transferred buffer is 8 bytes, so there's no way to make it
> aligned properly. Unfortunately the entailing discussion did not yield a
> solution at
On Fri, Sep 14, 2012 at 08:53:32AM -0700, Simon Glass wrote:
> Hi,
>
> On Wed, Sep 12, 2012 at 4:42 PM, Marek Vasut wrote:
> > Dear Stephen Warren,
> >
> >> On 09/12/2012 04:38 PM, Marek Vasut wrote:
> >> > Dear Stephen Warren,
> >> >
> >> >> On 09/12/2012 10:19 AM, Tom Warren wrote:
> >> >>> Fol
Dear Thierry Reding,
> On Fri, Sep 14, 2012 at 08:53:32AM -0700, Simon Glass wrote:
> > Hi,
> >
> > On Wed, Sep 12, 2012 at 4:42 PM, Marek Vasut wrote:
> > > Dear Stephen Warren,
> > >
> > >> On 09/12/2012 04:38 PM, Marek Vasut wrote:
> > >> > Dear Stephen Warren,
> > >> >
> > >> >> On 09/12/2
Hi,
On Wed, Sep 12, 2012 at 4:42 PM, Marek Vasut wrote:
> Dear Stephen Warren,
>
>> On 09/12/2012 04:38 PM, Marek Vasut wrote:
>> > Dear Stephen Warren,
>> >
>> >> On 09/12/2012 10:19 AM, Tom Warren wrote:
>> >>> Folks,
>> >>>
>> >>> Stephen Warren has posted an internal bug regarding the cache
>
Dear Stephen Warren,
> On 09/12/2012 04:38 PM, Marek Vasut wrote:
> > Dear Stephen Warren,
> >
> >> On 09/12/2012 10:19 AM, Tom Warren wrote:
> >>> Folks,
> >>>
> >>> Stephen Warren has posted an internal bug regarding the cache
> >>> alignment 'warnings' seen on Tegra20 boards when accessing MM
On 09/12/2012 04:38 PM, Marek Vasut wrote:
> Dear Stephen Warren,
>
>> On 09/12/2012 10:19 AM, Tom Warren wrote:
>>> Folks,
>>>
>>> Stephen Warren has posted an internal bug regarding the cache
>>> alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's
>>> the gist:
>>>
>>> Executi
Dear Stephen Warren,
> On 09/12/2012 10:19 AM, Tom Warren wrote:
> > Folks,
> >
> > Stephen Warren has posted an internal bug regarding the cache
> > alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's
> > the gist:
> >
> > Executing "mmc dev 0" still yields cache warnings:
>
On 09/12/2012 10:19 AM, Tom Warren wrote:
> Folks,
>
> Stephen Warren has posted an internal bug regarding the cache
> alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's
> the gist:
>
> Executing "mmc dev 0" still yields cache warnings:
>
> Tegra20 (Harmony) # mmc dev 0
> ERR
Folks,
Stephen Warren has posted an internal bug regarding the cache
alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's
the gist:
Executing "mmc dev 0" still yields cache warnings:
Tegra20 (Harmony) # mmc dev 0
ERROR: v7_dcache_inval_range- stop address is not aligned- 0x3fb6
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