Hello Fabio and everybody,
just a quick update on this old email thread.
On Thu, Dec 02, 2021 at 05:14:28PM +0100, Francesco Dolcini wrote:
> In my tests adding 1ms delay after each MMDC register write seems to
> have a positive effect and this is going into the direction that using
>
Hello Fabio,
On Sat, Dec 04, 2021 at 11:29:23AM -0300, Fabio Estevam wrote:
> Back to your original instability issue: I suppose you are talking
> about colibri_imx6.c.
Both colibri/apalis imx6 are somehow affected.
> Does it work well if you convert it to the mx6_dram_cfg() scheme?
I have not
Hi Francesco,
On Fri, Dec 3, 2021 at 5:47 AM Francesco Dolcini
wrote:
> I think that this applies even with just one chip select, it is just
> prescribing a procedure and explicitly saying that it must be done for
> all the chip select in use, either 1 or 2.
According to the NXP application
On Thu, Dec 02, 2021 at 05:56:38PM -0300, Fabio Estevam wrote:
> The part that Francesco quoted:
>
> "A Precharge All command must be issued prior to the
> MRW command to ensure robust DDR initialization. This
> command is required to be issued to both chip selects if two
> chip selects are
Hello Fabio and Michael,
On Thu, Dec 02, 2021 at 09:36:44PM +0100, Michael Nazzareno Trimarchi wrote:
> On Thu, Dec 2, 2021 at 9:14 PM Fabio Estevam wrote:
> > On Thu, Dec 2, 2021 at 1:14 PM Francesco Dolcini
> > wrote:
> > > I'm a little bit puzzled at the moment, according to the iMX6
Hi Michael,
On Thu, Dec 2, 2021 at 5:36 PM Michael Nazzareno Trimarchi
wrote:
> The bootrom loads the dcd using some logic and you write the register
> in sequence.
> You don't respect the ddr initialization or this delay on MMDC
> according to 44.4.2.
> Is that not necessary?
I don't see in
Hi Fabio
On Thu, Dec 2, 2021 at 9:14 PM Fabio Estevam wrote:
>
> Hi Francesco,
>
> On Thu, Dec 2, 2021 at 1:14 PM Francesco Dolcini
> wrote:
> >
> > Hello Fabio, Tim and all,
> > in the last few weeks I have been debugging some sporadic i.MX6 board
> > boot failures (2020.07 U-Boot, if that
Hi Francesco,
On Thu, Dec 2, 2021 at 1:14 PM Francesco Dolcini
wrote:
>
> Hello Fabio, Tim and all,
> in the last few weeks I have been debugging some sporadic i.MX6 board
> boot failures (2020.07 U-Boot, if that matters) and we have some loose
> indication that they could be RAM related. The
Hello Fabio, Tim and all,
in the last few weeks I have been debugging some sporadic i.MX6 board
boot failures (2020.07 U-Boot, if that matters) and we have some loose
indication that they could be RAM related. The effect is that SPL is not
able to load U-Boot from the eMMC to DDR and
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