> -----Original Message-----
> From: Maniyam, Dinesh <dinesh.mani...@intel.com>
> Sent: Tuesday, 31 May, 2022 4:06 PM
> To: u-boot@lists.denx.de
> Cc: Chee, Tien Fong <tien.fong.c...@intel.com>; Hea, Kok Kiang
> <kok.kiang....@intel.com>; Gan, Yau Wai <yau.wai....@intel.com>; Kho,
> Sin Hui <sin.hui....@intel.com>; Lokanathan, Raaj
> <raaj.lokanat...@intel.com>; Maniyam, Dinesh
> <dinesh.mani...@intel.com>
> Subject: [PATCH] arm: dts: socfpga: agilex: Add freeze controller node
>
> From: Dinesh Maniyam <dinesh.mani...@intel.com>
>
> The freeze controller is required for FPGA partial reconfig.
> This node is disable on default.
> Enable this node via u-boot fdt command when needed.
>
> Signed-off-by: Yau Wai Gan <yau.wai....@intel.com>
> Signed-off-by: Dinesh Maniyam <dinesh.mani...@intel.com>
> ---
> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> index 6cac36a1fc..2400fad18a 100644
> --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> @@ -2,7 +2,7 @@
> /*
> * U-Boot additions
> *
> - * Copyright (C) 2019 Intel Corporation <www.intel.com>
> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
> */
>
> #include "socfpga_agilex-u-boot.dtsi"
> @@ -11,6 +11,15 @@
> aliases {
> spi0 = &qspi;
> i2c0 = &i2c1;
> + freeze_br0 = &freeze_controller;
> + };
> +
> + soc {
> + freeze_controller: freeze_controller@f9000450 {
> + compatible = "altr,freeze-bridge-controller";
> + reg = <0xf9000450 0x00000010>;
> + status = "disabled";
> + };
> };
>
> memory {
> --
> 2.26.2
Reviewed-by: Tien Fong Chee <tien.fong.c...@intel.com>
Regards
Tien Fong
