On 14/12/2020 14:12, Amit Tomer wrote:
> Hi,
>
> Thanks for having the detailed look and providing comments:
>
>> According to the datasheet the clock source could also be NAND_PLL,
>> depending on bit 9.
>> Both PLLs use the same rate calculation, so it's just matter of the PLL
>> address
Hi,
Thanks for having the detailed look and providing comments:
> According to the datasheet the clock source could also be NAND_PLL,
> depending on bit 9.
> Both PLLs use the same rate calculation, so it's just matter of the PLL
> address offset to use for covering both.
Ok, should I change
On 13/12/2020 09:44, Amit Singh Tomar wrote:
Hi,
> This commit adds SD/MMC clocks, and provides .set/get_rate callbacks
> for SD/MMC device present on Actions OWL S700 SoCs.
>
> Signed-off-by: Amit Singh Tomar
> ---
> drivers/clk/owl/clk_owl.c | 66
>
3 matches
Mail list logo
