Hi Lukas
於 2019年3月12日 週二 下午7:04寫道:
>
>
>
> > -Original Message-
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Wednesday, March 06, 2019 6:53 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer Dabbelt;
> > Alexander
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer
wrote:
>
> RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
> the previous boot stage. Machine mode firmware such as BBL and OpenSBI
> do this when starting their payload (U-Boot) in supervisor mode. If
> U-Boot is running in
On 3/5/19 2:54 PM, Lukas Auer wrote:
RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task
> -Original Message-
> From: Lukas Auer
> Sent: Wednesday, March 6, 2019 4:23 AM
> To: u-boot@lists.denx.de
> Cc: Atish Patra ; Anup Patel
> ; Bin Meng ; Andreas
> Schwab ; Palmer Dabbelt ;
> Alexander Graf ; Lukas Auer
> ; Rick Chen ; Anup
> Patel
> Subject: [PATCH v2 7/9] riscv: do
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