On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote:
> On 06/06/2017 10:26 AM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote:
> > >
> > > On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
On 06/06/2017 10:26 AM, Chee, Tien Fong wrote:
> On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote:
>> On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Enable FPGA driver build for SPL because FPGA driver is needed for
>>>
On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote:
> On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Enable FPGA driver build for SPL because FPGA driver is needed for
> > SPL
> > to configure and getting DDR up before
On 06/06/2017 08:35 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Enable FPGA driver build for SPL because FPGA driver is needed for SPL
> to configure and getting DDR up before loading U-boot into DDR and
> booting from there.
>
> FPGA driver build on
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