CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4)
architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ
to make it generic for exynos architecture.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
Changes for v2:
- None
Changes for v3:
This patchset add support for Samsung's SMDK5250 board based on
EXYNOS5250 based SoC. It also adds support for MMC SPL booting.
The porting is done by Samsung engineers at HQ in System LSI Team.
I am contributing in upstreaming the code for the board.
Based upon discussions following patches are
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
Changes for v2:
- This patch was part of EXYNOS: Add SMDK5250 board support
- Now it is seprated as SoC
This patch adds support for MMC SPL booting.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
Changes for v2:
- None
Changes for v3:
- None
Changes for v4:
- None
Changes for v5:
- None
Changes for v6:
- None
Changes for v7:
- None
SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
Changes for v2:
- This patch is bifurcated into borad support and SoC support
- Fixed typo: s/EEYNOS/EXYNOS
- Squashed patch SMDK5250: enable device tree
On 01/02/2012 20:31, Eric Nelson wrote:
Hi Mike,
My comment was the inverse: I can't test just the 'sf probe' updates
unless I
have the core SPI flash support for mx6qsabrelite.
AFAIK, the update to cmd_sf doesn't have any dependencies and of course
the README update doesn't.
Then I
Dear Wolfgang,
On Tuesday 17 January 2012 02:46 PM, Aneesh V wrote:
Dear Wolfgang,
On Wednesday 23 November 2011 03:33 PM, Sebastian Andrzej Siewior wrote:
* Wolfgang Denk | 2011-11-22 20:04:47 [+0100]:
Dear Sebastian Andrzej Siewior,
In message2022123007.ga5...@linutronix.de you
Hello Heiko and Sughosh,
On Wed, Feb 1, 2012 at 8:33 AM, Heiko Schocher h...@denx.de wrote:
Sughosh Ganu wrote:
On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch
christian.rie...@omicron.at wrote:
The V bit of the c1 register of CP15 should not be cleared
since the SoC has no valid memory
Hello Christian,
Christian Riesch wrote:
Hello Heiko and Sughosh,
On Wed, Feb 1, 2012 at 8:33 AM, Heiko Schocher h...@denx.de wrote:
Sughosh Ganu wrote:
On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch
christian.rie...@omicron.at wrote:
The V bit of the c1 register of CP15 should not
This patch adds support for the Calimain board from
OMICRON electronics GmbH. The board features a Texas Instruments AM1808
SoC, 128 MB DDR2 memory, and 64 MB NOR flash memory connected to CS2 and
CS3.
Signed-off-by: Christian Riesch christian.rie...@omicron.at
---
MAINTAINERS
Signed-off-by: Christian Riesch christian.rie...@omicron.at
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Acked-by: Heiko Schocher h...@denx.de
Tested-by: Heiko Schocher h...@denx.de
---
arch/arm/cpu/arm926ejs/start.S |5 -
1 files changed, 4 insertions(+), 1
Hi,
In this patchset I tried to put everything from the discussion
in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
Although this is the second version of this patchset, the version number
is v6 since Sughosh's patches were already v4.
Changes since v5:
- introduced
From: Sughosh Ganu urwithsugh...@gmail.com
The current implementation invalidates the data cache before turning it
off and causes problems on the hawkboard. See the discussion in
http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
According to the ARM926EJ-S Technical Reference
This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416
arm, arm926ejs: always do cpu critical inits since it impacts all
arm926ejs based configurations and caused problems, e.g., with
the hawkboard.
Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines
from the board
The V bit of the c1 register of CP15 should not be cleared on DA850
SoCs since they have no valid memory at 0x. This patch
introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
that allows setting the correct value for the V bit.
Signed-off-by: Christian Riesch
From: Sughosh Ganu urwithsugh...@gmail.com
This patch moves hawkboard to the new spl infrastructure from the
older nand_spl one.
Removed the hawkboard_nand_config build option -- The spl code now
gets compiled with hawkboard_config, after building the main u-boot
image, using the
The low level initialization code in
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for
DM644X SoCs only. This patch makes the lowlevel_init function in this
file a dummy function for SoCs other than DM644X.
Signed-off-by: Christian Riesch christian.rie...@omicron.at
Cc: Tom Rini
spl for OMAP4 does not use mmc read/write.
Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms where mmc
write/erase operation is not needed in spl.
Use these CONFIGS to remove write/erase code in mmc.c and omap_hsmmc.c
This reduces the spl size by ~1128 Bytes
Signed-off-by: Balaji T K
add support to read mac address for AM18x EVM manufactured from
Spectrum digital which have mac address stored in I2C EEPROM manfactured
by WINBOND. This patch reads mac address from I2C EEPROM and updates
environment variable if not set. Introduced a config option
CONFIG_MAC_ADDR_IN_EEPROM to
add support to read mac address for da850/L138 evm manufactued by
Logic PD which store mac address in SPI flash manufactued by ST
Microelectronics. This patch adds support to read mac address from
spi flash and set the mac address if it hasen't been set in environmet.
Introduced a config option
There are two da850 SOC based EVMs, one from Spectrum digital
and other from Logic PD. Boards from Spectrum digital have mac
address stored in I2C EEPROM and they have spi flash manufactured
by WINBOND. Boards from Logic PD store mac address in ST
Microelectronics SPI flash. This patch series adds
This patch series adds new command - 'clocks' for davinci family
of SOCs. This command prints CPU, DSP core and DDR frequency from
the u-boot prompt. Also, support for printing frequency info during
u-boot initialization is removed as it will delay u-boot coming up.
These patches have undergone a
remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer
required. This is because clock info will be printed as part
'clocks' command. Also avoid building of print_cpuinfo() function
for SPL framework.
Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com
Cc: Tom Rini tr...@ti.com
---
Add 'clocks' command to print various frequencies such as ARM
frequency, DSP core frequency and DDR frequency. Remove
print_cpuinfo() function as it is no longer required.
Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com
Cc: Tom Rini tr...@ti.com
---
arch/arm/cpu/arm926ejs/davinci/speed.c |
Move the clock related function from cpu.c to new file
speed.c. Eliminate volatile keyword usage which made no
justification and also to keep checkpatch.pl happy. Replace
REG instructions by readl.
Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com
Cc: Tom Rini tr...@ti.com
---
Hi,
Thank you for re-submitting the patchset!
On Thu, Feb 2, 2012 at 2:42 PM, Manjunath Hadli manjunath.ha...@ti.com wrote:
There are two da850 SOC based EVMs, one from Spectrum digital
and other from Logic PD. Boards from Spectrum digital have mac
address stored in I2C EEPROM and they have
On 02/02/2012 02:18 AM, Stefano Babic wrote:
On 01/02/2012 20:31, Eric Nelson wrote:
Hi Mike,
My comment was the inverse: I can't test just the 'sf probe' updates
unless I
have the core SPI flash support for mx6qsabrelite.
AFAIK, the update to cmd_sf doesn't have any dependencies and of
Hi Marek,
Ok, what happens if you replace mx28_dram_init() with:
while (!readl(0x8001c280))
mx28_mem_init();
It's not entirely clear what you'd like me to try: mx28_dram_init
is called in U-Boot, while mx28_mem_init is SPL code.
I have tried to link SPL objects along, but I'm getting
On Thu, Feb 2, 2012 at 6:04 AM, Balaji T K balaj...@ti.com wrote:
spl for OMAP4 does not use mmc read/write.
Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms where mmc
write/erase operation is not needed in spl.
Use these CONFIGS to remove write/erase code in mmc.c and omap_hsmmc.c
On Thursday 02 February 2012 04:18:45 Stefano Babic wrote:
On 01/02/2012 20:31, Eric Nelson wrote:
My comment was the inverse: I can't test just the 'sf probe' updates
unless I have the core SPI flash support for mx6qsabrelite.
AFAIK, the update to cmd_sf doesn't have any dependencies
On Thu, Feb 2, 2012 at 6:53 AM, Manjunath Hadli manjunath.ha...@ti.com wrote:
Add 'clocks' command to print various frequencies such as ARM
frequency, DSP core frequency and DDR frequency. Remove
print_cpuinfo() function as it is no longer required.
Signed-off-by: Manjunath Hadli
Tom,
On Thursday 02 February 2012 10:02 PM, Tom Rini wrote:
On Thu, Feb 2, 2012 at 6:04 AM, Balaji T Kbalaj...@ti.com wrote:
spl for OMAP4 does not use mmc read/write.
Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms where mmc
write/erase operation is not needed in spl.
Use these
On 2/2/12, Fabio Estevam feste...@gmail.com wrote:
2. Please grep the locations where hw_clkctrl_frac0 is assigned as
32-bit and change those as well.
Please do the same for hw_clkctrl_frac1 as well. There is one location
in clock.c where it is read as 32-bit.
Thanks,
Fabio Estevam
On Thu, Feb 2, 2012 at 9:48 AM, Aneesh V ane...@ti.com wrote:
Tom,
On Thursday 02 February 2012 10:02 PM, Tom Rini wrote:
On Thu, Feb 2, 2012 at 6:04 AM, Balaji T Kbalaj...@ti.com wrote:
spl for OMAP4 does not use mmc read/write.
Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms
2. Please grep the locations where hw_clkctrl_frac0 is assigned as
32-bit and change those as well.
Please do the same for hw_clkctrl_frac1 as well. There is one location
in clock.c where it is read as 32-bit.
I will check all hw_clkctrl_frac* register access, but tomorrow because
the
On Sat, Jan 28, 2012 at 12:25 PM, Thomas Weber tho...@tweber.de wrote:
From: Thomas Weber we...@corscience.de
Tricorder is a board which is very similar to the Devkit8000. It
is designed as a base platform for further medical devices.
On Tue, Jan 31, 2012 at 10:35 AM, Nicolas Dechesne n-deche...@ti.com wrote:
In 8775471bb, the call to timer_init() was removed from common code
and put in OMAP3 s_init() function. As a result the boot was broken
on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix
boot on all
On Tue, Jan 17, 2012 at 12:20 AM, Heiko Schocher h...@denx.de wrote:
- CONFIG_SYS_MMC_ENV_DEV, needed if environment on mmc
- wait for 1 second timer in board_late_init() only, if
timer is running.
- add UBI/UBIFS support
- add FIT images support
- menu support
- U-Boot max size now
Hello,
The following changes since commit 78936e6d110bbcfe6db3406456c16a7a174ae031:
Tom Rini (1):
OMAP3: Correct get_sdr_cs_offset mask
are available in the git repository at:
git://git.denx.de/u-boot-ti.git master
Dechesne, Nicolas (1):
OMAP SPL: Fix missing timer_init()
Hello everyone
im trying to port u-boot 2011-09 to a new board with an arm based SOC
i found that u-boot will always relocate the code even if it is placed
already in DDR which is the case with my SOC.
is there any clean way to avoid relocating the u-boot ? does the various SPL
configs have
On 2/2/12, Robert Deliën rob...@delien.nl wrote:
Ideally I'd like to set up these registers as uint8_t*. Any ideas? I'll also
check if bye-lane shifting is done automatically here.
You can write:
writeb(19 , clkctrl_regs-hw_clkctrl_frac0);
Regards,
Fabio Estevam
Hi,
This patch fixes ref_cpu clock setup. This bug leads to a hanging board
after rebooting from the Kernel, due to failing memory size detection:
U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00)
Freescale i.MX28 family
I2C: ready
DRAM: 0 Bytes
The cause of the bug is register
Hi,
In addition to my first patch, please consider accepting this patch too.
It prevents needless switching on and off PLL bypass mode and it
allow single stepping through the SPL.
Hi,
this is how the imx-bootlets does it though. It's likely that FSL wants the
PLL0
to run from XTAL when
Hello everyone
im trying to port u-boot 2011-09 to a new board with an arm based SOC
i found that u-boot will always relocate the code even if it is placed
already in DDR which is the case with my SOC.
The u-boot is always relocated to the end of the DRAM, which is likely what you
want.
On Wednesday 01 February 2012 20:18:09 Andy Fleming wrote:
Kumar, in connection with his imminent departure from Freescale, has
asked Wolfgang to step down from custodianship for U-Boot for 85xx and
86xx. As such, I will be re-assuming those duties. Please make sure to
copy me on all
On Thursday 02 February 2012 04:11:27 Chander Kashyap wrote:
--- /dev/null
+++ b/board/samsung/smdk5250/tools/mkexynos_image.c
tools should be in tools/. there are already plenty of examples in there (see
tools/msxboot.c as the first example i found by reading tools/Makefile).
+int main(int
On 01/24/2012 04:21 PM, Simon Glass wrote:
This adds a property to indicate a port which can switch between host and
device
mode.
...
diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt
b/doc/device-tree-bindings/usb/tegra-usb.txt
...
+Optional properties:
...
+ -
I am newbie in this. Anybody done it?
Any lead is appreciated.
Cheers,
Bud Miljkovic
-Original Message-
From: Marek Vasut [mailto:marek.va...@gmail.com]
Sent: Wednesday, 1 February 2012 11:58 p.m.
To: Wolfgang Denk
Cc: u-boot@lists.denx.de; Bud Miljkovic
Subject: Re: [U-Boot] Can
On 01/24/2012 04:21 PM, Simon Glass wrote:
This adds clock references to the USB part of the device tree for U-Boot.
The USB timing information may vary between boards sometimes, but for
now we hard-code it in C. This is because all current T2x boards use
the same values, we will deal with
On Thursday 02 February 2012 16:40:45 Bud Miljkovic wrote:
I am newbie in this. Anybody done it?
Any lead is appreciated.
please do not hijack threads. do not just pick a random e-mail and hit
reply. start a new one from scratch.
as for your question, check out the latest git. yaffs2 is
On 01/24/2012 04:21 PM, Simon Glass wrote:
This switches Seaboard over to use FDT for run-time config instead of
CONFIG options. USB is the only user at present.
Signed-off-by: Simon Glass s...@chromium.org
Aside from the issues I've just mentioned in my recent emails, and from
needing to
Dear Manjunath Hadli,
In message 1328190138-5276-3-git-send-email-manjunath.ha...@ti.com you wrote:
add support to read mac address for AM18x EVM manufactured from
Spectrum digital which have mac address stored in I2C EEPROM manfactured
by WINBOND. This patch reads mac address from I2C EEPROM
Bud
Last time I looked, the yaffs code in u-boot is pretty old and I would
recommend refreshing it.
-- Charles
On Friday 03 February 2012 10:40:45 Bud Miljkovic wrote:
I am newbie in this. Anybody done it?
Any lead is appreciated.
Cheers,
Bud Miljkovic
-Original Message-
From: Peter Meerwald p.meerw...@bct-electronic.com
Signed-off-by: Peter Meerwald p.meerw...@bct-electronic.com
---
doc/README.SPL |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/doc/README.SPL b/doc/README.SPL
index f01a8bd..0276953 100644
--- a/doc/README.SPL
+++
From: Peter Meerwald p.meerw...@bct-electronic.com
Signed-off-by: Peter Meerwald p.meerw...@bct-electronic.com
---
board/ti/beagle/beagle.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index 18bfaa8..c0a94a9
From: Peter Meerwald p.meerw...@bct-electronic.com
Signed-off-by: Peter Meerwald p.meerw...@bct-electronic.com
---
arch/arm/cpu/armv7/omap3/board.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
This devready func is only used in this driver, so mark it static.
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
drivers/mtd/nand/bfin_nand.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/nand/bfin_nand.c b/drivers/mtd/nand/bfin_nand.c
index
Added from Linux - commit 62aa2b537c6f5957afd98e29f96897419ed5ebab
Signed-off-by: Tom Rini tr...@ti.com
---
Makefile|5 ++
tools/checkstack.pl | 172 +++
2 files changed, 177 insertions(+), 0 deletions(-)
create mode 100755
Add the gigabit phy KSZ9021.
Also, add function ksz9021_phy_extended_write
/_read for access to the phys extended registers.
The environment variable disable_giga
can be used to disable 1000baseTx.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Acked-by: Dirk Behme
Define CONFIG_PHY_MICREL, and
minimize the tx clock delay.
There is an issue with 1000 baseTx mode on early revs
of the SabreLite boards. The center tap pin 9 of the mag RJ45
USB combo was connected to the 3.3 filtered supply. Letting
this pin float solved the problem. Symptoms of the problem
Boards may have things they want done before or after normal phy config.
Letting the boards call drv-config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Acked-by: Dirk Behme
Define CONFIG_FEC_QUIRK_ENET_MAC and add to
board files mx6qarm2 and mx6qsabrelite.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Acked-by: Dirk Behme dirk.be...@de.bosch.com
---
drivers/net/fec_mxc.c | 21 +++--
drivers/net/fec_mxc.h |2 ++
Surround non PHYLIB routines miiphy_restart_aneg
and miiphy_wait_aneg with ifndef CONFIG_PHYLIB.
When later PHYLIB is required it is easy to delete
the non-PHYLIB code. This separation idea
came from Andy Fleming.
fec_miiphy_read, and fec_miiphy_write changed to
fec_phy_read, and fec_phy_write
I have a pile of changes to u-boot that make yaffs work w/mtdparts (I.e.
ymount /partition looks through mtdparts to find start/end blocks, etc)
that works in u-boot-2011.06), and want to refresh that for a current u-boot,
but it's gonna take time to get it into acceptable shape for submission.
Hi Stefano,
I have cloned yesterday http://git.denx.de/u-boot.git on to my local
machine and from there selected the v2011.12-rc3 tag. Then I configured
the mx53loco board and successfully build u-boot.imx, copied the image
to a SD card and powered it up. What I then got on the serial port
Dear Charles Manning,
In message 201202031119.57323.mannin...@actrix.gen.nz you wrote:
Last time I looked, the yaffs code in u-boot is pretty old and I would
recommend refreshing it.
Patches are welcome!
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang
Bud,
2012/2/3 Bud Miljkovic bud_miljko...@trimble.com:
Hi Stefano,
I have cloned yesterday http://git.denx.de/u-boot.git on to my local
machine and from there selected the v2011.12-rc3 tag. Then I configured
the mx53loco board and successfully build u-boot.imx, copied the image
to a SD
On 03/02/2012 06:58, Jason Liu wrote:
Hi Bud,
I have cloned yesterday http://git.denx.de/u-boot.git on to my local
machine and from there selected the v2011.12-rc3 tag. Then I configured
the mx53loco board and successfully build u-boot.imx, copied the image
to a SD card and powered it up.
Albert,
Any suggestions?
Thanks
Amit Virdi
On 2/1/12, Amit Virdi amitvi...@gmail.com wrote:
Hi All,
I'm in the process of updating platform support for spear series of
SoC on the latest u-boot.
I picked u-boot v2011.12. I tried compiling for different spear boards
(spear 300, 310, 300 and
Adding Albert now...
On 2/3/12, Amit Virdi amitvi...@gmail.com wrote:
Albert,
Any suggestions?
Thanks
Amit Virdi
On 2/1/12, Amit Virdi amitvi...@gmail.com wrote:
Hi All,
I'm in the process of updating platform support for spear series of
SoC on the latest u-boot.
I picked u-boot
Hi,
This patch fixes ref_cpu clock setup. This bug leads to a hanging board
after rebooting from the Kernel, due to failing memory size detection:
U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00)
Freescale i.MX28 family
I2C: ready
DRAM: 0 Bytes
The cause of the bug is register
---
drivers/net/sh_eth.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 1bc44a8..8d3dac2 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -94,7 +94,6 @@ int sh_eth_send(struct eth_device *dev, volatile void
SH7734 has one channel ethernet device.
This support 10/100/1000Base, and RMII/MII/GMII.
And this has the same structure as SH7763.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 17 +-
drivers/net/sh_eth.h | 85
The r0p7734 board has SH7734, 128MB DDR2-SDRAM, USB,
Ethernet, and more.
This patch supports the following functions:
- 128MB DDR2-SDRAM
- 32MB NOR Flash memory
- Serial console (SCIF)
- Ethernet (SH-Ether/SMSC)
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
MAINTAINERS
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 27 +--
1 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index c1abe7c..e29061c 100644
--- a/drivers/net/sh_eth.c
+++
Hi,
on i.MX6 devices, e.g. ARM2 or SabreLite, the ROM boot loader copies the
U-Boot image from the boot device, e.g. the SD card, to the main memory.
This does mean that U-Boot is started in RAM.
With this, one might wonder why any relocation RAM - RAM is done anyway
and if this could be
Renesas SH7734 has two I2C interfaceis.
This supports these I2C.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/i2c/Makefile|1 +
drivers/i2c/sh_sh7734_i2c.c | 468 +++
2 files changed, 469 insertions(+), 0
r0p7734 board stores away MAC address in EEPROM.
This sets an MAC address to reading, environment variable
from an EEPROM by supporting I2C.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
board/renesas/r0p7734/r0p7734.c | 19 ++-
include/configs/r0p7734.h
78 matches
Mail list logo
