[U-Boot] MPC8555 pci issue
Hi all, we have a MPC8555 custom designed board, where we ported u-boot(1.3.1) and linux 2.6.24(without PCI). we have a pci-to-usb controller(32bit,33MHZ,PCI1 controller, IDSEL 18) on pci bus, if we enable the PCI in u-boot it is hanging while doing PCI enumeration, then we disabled PCI and tried to read the configuration data(vendor and device id) of the usb controller by giving following commands. $md 0xe0008000 0x80009000 $md 0xe0008004 then it is hanging, when we check the pci signals(frame, idsel, irdy, trdy etc) they seem to be proper, even the chip is responding with its vendor and device id(we could see then on the analyzer). what could be the problem. Regards, -- Ashok Kumar Kacham Member(Research Staff), Central Research Laboratory, Bharat Electronics Ltd, Bangalore-13. Every 3000 Sheets of paper costs us a tree.. Save trees... Conserve Trees. Don't print this email or any Files unless you really need to Confidentiality Notice The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain confidential or privileged information. If you are not the intended recipient, please notify the sender at Bharat Electronics or supp...@bel.co.in immediately and destroy all copies of this message and any attachments. Email secured by Check Point ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Rx FIFO: more than 64 bytes receive error
Hi , Thank you very much ,for the quick response albert The detailed explanation about the project is as below: I have a fingerprint module(FPC-AM3) which works fine and can receive whole fingerprint template data at kernel on UART2 of the processor. The same i am trying to implement at u-boot. I am trying to receive almost 1Kb of fingerprint template. Fingerprint template is received once we transmit a command of 6 bytes to fingerprint over UART2 to Fingerprint module, and then the response is 948 bytes of template data over UART2 on the Receive side. I went through the *loads* command too. If i am not wrong it takes the file from remote location and loads on to the address mentioned in the argument, which is not the idea. As explained before we are trying to receive 948 bytes of data from the UART2 port (Fingerprint module). Attaching the patch as suggested :patch includes our finger print code and the UART2 initialization change. Please help us in getting the 948 bytes of data over UART2. Let us know the code changes. *NOTE: we have even modified the hardware for a loopback connection and then ran the same code on it, but we could not receive more than 64 bytes. We are receiving the first 64 bytes and then rest of the bytes are not seen. * Thanks Regards, Lokesh On Sat, Dec 29, 2012 at 7:28 PM, Albert ARIBAUD albert.u.b...@aribaud.netwrote: Hi lokesh, On Sat, 29 Dec 2012 17:01:35 +0530, lokesh nijalinge lokesh1kumar2nijali...@gmail.com wrote: Hi, I am using the arm processor for my project and need to receive around 1K bytes of data over UART. I am able to receive only 64 bytes at U-boot, which is the UART RX FIFO size. After receiving the 64 bytes i am not getting any data. I read the Technical Reference Manual, which says the if more than FIFO size data is received then data will be lost instead of overwriting. Please let me know whether i need to configure any UART registers to achieve more than 64 bytes. *Details of the project:* Processor : DM3730 from Texas instruments -OMAP3 ARM Cortex UART device : NS16550 The default code having the UART initialization sequence posted below does not seem to take care of the handling of more than 64 bytes of RX data. Hmm... I can tell any U-Boot receives and correctly processes a lot more than 64 bytes without any issue; I routinely throw a lot more than this at the few U-Boot's I have lying around, all of which use NS16550-like serials. I even sometimes 'loads' a payload of several hundred bytes to some megs, without any issue. However, while 'loads' itself can handle very large serial input, the serial driver in itself will never handle more than the FIFO depth: the 'loads' command handler has to read from the driver frequently in order to avoid an overload. In your case, you did not describe (or did I miss it?) what it is that *uses* the received bytes, and how and when these received bytes are read from the driver. Can you elaborate on this? *Changes done by us to get the Data from RX fifo. * Please show such changes as a patch (made with got format-patch or at least git diff) -- with '[RFC]' in the message subject so that we know it is not a submission for inclusion into U-boot. Amicalement, -- Albert. -- Thanks Regards, Lokesh Kumar, custom_patch.patch Description: Binary data ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 1/9] FDT: Add compatible string for DWMMC
Add required compatible information for DWMMC driver.
Changes from V1:
No change.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index ce10bf4..dcd4142 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -76,6 +76,7 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */
COMPAT_WOLFSON_WM8994_CODEC,/* Wolfson WM8994 Sound Codec */
COMPAT_SAMSUNG_EXYNOS_SPI, /* Exynos SPI */
+ COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index aa75710..646d5d6 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -51,6 +51,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS5_SOUND, samsung,exynos-sound),
COMPAT(WOLFSON_WM8994_CODEC, wolfson,wm8994-codec),
COMPAT(SAMSUNG_EXYNOS_SPI, samsung,exynos-spi),
+ COMPAT(SAMSUNG_EXYNOS5_DWMMC, samsung,exynos5250-dwmmc),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
--
1.8.0
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[U-Boot] [PATCH V3 2/9] EXYNOS5: FDT: Add DWMMC device node data
This patch adds DWMMC device node data for exynos5.
This patch also adds binding file for DWMMC device node.
Changes from V1:
1)Added binding file for DWMMC device node at the location
doc/device-tree-bindings/exynos/dwmmc.txt.
2)Removed the propname 'index' from device node.
3)Prefixed the vendor name 'samsung' before propname in device node.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Signed-off-by: Amar amarendra...@samsung.comX
---
arch/arm/dts/exynos5250.dtsi | 32 +++
board/samsung/dts/exynos5250-smdk5250.dts | 22 +
doc/device-tree-bindings/exynos/dwmmc.txt | 29
3 files changed, 83 insertions(+)
create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index 1008797..b701ae5 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -138,4 +138,36 @@
reg = 0x131b 0x30;
interrupts = 0 130 0;
};
+
+ dwmmc@1220 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos5250-dwmmc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ };
+
+ dwmmc@1221 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos5250-dwmmc;
+ reg = 0x1221 0x1000;
+ interrupts = 0 76 0;
+ };
+
+ dwmmc@1222 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos5250-dwmmc;
+ reg = 0x1222 0x1000;
+ interrupts = 0 77 0;
+ };
+
+ dwmmc@1223 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = samsung,exynos5250-dwmmc;
+ reg = 0x1223 0x1000;
+ interrupts = 0 78 0;
+ };
};
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts
b/board/samsung/dts/exynos5250-smdk5250.dts
index a8e62da..9baf622 100644
--- a/board/samsung/dts/exynos5250-smdk5250.dts
+++ b/board/samsung/dts/exynos5250-smdk5250.dts
@@ -30,6 +30,10 @@
spi2 = /spi@12d4;
spi3 = /spi@131a;
spi4 = /spi@131b;
+ dwmmc0 = /dwmmc@1220;
+ dwmmc1 = /dwmmc@1221;
+ dwmmc2 = /dwmmc@1222;
+ dwmmc3 = /dwmmc@1223;
};
sromc@1225 {
@@ -59,4 +63,22 @@
compatible = wolfson,wm8994-codec;
};
};
+
+ dwmmc@1220 {
+ samsung,bus-width = 8;
+ samsung,timing = 1 3 3;
+ };
+
+ dwmmc@1221 {
+ status = disabled;
+ };
+
+ dwmmc@1222 {
+ samsung,bus-width = 4;
+ samsung,timing = 1 2 3;
+ };
+
+ dwmmc@1223 {
+ status = disabled;
+ };
};
diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt
b/doc/device-tree-bindings/exynos/dwmmc.txt
new file mode 100644
index 000..6232ad6
--- /dev/null
+++ b/doc/device-tree-bindings/exynos/dwmmc.txt
@@ -0,0 +1,29 @@
+* Exynos 5250 DWC_mobile_storage
+
+The Exynos 5250 provides DWC_mobile_storage interface which supports
+. Embedded Multimedia Cards (EMMC-version 4.5)
+. Secure Digital memory (SD mem-version 2.0)
+. Secure Digital I/O (SDIO-version 3.0)
+. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
+
+The Exynos 5250 DWC_mobile_storage provides four channels.
+SOC specific and Board specific properties are channel specific.
+
+Required SoC Specific Properties:
+
+- compatible: should be
+ - samsung,exynos5250-dwmmc: for exynos5250 platforms
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- interrupts: The interrupt number to the cpu.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- samsung,bus-width: The width of the bus used to interface the devices
+ supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
+- samsung,timing: The timing values to be written into the
+ Drv/sample clock selection register of corresponding channel.
--
1.8.0
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[U-Boot] [PATCH V3 4/9] EXYNOS5: DWMMC: Added FDT support for DWMMC
This patch adds FDT support for DWMMC, by reading the DWMMC node data
from the device tree and initialising DWMMC channels as per data
obtained from the node.
Changes from V1:
1)Updated code to have same signature for the function
exynos_dwmci_init() for both FDT and non-FDT versions.
2)Updated code to pass device_id parameter to the function
exynos5_mmc_set_clk_div() instead of index.
3)Updated code to decode the value of samsung,width from FDT.
4)Channel index is computed instead of getting from FDT.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
---
arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++
drivers/mmc/exynos_dw_mmc.c | 116 +--
include/dwmmc.h | 4 ++
3 files changed, 117 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h
b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b..40dcc7b 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -29,8 +29,12 @@
int exynos_dwmci_init(u32 regbase, int bus_width, int index);
+#ifdef CONFIG_OF_CONTROL
+unsigned int exynos_dwmmc_init(const void *blob);
+#else
static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() + (0x1 * index);
return exynos_dwmci_init(base, bus_width, index);
}
+#endif
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 72a31b7..541889f 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -19,39 +19,141 @@
*/
#include common.h
-#include malloc.h
#include dwmmc.h
+#include fdtdec.h
+#include libfdt.h
+#include malloc.h
#include asm/arch/dwmmc.h
#include asm/arch/clk.h
+#include asm/arch/pinmux.h
+
+#defineDWMMC_MAX_CH_NUM4
+#defineDWMMC_MAX_FREQ 5200
+#defineDWMMC_MIN_FREQ 40
+#defineDWMMC_MMC0_CLKSEL_VAL 0x03030001
+#defineDWMMC_MMC2_CLKSEL_VAL 0x03020001
static char *EXYNOS_NAME = EXYNOS DWMMC;
+u32 timing[3];
+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
static void exynos_dwmci_clksel(struct dwmci_host *host)
{
- u32 val;
- val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
- DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
+ dwmci_writel(host, DWMCI_CLKSEL, host-clksel_val);
+}
- dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+ return get_mmc_clk(dev_index);
}
int exynos_dwmci_init(u32 regbase, int bus_width, int index)
{
struct dwmci_host *host = NULL;
+ int dev_id = 0;
host = malloc(sizeof(struct dwmci_host));
if (!host) {
printf(dwmci_host malloc fail!\n);
return 1;
}
+ /* Convert index into corresponding peripheral ID */
+ dev_id = index + PERIPH_ID_SDMMC0;
+
+ /* set the clock divisor - clk_div_fsys for mmc */
+ if (exynos5_mmc_set_clk_div(dev_id)) {
+ debug(mmc clock div set failed\n);
+ return -1;
+ }
host-name = EXYNOS_NAME;
host-ioaddr = (void *)regbase;
host-buswidth = bus_width;
+#ifdef CONFIG_OF_CONTROL
+ host-clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+ DWMCI_SET_DRV_CLK(timing[1]) |
+ DWMCI_SET_DIV_RATIO(timing[2]));
+#else
+ if (0 == index)
+ host-clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+ if (2 == index)
+ host-clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+#endif
host-clksel = exynos_dwmci_clksel;
host-dev_index = index;
-
- add_dwmci(host, 5200, 40);
+ host-mmc_clk = exynos_dwmci_get_clk;
+ /* Add the mmc chennel to be registered with mmc core */
+ add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
return 0;
}
+#ifdef CONFIG_OF_CONTROL
+unsigned int exynos_dwmmc_init(const void *blob)
+{
+ u32 base;
+ int index, bus_width;
+ int node_list[DWMMC_MAX_CH_NUM];
+ int err = 0;
+ int dev_id, flag;
+ int count, i;
+
+ count = fdtdec_find_aliases_for_id(blob, dwmmc,
+ COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+ DWMMC_MAX_CH_NUM);
+
+ for (i = 0; i count; i++) {
+ int node = node_list[i];
+
+ if (node = 0)
+ continue;
+
+ /* Extract device id for each mmc channel */
+ dev_id = pinmux_decode_periph_id(blob, node);
+
+ /* Get the bus width from the device
[U-Boot] [PATCH V3 3/9] DWMMC: Initialise dwmci and resolve EMMC read write issues
This patch enumerates dwmci and set auto stop command during
dwmci initialisation.
EMMC read/write is not happening in current implementation
due to improper fifo size computation. Hence Modified the fifo size
computation to resolve EMMC read write issues.
Changes from V1:
1)Created the macros RX_WMARK_SHIFT and RX_WMARK_MASK in header file.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Amar amarendra...@samsung.com
---
drivers/mmc/dw_mmc.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 4070d4e..d8fa1a2 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -136,6 +136,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
return TIMEOUT;
}
timeout--;
+ mdelay(1);
}
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
@@ -314,7 +315,7 @@ static void dwmci_set_ios(struct mmc *mmc)
static int dwmci_init(struct mmc *mmc)
{
struct dwmci_host *host = (struct dwmci_host *)mmc-priv;
- u32 fifo_size, fifoth_val;
+ u32 fifo_size, fifoth_val, ier;
dwmci_writel(host, DWMCI_PWREN, 1);
@@ -323,6 +324,14 @@ static int dwmci_init(struct mmc *mmc)
return -1;
}
+ /* Enumerate at 400KHz */
+ dwmci_setup_bus(host, mmc-f_min);
+
+ /* Set auto stop command */
+ ier = dwmci_readl(host, DWMCI_CTRL);
+ ier |= (110);
+ dwmci_writel(host, DWMCI_CTRL, ier);
+
dwmci_writel(host, DWMCI_RINTSTS, 0x);
dwmci_writel(host, DWMCI_INTMASK, 0);
@@ -332,10 +341,11 @@ static int dwmci_init(struct mmc *mmc)
dwmci_writel(host, DWMCI_BMOD, 1);
fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+ fifo_size = ((fifo_size RX_WMARK_MASK) RX_WMARK_SHIFT) + 1;
if (host-fifoth_val)
fifoth_val = host-fifoth_val;
else
- fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
+ fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 - 1) |
TX_WMARK(fifo_size/2);
dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
--
1.8.0
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[U-Boot] [PATCH V3 0/9] EXYNOS5: Enable DWMMC, add FDT support for DWMMC and
This patch set enables and initialises DWMMC for Exynos5250 on SMDK5250. Adds driver changes required for DWMMC. Adds FDT support for DWMMC. Adds EMMC boot support for SMDK5250. This patch set is based on: EXYNOS: mmc: support DesignWare Controller for Samsung-SoC, which is merged in u-boot-mmc. Exynos: clock: support get_mmc_clk for exynos. Add DT based ethernet driver for SMDK5250. SMDK5250: Add FDT support present at the following link http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/149991 Changes from V1: 1)Corrected in response to review comments. 2)Created separate board files for FDT and non-FDT versions. 3)Added binding file for DWMMC device node. 4)Removed the propname 'index' from device node. 5)Prefixed the vendor name 'samsung' before propname in device node. 6)Ensured to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 7)EMMC clock setting has been moved from spl_boot.c to clock_init.c. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Amar (9): FDT: Add compatible string for DWMMC EXYNOS5: FDT: Add DWMMC device node data DWMMC: Initialise dwmci and resolve EMMC read write issues EXYNOS5: DWMMC: Added dt support for DWMMC EXYNOS5: DWMMC: API to set mmc clock divisor SMDK5250: Initialise and Enable DWMMC, support FDT and non-FDT MMC: APIs to support creation of boot partition SMDK5250: Enable EMMC booting COMMON: MMC: Command to support EMMC booting and boot partition creation arch/arm/cpu/armv7/exynos/clock.c | 38 - arch/arm/dts/exynos5250.dtsi | 32 arch/arm/include/asm/arch-exynos/clk.h| 4 + arch/arm/include/asm/arch-exynos/dwmmc.h | 4 + board/samsung/dts/exynos5250-smdk5250.dts | 22 +++ board/samsung/smdk5250/Makefile | 4 + board/samsung/smdk5250/clock_init.c | 15 ++ board/samsung/smdk5250/clock_init.h | 5 + board/samsung/smdk5250/exynos5-dt.c | 242 ++ board/samsung/smdk5250/smdk5250.c | 99 ++-- board/samsung/smdk5250/spl_boot.c | 52 ++- common/cmd_mmc.c | 84 ++- doc/device-tree-bindings/exynos/dwmmc.txt | 29 drivers/mmc/dw_mmc.c | 14 +- drivers/mmc/exynos_dw_mmc.c | 116 +- drivers/mmc/mmc.c | 118 +++ include/configs/exynos5250-dt.h | 2 + include/dwmmc.h | 4 + include/fdtdec.h | 1 + include/mmc.h | 16 ++ lib/fdtdec.c | 1 + 21 files changed, 827 insertions(+), 75 deletions(-) create mode 100644 board/samsung/smdk5250/exynos5-dt.c create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 6/9] SMDK5250: Initialise and Enable DWMMC, support FDT and non-FDT
This patch enables and initialises DWMMC for SMDK5250.
Supports both FDT and non-FDT. This patch creates a new file
'exynos5-dt.c' meant for FDT support.
exynos5-dt.c: This file shall contain all code which supports FDT.
Any addition of FDT support for any module needs to be
added in this file.
smdk5250.c: This file shall contain the code which supports non-FDT.
version. Any addition of non-FDT support for any module
needs to be added in this file.
May be, the file smdk5250.c can be removed in near
future
when non-FDT is not required.
The Makefile is updated to compile only one of the files
exynos5-dt.c / smdk5250.c based on FDT configuration.
NOTE:
Please note that all additions corresponding to FDT need to be added into the
file exynos5-dt.c.
At same time if non-FDT support is required then add the corresponding
updations into smdk5250.c.
Changes from V1:
1)A new file 'exynos5-dt.c' is created meant for FDT support
2)Makefile is updated to compile only one of the files
exynos5-dt.c / smdk5250.c based on FDT configuration
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Amar amarendra...@samsung.com
---
board/samsung/smdk5250/Makefile | 4 +
board/samsung/smdk5250/exynos5-dt.c | 242
board/samsung/smdk5250/smdk5250.c | 97 +++
include/configs/exynos5250-dt.h | 2 +
include/i2c.h | 2 +
5 files changed, 292 insertions(+), 55 deletions(-)
create mode 100644 board/samsung/smdk5250/exynos5-dt.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 47c6a5a..ecca9f3 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -32,8 +32,12 @@ COBJS+= tzpc_init.o
COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_OF_CONTROL
+COBJS += exynos5-dt.o
+else
COBJS += smdk5250.o
endif
+endif
ifdef CONFIG_SPL_BUILD
COBJS += spl_boot.o
diff --git a/board/samsung/smdk5250/exynos5-dt.c
b/board/samsung/smdk5250/exynos5-dt.c
new file mode 100644
index 000..da539ca
--- /dev/null
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include fdtdec.h
+#include asm/io.h
+#include i2c.h
+#include netdev.h
+#include spi.h
+#include asm/arch/cpu.h
+#include asm/arch/dwmmc.h
+#include asm/arch/gpio.h
+#include asm/arch/mmc.h
+#include asm/arch/pinmux.h
+#include asm/arch/sromc.h
+#include power/pmic.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd-bd-bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#ifdef CONFIG_EXYNOS_SPI
+ spi_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd-ram_size= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+ return 0;
+}
+
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+ if (pmic_init(I2C_PMIC))
+ return -1;
+ else
+ return 0;
+}
+#endif
+
+void dram_init_banksize(void)
+{
+ gd-bd-bi_dram[0].start = PHYS_SDRAM_1;
+ gd-bd-bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ gd-bd-bi_dram[1].start = PHYS_SDRAM_2;
+ gd-bd-bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+
[U-Boot] [PATCH V3 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor
This API computes the divisor value based on MPLL clock and
writes it into the FSYS1 register.
Changes from V1:
1)Updated the function exynos5_mmc_set_clk_div() to receive
'device_i'd as input parameter instead of 'index'.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Amar amarendra...@samsung.com
---
arch/arm/cpu/armv7/exynos/clock.c | 38 --
arch/arm/include/asm/arch-exynos/clk.h | 4
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 973b84e..cd42689 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -490,7 +490,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
- int shift;
+ int shift = 0;
sel = readl(clk-src_fsys);
sel = (sel (dev_index 2)) 0xf;
@@ -539,7 +539,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
- int shift;
+ int shift = 0;
sel = readl(clk-src_fsys);
sel = (sel (dev_index 2)) 0xf;
@@ -659,6 +659,40 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned
int div)
writel(val, addr);
}
+/* exynos5: set the mmc clock div ratio in fsys1 */
+int exynos5_mmc_set_clk_div(int dev_id)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int addr;
+ unsigned int clock;
+ unsigned int tmp;
+ unsigned int i;
+
+ /* get mpll clock */
+ clock = get_pll_clk(MPLL) / 100;
+
+ /*
+* CLK_DIV_FSYS1
+* MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0]
+* CLK_DIV_FSYS2
+* MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0]
+*/
+ if (dev_id = PERIPH_ID_SDMMC1)
+ addr = (unsigned int)clk-div_fsys1;
+ else
+ addr = (unsigned int)clk-div_fsys2;
+
+ tmp = readl(addr) ~FSYS1_MMC0_DIV_MASK;
+ for (i = 0; i = 0xf; i++) {
+ if ((clock / (i + 1)) = 400) {
+ writel(tmp | i 0, addr);
+ break;
+ }
+ }
+ return 0;
+}
+
/* get_lcd_clk: return lcd clock frequency */
static unsigned long exynos4_get_lcd_clk(void)
{
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index 1935b0b..2fd7c3e 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -29,6 +29,9 @@
#define VPLL 4
#define BPLL 5
+#define FSYS1_MMC0_DIV_MASK0xff0f
+#define FSYS1_MMC0_DIV_VAL 0x0701
+
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_i2c_clk(void);
@@ -36,6 +39,7 @@ unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
unsigned long get_mmc_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
+int exynos5_mmc_set_clk_div(int dev_index);
unsigned long get_lcd_clk(void);
void set_lcd_clk(void);
void set_mipi_clk(void);
--
1.8.0
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[U-Boot] [PATCH V3 7/9] MMC: APIs to support resize of EMMC boot partition
This patch adds APIs to open, close and to resize boot partiton for EMMC.
Changes from V1:
New patch.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Amar amarendra...@samsung.com
---
drivers/mmc/mmc.c | 118 ++
include/mmc.h | 16
2 files changed, 134 insertions(+)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 72e8ce6..8175b49 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1327,3 +1327,121 @@ int mmc_initialize(bd_t *bis)
return 0;
}
+
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+ unsigned long rpmbsize)
+{
+ int err;
+ struct mmc_cmd cmd;
+
+ /* Only use this command for raw EMMC moviNAND */
+ /* Enter backdoor mode */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = MMC_CMD62_ARG1;
+
+ err = mmc_send_cmd(mmc, cmd, NULL);
+ if (err) {
+ debug(mmc_boot_partition_size_change: Error1 = %d\n, err);
+ return err;
+ }
+
+ /* Boot partition changing mode */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = MMC_CMD62_ARG2;
+
+ err = mmc_send_cmd(mmc, cmd, NULL);
+ if (err) {
+ debug(mmc_boot_partition_size_change: Error2 = %d\n, err);
+ return err;
+ }
+ /* boot partition size is multiple of 128KB */
+ bootsize = ((bootsize*1024)/128);
+
+ /* Arg: boot partition size */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = bootsize;
+
+ err = mmc_send_cmd(mmc, cmd, NULL);
+ if (err) {
+ debug(mmc_boot_partition_size_change: Error3 = %d\n, err);
+ return err;
+ }
+ /* RPMB partition size is multiple of 128KB */
+ rpmbsize = ((rpmbsize*1024)/128);
+ /* Arg: RPMB partition size */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = rpmbsize;
+
+ err = mmc_send_cmd(mmc, cmd, NULL);
+ if (err) {
+ debug(mmc_boot_partition_size_change: Error4 = %d\n, err);
+ return err;
+ }
+ return 0;
+}
+
+int mmc_boot_open(struct mmc *mmc)
+{
+ int err;
+ struct mmc_cmd cmd;
+
+ /* Boot ack enable, boot partition enable , boot partition access */
+ cmd.cmdidx = MMC_CMD_SWITCH;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE 24 |
+ EXT_CSD_PART_CONF 16 |
+ (EXT_CSD_BOOT_ACK_ENABLE |
+ EXT_CSD_BOOT_PARTITION_ENABLE |
+ EXT_CSD_PARTITION_ACCESS_ENABLE) 8);
+
+ err = mmc_send_cmd(mmc, cmd, NULL);
+ if (err) {
+ debug(mmc_boot_open: Error1 = %d\n, err);
+ return err;
+ }
+
+ /* 4bit transfer mode at booting time. */
+ cmd.cmdidx = MMC_CMD_SWITCH;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE 24|
+ EXT_CSD_BOOT_BUS_WIDTH 16|
+ ((10) 8));
+
+ err = mmc_send_cmd(mmc, cmd, NULL);
+ if (err) {
+ debug(mmc_boot_open: Error2 = %d\n, err);
+ return err;
+ }
+
+ return 0;
+}
+
+int mmc_boot_close(struct mmc *mmc)
+{
+ int err;
+ struct mmc_cmd cmd;
+
+ /* Boot ack enable, boot partition enable , boot partition access */
+ cmd.cmdidx = MMC_CMD_SWITCH;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE 24|
+ EXT_CSD_PART_CONF 16|
+ (EXT_CSD_BOOT_ACK_ENABLE |
+ EXT_CSD_BOOT_PARTITION_ENABLE |
+ EXT_CSD_PARTITION_ACCESS_DISABLE) 8);
+
+ err = mmc_send_cmd(mmc, cmd, NULL);
+ if (err) {
+ debug(mmc_boot_close: Error = %d\n, err);
+ return err;
+ }
+
+ return 0;
+}
diff --git a/include/mmc.h b/include/mmc.h
index a13e2bd..999f0a3 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -86,6 +86,11 @@
#define MMC_CMD_APP_CMD55
#define MMC_CMD_SPI_READ_OCR 58
#define MMC_CMD_SPI_CRC_ON_OFF 59
+#define MMC_CMD_RES_MAN62
+
+#define MMC_CMD62_ARG1 0xefac62ec
+#define MMC_CMD62_ARG2 0xcbaea7
+
#define SD_CMD_SEND_RELATIVE_ADDR 3
#define SD_CMD_SWITCH_FUNC 6
@@ -153,6 +158,7 @@
*/
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
#define EXT_CSD_ERASE_GROUP_DEF175 /* R/W */
+#define EXT_CSD_BOOT_BUS_WIDTH 177
#define EXT_CSD_PART_CONF 179 /* R/W */
#define EXT_CSD_BUS_WIDTH
[U-Boot] [PATCH V3 8/9] SMDK5250: Enable EMMC booting
This patch adds support for EMMC booting on SMDK5250.
Changes from V1:
1)Updated spl_boot.c file to maintain irom pointer table
instead of using the #define values defined in header file.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Amar amarendra...@samsung.com
---
board/samsung/smdk5250/clock_init.c | 15 +++
board/samsung/smdk5250/clock_init.h | 5
board/samsung/smdk5250/spl_boot.c | 52 -
3 files changed, 65 insertions(+), 7 deletions(-)
diff --git a/board/samsung/smdk5250/clock_init.c
b/board/samsung/smdk5250/clock_init.c
index c009ae5..154993c 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -28,6 +28,7 @@
#include asm/arch/clk.h
#include asm/arch/clock.h
#include asm/arch/spl.h
+#include asm/arch/dwmmc.h
#include clock_init.h
#include setup.h
@@ -664,3 +665,17 @@ void clock_init_dp_clock(void)
/* We run DP at 267 Mhz */
setbits_le32(clk-div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
}
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
+ */
+void emmc_boot_clk_div_set(void)
+{
+ struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+ unsigned int div_mmc;
+
+ div_mmc = readl((unsigned int) clk-div_fsys1) ~FSYS1_MMC0_DIV_MASK;
+ div_mmc |= FSYS1_MMC0_DIV_VAL;
+ writel(div_mmc, (unsigned int) clk-div_fsys1);
+}
diff --git a/board/samsung/smdk5250/clock_init.h
b/board/samsung/smdk5250/clock_init.h
index f751bcb..20a1d47 100644
--- a/board/samsung/smdk5250/clock_init.h
+++ b/board/samsung/smdk5250/clock_init.h
@@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void);
* Initialize clock for the device
*/
void system_clock_init(void);
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ */
+void emmc_boot_clk_div_set(void);
#endif
diff --git a/board/samsung/smdk5250/spl_boot.c
b/board/samsung/smdk5250/spl_boot.c
index d8f3c1e..906e197 100644
--- a/board/samsung/smdk5250/spl_boot.c
+++ b/board/samsung/smdk5250/spl_boot.c
@@ -23,16 +23,38 @@
#includecommon.h
#includeconfig.h
+#include asm/arch-exynos/dmc.h
+#include asm/arch/clock.h
+#include asm/arch/clk.h
+
+#include clock_init.h
+
+/* Index into irom ptr table */
+enum index {
+ MMC_INDEX,
+ EMMC44_INDEX,
+ EMMC44_END_INDEX,
+ SPI_INDEX,
+};
+
+/* IROM Function Pointers Table */
+u32 irom_ptr_table[] = {
+ [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
+ [EMMC44_INDEX] = 0x02020044,/* iROM Function Pointer-EMMC4.4 boot*/
+ [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
+ -EMMC4.4 end boot operation */
+ [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
+ };
+
enum boot_mode {
BOOT_MODE_MMC = 4,
BOOT_MODE_SERIAL = 20,
+ BOOT_MODE_EMMC = 8, /* EMMC4.4 */
/* Boot based on Operating Mode pin settings */
BOOT_MODE_OM = 32,
BOOT_MODE_USB, /* Boot using USB download */
};
- typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
-
/*
* Copy U-boot from mmc to RAM:
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
@@ -40,23 +62,39 @@ enum boot_mode {
*/
void copy_uboot_to_ram(void)
{
- spi_copy_func_t spi_copy;
enum boot_mode bootmode;
- u32 (*copy_bl2)(u32, u32, u32);
-
+ u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst);
+ u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst);
+ u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
+ void (*end_bootop_from_emmc)(void);
+ /* read Operation Mode ststus register to find the bootmode */
bootmode = readl(EXYNOS5_POWER_BASE) OM_STAT;
switch (bootmode) {
case BOOT_MODE_SERIAL:
- spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR;
+ spi_copy = (void *) *(u32 *)irom_ptr_table[SPI_INDEX];
spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
CONFIG_SYS_TEXT_BASE);
break;
case BOOT_MODE_MMC:
- copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+ copy_bl2 = (void *) *(u32 *)irom_ptr_table[MMC_INDEX];
copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
CONFIG_SYS_TEXT_BASE);
break;
+ case BOOT_MODE_EMMC:
+ /* Set the FSYS1 clock divisor value for EMMC boot */
+ emmc_boot_clk_div_set();
+
+ copy_bl2_from_emmc =
+ (void *) *(u32 *)irom_ptr_table[EMMC44_INDEX];
+ end_bootop_from_emmc =
+ (void *) *(u32 *)irom_ptr_table[EMMC44_END_INDEX];
+
+
[U-Boot] [PATCH V3 9/9] COMMON: MMC: Command to support EMMC booting and to
This patch adds commands to open, close and resize boot partitions on EMMC.
Changes from V1:
1)Combined the common piece of code between 'open' and 'close'
operations.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Amar amarendra...@samsung.com
---
common/cmd_mmc.c | 84 +++-
1 file changed, 83 insertions(+), 1 deletion(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 7dacd51..1dabb5b 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -248,6 +248,84 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
curr_device, mmc-part_num);
return 0;
+ } else if ((strcmp(argv[1], open) == 0) ||
+ (strcmp(argv[1], close) == 0)) {
+ int dev;
+ struct mmc *mmc;
+
+ if (argc == 2)
+ dev = curr_device;
+ else if (argc == 3)
+ dev = simple_strtoul(argv[2], NULL, 10);
+ else
+ return CMD_RET_USAGE;
+
+ mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf(no mmc device at slot %x\n, dev);
+ return 1;
+ }
+
+ if (IS_SD(mmc)) {
+ printf(SD device cannot be opened/closed\n);
+ return 1;
+ }
+
+ if (strcmp(argv[1], open) == 0) {
+ if (!(mmc_boot_open(mmc))) {
+ printf(EMMC OPEN Success.\n);
+ printf(\t\t\t!!!Notice!!!\n);
+ printf(!You must close EMMC
+boot Partition after all
+images are written\n);
+ printf(!EMMC boot partition
+has continuity at
+image writing time.\n);
+ printf(!So, Do not close boot
+partition, Before, all
+images are written.\n);
+ return 0;
+ } else {
+ printf(EMMC OPEN Failed.\n);
+ return 1;
+ }
+ }
+
+ if (strcmp(argv[1], close) == 0) {
+ if (!(mmc_boot_close(mmc))) {
+ printf(EMMC CLOSE Success.\n);
+ return 0;
+ } else {
+ printf(EMMC CLOSE Failed.\n);
+ return 1;
+ }
+ }
+ } else if (strcmp(argv[1], bootpart) == 0) {
+ int dev;
+ dev = simple_strtoul(argv[2], NULL, 10);
+
+ u32 bootsize = simple_strtoul(argv[3], NULL, 10);
+ u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);
+ struct mmc *mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf(no mmc device at slot %x\n, dev);
+ return 1;
+ }
+
+ if (IS_SD(mmc)) {
+ printf(It is not a EMMC device\n);
+ return 1;
+ }
+
+ if (0 == mmc_boot_partition_size_change(mmc,
+ bootsize, rpmbsize)) {
+ printf(EMMC boot partition Size %d MB\n, bootsize);
+ printf(EMMC RPMB partition Size %d MB\n, rpmbsize);
+ return 0;
+ } else {
+ printf(EMMC boot partition Size change Failed.\n);
+ return 1;
+ }
}
state = MMC_INVALID;
@@ -317,5 +395,9 @@ U_BOOT_CMD(
mmc rescan\n
mmc part - lists available partition on current mmc device\n
mmc dev [dev] [part] - show or set current mmc device [partition]\n
- mmc list - lists available devices);
+ mmc list - lists available devices\n
+ mmc open device num - opens the specified device\n
+ mmc close device num - closes the specified device\n
+ mmc bootpart device num boot part size MB RPMB part size MB\n
+- change sizes of boot and RPMB partions of specified device\n);
#endif
--
1.8.0
___
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[U-Boot] [PATCH 01/12] cmd_sf: Add wr_inst argument to 'sf write' command
This patch provides a support to add a write instruction(wr_inst)
argument to 'sf write' command.
User will dynamically use the specific write instruction while
programming the flash using 'sf write' command.
Currently added an existing write instruction called pp(Page Program).
Example:
write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction.
u-boot sf write pp 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 36 +++--
drivers/mtd/spi/spi_flash.c |4 +-
drivers/mtd/spi/spi_flash_internal.h |2 +-
include/spi_flash.h | 10
include/spi_flash_inst.h | 30
5 files changed, 63 insertions(+), 19 deletions(-)
create mode 100644 include/spi_flash_inst.h
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index b175358..e7843f3 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -9,6 +9,7 @@
#include common.h
#include malloc.h
#include spi_flash.h
+#include spi_flash_inst.h
#include asm/io.h
@@ -234,20 +235,21 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
unsigned long len;
void *buf;
char *endp;
+ u8 wr_inst;
int ret;
- if (argc 4)
+ if (argc 5)
return -1;
- addr = simple_strtoul(argv[1], endp, 16);
- if (*argv[1] == 0 || *endp != 0)
- return -1;
- offset = simple_strtoul(argv[2], endp, 16);
+ addr = simple_strtoul(argv[2], endp, 16);
if (*argv[2] == 0 || *endp != 0)
return -1;
- len = simple_strtoul(argv[3], endp, 16);
+ offset = simple_strtoul(argv[3], endp, 16);
if (*argv[3] == 0 || *endp != 0)
return -1;
+ len = simple_strtoul(argv[4], endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ return -1;
/* Consistency checking */
if (offset + len flash-size) {
@@ -266,8 +268,17 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
ret = spi_flash_update(flash, offset, len, buf);
else if (strcmp(argv[0], read) == 0)
ret = spi_flash_read(flash, offset, len, buf);
- else
- ret = spi_flash_write(flash, offset, len, buf);
+ else {
+ if (strcmp(argv[1], pp) == 0)
+ wr_inst = CMD_PAGE_PROGRAM;
+ else {
+ printf(SF: Unknown %s wr_inst on 'sf write'\n,
+ argv[1]);
+ return 1;
+ }
+
+ ret = spi_flash_write(flash, wr_inst, offset, len, buf);
+ }
unmap_physmem(buf, len);
@@ -520,14 +531,17 @@ usage:
#endif
U_BOOT_CMD(
- sf, 5, 1, do_spi_flash,
+ sf, 6, 1, do_spi_flash,
SPI flash sub-system,
probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus\n
and chip select\n
sf read addr offset len- read `len' bytes starting at\n
`offset' to memory at `addr'\n
- sf write addr offset len - write `len' bytes from memory\n
-at `addr' to flash at `offset'\n
+ sf write wr_inst addr offset len\n
+ - write `len' bytes from memory\n
+at `addr' to flash at `offset'
using\n
+pp `wr_inst' write instruction\n
+pp (Page Program, 02h)\n
sf erase offset [+]len - erase `len' bytes from `offset'\n
`+len' round up `len' to block size\n
sf update addr offset len - erase and write `len' bytes from
memory\n
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 4dacdc7..8ba2c65 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -65,7 +65,7 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd,
size_t cmd_len,
return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
}
-int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
+int spi_flash_cmd_write_multi(struct spi_flash *flash, u8 wr_inst, u32 offset,
size_t len, const void *buf)
{
unsigned long page_addr, byte_addr, page_size;
@@ -83,7 +83,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
return ret;
}
- cmd[0] = CMD_PAGE_PROGRAM;
+ cmd[0] = wr_inst;
for (actual = 0; actual len; actual += chunk_len) {
chunk_len = min(len - actual, page_size - byte_addr);
diff --git a/drivers/mtd/spi/spi_flash_internal.h
[U-Boot] [PATCH 00/12] cmd_sf: Add support for read and write instructions
All these patches are added a support for read and write instruction for programming/reading SPI flash. Read and Write instruction are implemented as a command line arguments for 'sf write' , 'sf read' and 'sf update' commands. Currently I have added below instructions those are commonly available on all flash types. pp - Page Program (existing one) qpp - Quad-input Page Program afr - Array Fast Read (existing one) asr - Array Slow Read dofr - Dual Output Fast Read qofr - Quad Output Fast Read diofr - Dual IO Fast Read qiofr - Quad IO Fast Read I have tested mostly of the instruction on real h/w. This entire implementation will change the current sf framework little bit but I thought these changes are worth to add. Request for all your comment, so-that I can move forward. Please let me know for any issue regarding this new implementation. Thanks, Jagan. Jagannadha Sutradharudu Teki (12): cmd_sf: Add wr_inst argument to 'sf write' command cmd_sf: Add rd_inst argument to 'sf read' command cmd_sf: Add wr_inst argument to 'sf update' command cmd_sf: Add rd_inst argument to 'sf update' command cmd_sf: Define a functions for parsing read and write instructions cmd_sf: Add QPP(Quad-input Page Program) write instruction support cmd_sf: Add ASR(Array Slow Read) read instruction support cmd_sf: Add DOFR(Dual Output Fast Read) read instruction support cmd_sf: Add QOFR(Quad Output Fast Read) read instruction support cmd_sf: Add DIOFR(Dual IO Fast Read) read instruction support cmd_sf: Add QIOFR(Quad IO Fast Read) read instruction support sf: Pass rd_qeb_req variable as 0 for status and config reg reads common/cmd_sf.c | 198 +- drivers/mtd/spi/spi_flash.c | 40 +-- drivers/mtd/spi/spi_flash_internal.h | 10 +- include/spi_flash.h | 22 ++-- include/spi_flash_inst.h | 39 +++ 5 files changed, 257 insertions(+), 52 deletions(-) create mode 100644 include/spi_flash_inst.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/12] cmd_sf: Add rd_inst argument to 'sf read' command
This patch provides a support to add a read instruction(rd_inst)
argument to 'sf read' command.
User will dynamically use the specific read instruction while
reading the flash using 'sf read' command.
Currently added an existing read instruction called afr(Array Fast Read).
Example:
read 0x2000 length bytes starting at offset 0x0 to memory at 0x1
using afr read instruction.
u-boot sf read afr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 23 +--
drivers/mtd/spi/spi_flash.c |4 ++--
drivers/mtd/spi/spi_flash_internal.h |2 +-
include/spi_flash.h | 10 +-
include/spi_flash_inst.h |3 +++
5 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index e7843f3..88b18f8 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -235,7 +235,7 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
unsigned long len;
void *buf;
char *endp;
- u8 wr_inst;
+ u8 wr_inst, rd_inst;
int ret;
if (argc 5)
@@ -266,9 +266,17 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
if (strcmp(argv[0], update) == 0)
ret = spi_flash_update(flash, offset, len, buf);
- else if (strcmp(argv[0], read) == 0)
- ret = spi_flash_read(flash, offset, len, buf);
- else {
+ else if (strcmp(argv[0], read) == 0) {
+ if (strcmp(argv[1], afr) == 0)
+ rd_inst = CMD_READ_ARRAY_FAST;
+ else {
+ printf(SF: Unknown %s rd_inst on 'sf read'\n,
+ argv[1]);
+ return 1;
+ }
+
+ ret = spi_flash_read(flash, rd_inst, offset, len, buf);
+ } else {
if (strcmp(argv[1], pp) == 0)
wr_inst = CMD_PAGE_PROGRAM;
else {
@@ -535,8 +543,11 @@ U_BOOT_CMD(
SPI flash sub-system,
probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus\n
and chip select\n
- sf read addr offset len- read `len' bytes starting at\n
-`offset' to memory at `addr'\n
+ sf read rd_inst addr offset len\n
+ - read `len' bytes starting at\n
+`offset' to memory at `addr' using\n
+afr `rd_inst' read instruction\n
+afr (Array Fast Read, 0bh)\n
sf write wr_inst addr offset len\n
- write `len' bytes from memory\n
at `addr' to flash at `offset'
using\n
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 8ba2c65..0c64ac2 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -135,12 +135,12 @@ int spi_flash_read_common(struct spi_flash *flash, const
u8 *cmd,
return ret;
}
-int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
+int spi_flash_cmd_read_fast(struct spi_flash *flash, u8 rd_inst, u32 offset,
size_t len, void *data)
{
u8 cmd[5];
- cmd[0] = CMD_READ_ARRAY_FAST;
+ cmd[0] = rd_inst;
spi_flash_addr(offset, cmd);
cmd[4] = 0x00;
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 0d416b3..dcf8813 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -43,7 +43,7 @@ int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void
*response, size_t len);
int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len);
-int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
+int spi_flash_cmd_read_fast(struct spi_flash *flash, u8 rd_inst, u32 offset,
size_t len, void *data);
/*
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 9b3a6a1..6728796 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -39,8 +39,8 @@ struct spi_flash {
/* Erase (sector) size */
u32 sector_size;
- int (*read)(struct spi_flash *flash, u32 offset,
- size_t len, void *buf);
+ int (*read)(struct spi_flash *flash, u8 rd_inst,
+ u32 offset, size_t len, void *buf);
int (*write)(struct spi_flash *flash, u8 wr_inst,
u32 offset, size_t len, const void *buf);
int (*erase)(struct spi_flash *flash, u32 offset,
@@ -51,10 +51,10 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
[U-Boot] [PATCH 03/12] cmd_sf: Add wr_inst argument to 'sf update' command
This patch provides a support to add a write instruction(wr_inst)
argument to 'sf update' command.
User will dynamically use the specific write instruction while
programming the flash using 'sf update' command.
Currently added an existing write instruction called pp(Page Program).
Example:
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction.
u-boot sf update pp 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 37 ++---
1 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 88b18f8..0f4e440 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -141,6 +141,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
* If the data being written is the same, then *skipped is incremented by len.
*
* @param flashflash context pointer
+ * @param wr_inst write instruction
* @param offset flash offset to write
* @param len number of bytes to write
* @param buf buffer to write from
@@ -148,8 +149,9 @@ static int do_spi_flash_probe(int argc, char * const argv[])
* @param skipped Count of skipped data (incremented by this function)
* @return NULL if OK, else a string containing the stage which failed
*/
-static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset,
- size_t len, const char *buf, char *cmp_buf, size_t *skipped)
+static const char *spi_flash_update_block(struct spi_flash *flash, u8 wr_inst,
+ u32 offset, size_t len, const char *buf, char *cmp_buf,
+ size_t *skipped)
{
debug(offset=%#x, sector_size=%#x, len=%#zx\n,
offset, flash-sector_size, len);
@@ -163,7 +165,7 @@ static const char *spi_flash_update_block(struct spi_flash
*flash, u32 offset,
}
if (spi_flash_erase(flash, offset, len))
return erase;
- if (spi_flash_write(flash, offset, len, buf))
+ if (spi_flash_write(flash, wr_inst, offset, len, buf))
return write;
return NULL;
}
@@ -173,12 +175,13 @@ static const char *spi_flash_update_block(struct
spi_flash *flash, u32 offset,
* to change. Existing blocks with the correct data are left unchanged.
*
* @param flashflash context pointer
+ * @param wr_inst write instruction
* @param offset flash offset to write
* @param len number of bytes to write
* @param buf buffer to write from
* @return 0 if ok, 1 on error
*/
-static int spi_flash_update(struct spi_flash *flash, u32 offset,
+static int spi_flash_update(struct spi_flash *flash, u8 wr_inst, u32 offset,
size_t len, const char *buf)
{
const char *err_oper = NULL;
@@ -206,8 +209,9 @@ static int spi_flash_update(struct spi_flash *flash, u32
offset,
start_time));
last_update = get_timer(0);
}
- err_oper = spi_flash_update_block(flash, offset, todo,
- buf, cmp_buf, skipped);
+ err_oper = spi_flash_update_block(flash, wr_inst,
+ offset, todo, buf, cmp_buf,
+ skipped);
}
} else {
err_oper = malloc;
@@ -264,9 +268,17 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
return 1;
}
- if (strcmp(argv[0], update) == 0)
- ret = spi_flash_update(flash, offset, len, buf);
- else if (strcmp(argv[0], read) == 0) {
+ if (strcmp(argv[0], update) == 0) {
+ if (strcmp(argv[1], pp) == 0)
+ wr_inst = CMD_PAGE_PROGRAM;
+ else {
+ printf(SF: Unknown %s wr_inst on 'sf update'\n,
+ argv[1]);
+ return 1;
+ }
+
+ ret = spi_flash_update(flash, wr_inst, offset, len, buf);
+ } else if (strcmp(argv[0], read) == 0) {
if (strcmp(argv[1], afr) == 0)
rd_inst = CMD_READ_ARRAY_FAST;
else {
@@ -555,7 +567,10 @@ U_BOOT_CMD(
pp (Page Program, 02h)\n
sf erase offset [+]len - erase `len' bytes from `offset'\n
`+len' round up `len' to block size\n
- sf update addr offset len - erase and write `len' bytes from
memory\n
-at `addr' to flash at `offset'
+ sf update wr_inst addr offset len\n
+ - erase and write `len' bytes from
memory\n
+at `addr' to
[U-Boot] [PATCH 05/12] cmd_sf: Define a functions for parsing read and write instructions
This patch provides to define a separate functions for parsing read
and write instructions by taking instruction argument from user.
So-that the common functions can used in a different levels for
parsing read and write instructions.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 70 ++
1 files changed, 54 insertions(+), 16 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 4cfd48a..d59ecce 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -234,6 +234,48 @@ static int spi_flash_update(struct spi_flash *flash, u8
wr_inst, u8 rd_inst,
return 0;
}
+/*
+ * This function parsed the write instruction for write operation
+ *
+ * Input:
+ *arg: specified write instruction from user
+ * Output:
+ *wr_inst: parsed write instruction for write operation
+ * Return:
+ *1: for Unknown wr_inst from user
+ *0: Success
+ */
+static int sf_parse_wr_inst_arg(char *arg, u8 *wr_inst)
+{
+ if (strcmp(arg, pp) == 0)
+ *wr_inst = CMD_PAGE_PROGRAM;
+ else
+ return 1;
+
+ return 0;
+}
+
+/*
+ * This function parsed the read instruction for read operation
+ *
+ * Input:
+ *arg: specified read instruction from user
+ * Output:
+ *rd_inst: parsed read instruction for write operation
+ * Return:
+ *1: for Unknown rd_inst from user
+ *0: Success
+ */
+static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst)
+{
+ if (strcmp(arg, afr) == 0)
+ *rd_inst = CMD_READ_ARRAY_FAST;
+ else
+ return 1;
+
+ return 0;
+}
+
static int do_spi_flash_read_write(int argc, char * const argv[])
{
unsigned long addr;
@@ -281,41 +323,37 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
}
if (strcmp(argv[0], update) == 0) {
- if (strcmp(argv[1], pp) == 0)
- wr_inst = CMD_PAGE_PROGRAM;
- else {
+ ret = sf_parse_wr_inst_arg(argv[1], wr_inst);
+ if (ret) {
printf(SF: Unknown %s wr_inst on 'sf update'\n,
argv[1]);
- return 1;
+ return ret;
}
- if (strcmp(argv[2], afr) == 0)
- rd_inst = CMD_READ_ARRAY_FAST;
- else {
+ ret = sf_parse_rd_inst_arg(argv[2], rd_inst);
+ if (ret) {
printf(SF: Unknown %s rd_inst on 'sf update'\n,
argv[2]);
- return 1;
+ return ret;
}
ret = spi_flash_update(flash, wr_inst, rd_inst,
offset, len, buf);
} else if (strcmp(argv[0], read) == 0) {
- if (strcmp(argv[1], afr) == 0)
- rd_inst = CMD_READ_ARRAY_FAST;
- else {
+ ret = sf_parse_rd_inst_arg(argv[1], rd_inst);
+ if (ret) {
printf(SF: Unknown %s rd_inst on 'sf read'\n,
argv[1]);
- return 1;
+ return ret;
}
ret = spi_flash_read(flash, rd_inst, offset, len, buf);
} else {
- if (strcmp(argv[1], pp) == 0)
- wr_inst = CMD_PAGE_PROGRAM;
- else {
+ ret = sf_parse_wr_inst_arg(argv[1], wr_inst);
+ if (ret) {
printf(SF: Unknown %s wr_inst on 'sf write'\n,
argv[1]);
- return 1;
+ return ret;
}
ret = spi_flash_write(flash, wr_inst, offset, len, buf);
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/12] cmd_sf: Add rd_inst argument to 'sf update' command
This patch provides a support to add a read instruction(rd_inst)
argument to 'sf update' command.
User will dynamically use the specific read instruction while
reading the flash using 'sf update' command.
Currently added an existing read instruction called afr(Array Fast Read).
Example:
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction and afr read instruction.
u-boot sf update pp afr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 63 +-
1 files changed, 43 insertions(+), 20 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 0f4e440..4cfd48a 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -142,6 +142,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
*
* @param flashflash context pointer
* @param wr_inst write instruction
+ * @param rd_inst read instruction
* @param offset flash offset to write
* @param len number of bytes to write
* @param buf buffer to write from
@@ -150,12 +151,12 @@ static int do_spi_flash_probe(int argc, char * const
argv[])
* @return NULL if OK, else a string containing the stage which failed
*/
static const char *spi_flash_update_block(struct spi_flash *flash, u8 wr_inst,
- u32 offset, size_t len, const char *buf, char *cmp_buf,
- size_t *skipped)
+ u8 rd_inst, u32 offset, size_t len, const char *buf,
+ char *cmp_buf, size_t *skipped)
{
debug(offset=%#x, sector_size=%#x, len=%#zx\n,
offset, flash-sector_size, len);
- if (spi_flash_read(flash, offset, len, cmp_buf))
+ if (spi_flash_read(flash, rd_inst, offset, len, cmp_buf))
return read;
if (memcmp(cmp_buf, buf, len) == 0) {
debug(Skip region %x size %zx: no change\n,
@@ -176,13 +177,14 @@ static const char *spi_flash_update_block(struct
spi_flash *flash, u8 wr_inst,
*
* @param flashflash context pointer
* @param wr_inst write instruction
+ * @param rd_inst read instruction
* @param offset flash offset to write
* @param len number of bytes to write
* @param buf buffer to write from
* @return 0 if ok, 1 on error
*/
-static int spi_flash_update(struct spi_flash *flash, u8 wr_inst, u32 offset,
- size_t len, const char *buf)
+static int spi_flash_update(struct spi_flash *flash, u8 wr_inst, u8 rd_inst,
+ u32 offset, size_t len, const char *buf)
{
const char *err_oper = NULL;
char *cmp_buf;
@@ -210,8 +212,8 @@ static int spi_flash_update(struct spi_flash *flash, u8
wr_inst, u32 offset,
last_update = get_timer(0);
}
err_oper = spi_flash_update_block(flash, wr_inst,
- offset, todo, buf, cmp_buf,
- skipped);
+ rd_inst, offset, todo, buf,
+ cmp_buf, skipped);
}
} else {
err_oper = malloc;
@@ -240,19 +242,29 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
void *buf;
char *endp;
u8 wr_inst, rd_inst;
+ int update_rd_inst;
int ret;
- if (argc 5)
- return -1;
+ if (strcmp(argv[0], update) == 0) {
+ if (argc 6)
+ return -1;
- addr = simple_strtoul(argv[2], endp, 16);
- if (*argv[2] == 0 || *endp != 0)
+ update_rd_inst = 1;
+ } else {
+ if (argc 5)
+ return -1;
+
+ update_rd_inst = 0;
+ }
+
+ addr = simple_strtoul(argv[update_rd_inst + 2], endp, 16);
+ if (*argv[update_rd_inst + 2] == 0 || *endp != 0)
return -1;
- offset = simple_strtoul(argv[3], endp, 16);
- if (*argv[3] == 0 || *endp != 0)
+ offset = simple_strtoul(argv[update_rd_inst + 3], endp, 16);
+ if (*argv[update_rd_inst + 3] == 0 || *endp != 0)
return -1;
- len = simple_strtoul(argv[4], endp, 16);
- if (*argv[4] == 0 || *endp != 0)
+ len = simple_strtoul(argv[update_rd_inst + 4], endp, 16);
+ if (*argv[update_rd_inst + 4] == 0 || *endp != 0)
return -1;
/* Consistency checking */
@@ -277,7 +289,16 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
return 1;
}
- ret = spi_flash_update(flash, wr_inst, offset, len, buf);
+ if (strcmp(argv[2], afr) == 0)
+ rd_inst = CMD_READ_ARRAY_FAST;
+ else {
+ printf(SF: Unknown %s rd_inst
[U-Boot] [PATCH 07/12] cmd_sf: Add ASR(Array Slow Read) read instruction support
This patch provides a support to read a flash using 'asr'
read instruction(rd_inst) for 'sf read' and 'sf update' commands.
'asr' is similar to afr(Array Fast Read) except that it's
operated under slow speeds.
Example:
read 0x2000 length bytes starting at offset 0x0 to memory at 0x1
using asr read instruction.
u-boot sf read asr 0x1 0x0 0x2000
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction and asr read instruction.
u-boot sf update pp asr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 10 +++---
include/spi_flash_inst.h |1 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index b1f19ef..3d9c93e 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -279,6 +279,8 @@ static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst)
{
if (strcmp(arg, afr) == 0)
*rd_inst = CMD_READ_ARRAY_FAST;
+ else if (strcmp(arg, asr) == 0)
+ *rd_inst = CMD_READ_ARRAY_SLOW;
else
return 1;
@@ -628,8 +630,9 @@ U_BOOT_CMD(
sf read rd_inst addr offset len\n
- read `len' bytes starting at\n
`offset' to memory at `addr' using\n
-afr `rd_inst' read instruction\n
+afr | asr `rd_inst' read
instructions\n
afr (Array Fast Read, 0bh)\n
+asr (Array Slow Read, 02b)\n
sf write wr_inst addr offset len\n
- write `len' bytes from memory\n
at `addr' to flash at `offset'
using\n
@@ -644,7 +647,8 @@ U_BOOT_CMD(
pp | qpp `wr_inst' write instructions
and\n
pp (Page Program, 02h)\n
qpp (Quad Page Program, 32h)\n
-afr `rd_inst' read instruction\n
-afr (Array Fast Read, 0bh)
+afr | asr `rd_inst' read
instructions\n
+afr (Array Fast Read, 0bh)\n
+asr (Array Slow Read, 02b)
SF_TEST_HELP
);
diff --git a/include/spi_flash_inst.h b/include/spi_flash_inst.h
index a530842..85c8e70 100644
--- a/include/spi_flash_inst.h
+++ b/include/spi_flash_inst.h
@@ -30,5 +30,6 @@
/* Read commands */
#define CMD_READ_ARRAY_FAST0x0b
+#define CMD_READ_ARRAY_SLOW0x03
#endif /* _SPI_FLASH_INST_H_ */
--
1.7.0.4
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[U-Boot] [PATCH 06/12] cmd_sf: Add QPP(Quad-input Page Program) write instruction support
This patch provides a support to program a flash using 'qpp'
write instruction(wr_inst) for 'sf write' and 'sf update' commands.
'qpp' will effectively increases the data transfer rate
by up to four times, as compared to the pp( Page Program).
Example:
write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using qpp write instruction.
u-boot sf write qpp 0x1 0x0 0x2000
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using qpp write instruction and afr read instruction.
u-boot sf update qpp afr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 41 ++---
drivers/mtd/spi/spi_flash.c | 12 -
drivers/mtd/spi/spi_flash_internal.h |4 +-
include/spi_flash.h |7 +++--
include/spi_flash_inst.h |1 +
5 files changed, 44 insertions(+), 21 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index d59ecce..b1f19ef 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -143,6 +143,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
* @param flashflash context pointer
* @param wr_inst write instruction
* @param rd_inst read instruction
+ * @param wr_qeb_req quad enable bit is required for this write operation?
* @param offset flash offset to write
* @param len number of bytes to write
* @param buf buffer to write from
@@ -151,8 +152,8 @@ static int do_spi_flash_probe(int argc, char * const argv[])
* @return NULL if OK, else a string containing the stage which failed
*/
static const char *spi_flash_update_block(struct spi_flash *flash, u8 wr_inst,
- u8 rd_inst, u32 offset, size_t len, const char *buf,
- char *cmp_buf, size_t *skipped)
+ u8 rd_inst, u8 wr_qeb_req, u32 offset, size_t len,
+ const char *buf, char *cmp_buf, size_t *skipped)
{
debug(offset=%#x, sector_size=%#x, len=%#zx\n,
offset, flash-sector_size, len);
@@ -166,7 +167,7 @@ static const char *spi_flash_update_block(struct spi_flash
*flash, u8 wr_inst,
}
if (spi_flash_erase(flash, offset, len))
return erase;
- if (spi_flash_write(flash, wr_inst, offset, len, buf))
+ if (spi_flash_write(flash, wr_inst, wr_qeb_req, offset, len, buf))
return write;
return NULL;
}
@@ -178,13 +179,14 @@ static const char *spi_flash_update_block(struct
spi_flash *flash, u8 wr_inst,
* @param flashflash context pointer
* @param wr_inst write instruction
* @param rd_inst read instruction
+ * @param wr_qeb_req quad enable bit is required for this write operation?
* @param offset flash offset to write
* @param len number of bytes to write
* @param buf buffer to write from
* @return 0 if ok, 1 on error
*/
static int spi_flash_update(struct spi_flash *flash, u8 wr_inst, u8 rd_inst,
- u32 offset, size_t len, const char *buf)
+ u8 wr_qeb_req, u32 offset, size_t len, const char *buf)
{
const char *err_oper = NULL;
char *cmp_buf;
@@ -212,7 +214,8 @@ static int spi_flash_update(struct spi_flash *flash, u8
wr_inst, u8 rd_inst,
last_update = get_timer(0);
}
err_oper = spi_flash_update_block(flash, wr_inst,
- rd_inst, offset, todo, buf,
+ rd_inst, wr_qeb_req,
+ offset, todo, buf,
cmp_buf, skipped);
}
} else {
@@ -241,15 +244,21 @@ static int spi_flash_update(struct spi_flash *flash, u8
wr_inst, u8 rd_inst,
*arg: specified write instruction from user
* Output:
*wr_inst: parsed write instruction for write operation
+ *wr_qeb_req: assign to 1 if this instruction require quad enable bit
+ * need to set prior to actual write operation
* Return:
*1: for Unknown wr_inst from user
*0: Success
*/
-static int sf_parse_wr_inst_arg(char *arg, u8 *wr_inst)
+static int sf_parse_wr_inst_arg(char *arg, u8 *wr_inst, u8 *wr_qeb_req)
{
- if (strcmp(arg, pp) == 0)
+ if (strcmp(arg, pp) == 0) {
*wr_inst = CMD_PAGE_PROGRAM;
- else
+ *wr_qeb_req = 0;
+ } else if (strcmp(arg, qpp) == 0) {
+ *wr_inst = CMD_QUAD_PAGE_PROGRAM;
+ *wr_qeb_req = 1;
+ } else
return 1;
return 0;
@@ -284,6 +293,7 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
void *buf;
char *endp;
u8 wr_inst, rd_inst;
+ u8 wr_qeb_req;
int update_rd_inst;
int ret;
@@ -323,7 +333,7 @@
[U-Boot] [PATCH 08/12] cmd_sf: Add DOFR(Dual Output Fast Read) read instruction support
This patch provides a support to read a flash using 'dofr' read instruction(rd_inst) for 'sf read' and 'sf update' commands. 'dofr' will effectively increases the data transfer rate by up to two times, as compared to the afr(Array Fast Read). Example: read 0x2000 length bytes starting at offset 0x0 to memory at 0x1 using dofr read instruction. u-boot sf read dofr 0x1 0x0 0x2000 erase and write 0x2000 length bytes from memory at 0x1 address to flash offset at 0x0 using pp write instruction and dofr read instruction. u-boot sf update pp dofr 0x1 0x0 0x2000 Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com --- common/cmd_sf.c | 10 +++--- include/spi_flash_inst.h |1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 3d9c93e..b971d2a 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -281,6 +281,8 @@ static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst) *rd_inst = CMD_READ_ARRAY_FAST; else if (strcmp(arg, asr) == 0) *rd_inst = CMD_READ_ARRAY_SLOW; + else if (strcmp(arg, dofr) == 0) + *rd_inst = CMD_READ_DUAL_OUTPUT_FAST; else return 1; @@ -630,9 +632,10 @@ U_BOOT_CMD( sf read rd_inst addr offset len\n - read `len' bytes starting at\n `offset' to memory at `addr' using\n -afr | asr `rd_inst' read instructions\n +afr | asr | dofr `rd_inst' read instructions\n afr (Array Fast Read, 0bh)\n asr (Array Slow Read, 02b)\n +dofr (Dual Output Fast Read, 3bh)\n sf write wr_inst addr offset len\n - write `len' bytes from memory\n at `addr' to flash at `offset' using\n @@ -647,8 +650,9 @@ U_BOOT_CMD( pp | qpp `wr_inst' write instructions and\n pp (Page Program, 02h)\n qpp (Quad Page Program, 32h)\n -afr | asr `rd_inst' read instructions\n +afr | asr | dofr `rd_inst' read instructions\n afr (Array Fast Read, 0bh)\n -asr (Array Slow Read, 02b) +asr (Array Slow Read, 02b)\n +dofr (Dual Output Fast Read, 3bh) SF_TEST_HELP ); diff --git a/include/spi_flash_inst.h b/include/spi_flash_inst.h index 85c8e70..f8fcf5e 100644 --- a/include/spi_flash_inst.h +++ b/include/spi_flash_inst.h @@ -31,5 +31,6 @@ /* Read commands */ #define CMD_READ_ARRAY_FAST0x0b #define CMD_READ_ARRAY_SLOW0x03 +#define CMD_READ_DUAL_OUTPUT_FAST 0x3b #endif /* _SPI_FLASH_INST_H_ */ -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/12] cmd_sf: Add QOFR(Quad Output Fast Read) read instruction support
This patch provides a support to read a flash using 'qofr'
read instruction(rd_inst) for 'sf read' and 'sf update' commands.
'qofr' will effectively increases the data transfer rate
by up to four times, as compared to the afr(Array Fast Read).
Example:
read 0x2000 length bytes starting at offset 0x0 to memory at 0x1
using qofr read instruction.
u-boot sf read qofr 0x1 0x0 0x2000
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction and qofr read instruction.
u-boot sf update pp qofr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 43 ++
drivers/mtd/spi/spi_flash.c | 18 +++---
drivers/mtd/spi/spi_flash_internal.h |6 ++--
include/spi_flash.h |7 +++--
include/spi_flash_inst.h |1 +
5 files changed, 50 insertions(+), 25 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index b971d2a..a07effd 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -144,6 +144,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
* @param wr_inst write instruction
* @param rd_inst read instruction
* @param wr_qeb_req quad enable bit is required for this write operation?
+ * @param rd_qeb_req quad enable bit is required for this read operation?
* @param offset flash offset to write
* @param len number of bytes to write
* @param buf buffer to write from
@@ -152,12 +153,12 @@ static int do_spi_flash_probe(int argc, char * const
argv[])
* @return NULL if OK, else a string containing the stage which failed
*/
static const char *spi_flash_update_block(struct spi_flash *flash, u8 wr_inst,
- u8 rd_inst, u8 wr_qeb_req, u32 offset, size_t len,
- const char *buf, char *cmp_buf, size_t *skipped)
+ u8 rd_inst, u8 wr_qeb_req, u8 rd_qeb_req, u32 offset,
+ size_t len, const char *buf, char *cmp_buf, size_t *skipped)
{
debug(offset=%#x, sector_size=%#x, len=%#zx\n,
offset, flash-sector_size, len);
- if (spi_flash_read(flash, rd_inst, offset, len, cmp_buf))
+ if (spi_flash_read(flash, rd_inst, rd_qeb_req, offset, len, cmp_buf))
return read;
if (memcmp(cmp_buf, buf, len) == 0) {
debug(Skip region %x size %zx: no change\n,
@@ -180,13 +181,15 @@ static const char *spi_flash_update_block(struct
spi_flash *flash, u8 wr_inst,
* @param wr_inst write instruction
* @param rd_inst read instruction
* @param wr_qeb_req quad enable bit is required for this write operation?
+ * @param rd_qeb_req quad enable bit is required for this read operation?
* @param offset flash offset to write
* @param len number of bytes to write
* @param buf buffer to write from
* @return 0 if ok, 1 on error
*/
static int spi_flash_update(struct spi_flash *flash, u8 wr_inst, u8 rd_inst,
- u8 wr_qeb_req, u32 offset, size_t len, const char *buf)
+ u8 wr_qeb_req, u8 rd_qeb_req, u32 offset,
+ size_t len, const char *buf)
{
const char *err_oper = NULL;
char *cmp_buf;
@@ -214,7 +217,7 @@ static int spi_flash_update(struct spi_flash *flash, u8
wr_inst, u8 rd_inst,
last_update = get_timer(0);
}
err_oper = spi_flash_update_block(flash, wr_inst,
- rd_inst, wr_qeb_req,
+ rd_inst, wr_qeb_req, rd_qeb_req,
offset, todo, buf,
cmp_buf, skipped);
}
@@ -271,19 +274,26 @@ static int sf_parse_wr_inst_arg(char *arg, u8 *wr_inst,
u8 *wr_qeb_req)
*arg: specified read instruction from user
* Output:
*rd_inst: parsed read instruction for write operation
+ *rd_qeb_req: assign to 1 if this instruction require quad enable bit
+ * need to set prior to actual read operation
* Return:
*1: for Unknown rd_inst from user
*0: Success
*/
-static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst)
+static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst, u8 *rd_qeb_req)
{
+ *rd_qeb_req = 0;
+
if (strcmp(arg, afr) == 0)
*rd_inst = CMD_READ_ARRAY_FAST;
else if (strcmp(arg, asr) == 0)
*rd_inst = CMD_READ_ARRAY_SLOW;
else if (strcmp(arg, dofr) == 0)
*rd_inst = CMD_READ_DUAL_OUTPUT_FAST;
- else
+ else if (strcmp(arg, qofr) == 0) {
+ *rd_inst = CMD_READ_QUAD_OUTPUT_FAST;
+ *rd_qeb_req = 1;
+ } else
return 1;
return 0;
@@ -297,7 +307,7 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
void
[U-Boot] [PATCH 10/12] cmd_sf: Add DIOFR(Dual IO Fast Read) read instruction support
This patch provides a support to read a flash using 'diofr'
read instruction(rd_inst) for 'sf read' and 'sf update' commands.
'diofr' is similar to the dofr(Dual Output Fast Read) except that it
improves performance throughput by allowing input of the
address bits using two bits per SCK via two input pins.
Example:
read 0x2000 length bytes starting at offset 0x0 to memory at 0x1
using diofr read instruction.
u-boot sf read diofr 0x1 0x0 0x2000
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction and diofr read instruction.
u-boot sf update pp diofr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c | 10 +++---
include/spi_flash_inst.h |1 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index a07effd..5ced1cc 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -293,7 +293,9 @@ static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst, u8
*rd_qeb_req)
else if (strcmp(arg, qofr) == 0) {
*rd_inst = CMD_READ_QUAD_OUTPUT_FAST;
*rd_qeb_req = 1;
- } else
+ } else if (strcmp(arg, diofr) == 0)
+ *rd_inst = CMD_READ_DUAL_IO_FAST;
+ else
return 1;
return 0;
@@ -648,6 +650,7 @@ U_BOOT_CMD(
asr (Array Slow Read, 02b)\n
dofr (Dual Output Fast Read, 3bh)\n
qofr (Quad Output Fast Read, 6bh)\n
+diofr (Dual Input/Output Fast Read,
bbh)\n
sf write wr_inst addr offset len\n
- write `len' bytes from memory\n
at `addr' to flash at `offset'
using\n
@@ -662,10 +665,11 @@ U_BOOT_CMD(
pp | qpp `wr_inst' write instructions
and\n
pp (Page Program, 02h)\n
qpp (Quad Page Program, 32h)\n
-afr | asr | dofr | qofr `rd_inst'
read instructions\n
+afr | asr | dofr | qofr | diofr
`rd_inst' read instructions\n
afr (Array Fast Read, 0bh)\n
asr (Array Slow Read, 02b)\n
dofr (Dual Output Fast Read, 3bh)\n
-qofr (Quad Output Fast Read, 6bh)
+qofr (Quad Output Fast Read, 6bh)\n
+diofr (Dual Input/Output Fast Read,
bbh)
SF_TEST_HELP
);
diff --git a/include/spi_flash_inst.h b/include/spi_flash_inst.h
index 67b22c8..e718e8e 100644
--- a/include/spi_flash_inst.h
+++ b/include/spi_flash_inst.h
@@ -33,5 +33,6 @@
#define CMD_READ_ARRAY_SLOW0x03
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
+#define CMD_READ_DUAL_IO_FAST 0xbb
#endif /* _SPI_FLASH_INST_H_ */
--
1.7.0.4
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[U-Boot] [PATCH 11/12] cmd_sf: Add QIOFR(Quad IO Fast Read) read instruction support
This patch provides a support to read a flash using 'qiofr'
read instruction(rd_inst) for 'sf read' and 'sf update' commands.
'qiofr' is similar to the qofr(Quad Output Fast Read) except that it
improves performance throughput by allowing input of the
address bits using four bits per SCK via four input pins.
Example:
read 0x2000 length bytes starting at offset 0x0 to memory at 0x1
using qiofr read instruction.
u-boot sf read qiofr 0x1 0x0 0x2000
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction and qiofr read instruction.
u-boot sf update pp qiofr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
common/cmd_sf.c |9 +++--
include/spi_flash_inst.h |1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 5ced1cc..cd76f28 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -295,7 +295,10 @@ static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst, u8
*rd_qeb_req)
*rd_qeb_req = 1;
} else if (strcmp(arg, diofr) == 0)
*rd_inst = CMD_READ_DUAL_IO_FAST;
- else
+ else if (strcmp(arg, qiofr) == 0) {
+ *rd_inst = CMD_READ_QUAD_IO_FAST;
+ *rd_qeb_req = 1;
+ } else
return 1;
return 0;
@@ -651,6 +654,7 @@ U_BOOT_CMD(
dofr (Dual Output Fast Read, 3bh)\n
qofr (Quad Output Fast Read, 6bh)\n
diofr (Dual Input/Output Fast Read,
bbh)\n
+qiofr (Quad Input/Output Fast Read,
ebh)\n
sf write wr_inst addr offset len\n
- write `len' bytes from memory\n
at `addr' to flash at `offset'
using\n
@@ -670,6 +674,7 @@ U_BOOT_CMD(
asr (Array Slow Read, 02b)\n
dofr (Dual Output Fast Read, 3bh)\n
qofr (Quad Output Fast Read, 6bh)\n
-diofr (Dual Input/Output Fast Read,
bbh)
+diofr (Dual Input/Output Fast Read,
bbh)\n
+qiofr (Quad Input/Output Fast Read,
ebh)
SF_TEST_HELP
);
diff --git a/include/spi_flash_inst.h b/include/spi_flash_inst.h
index e718e8e..556e179 100644
--- a/include/spi_flash_inst.h
+++ b/include/spi_flash_inst.h
@@ -34,5 +34,6 @@
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_DUAL_IO_FAST 0xbb
+#define CMD_READ_QUAD_IO_FAST 0xeb
#endif /* _SPI_FLASH_INST_H_ */
--
1.7.0.4
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[U-Boot] [PATCH 12/12] sf: Pass rd_qeb_req variable as 0 for status and config reg reads
Config and Status register reads doesn't require to set
the quad enable bit, hence rd_qeb_req variable passed as 0.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/spi_flash.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 15ad05c..7a15a69 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -293,7 +293,8 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, void
*data)
int ret;
cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash, cmd, sizeof(cmd), (void *)data, 1);
+ ret = spi_flash_read_common(flash, cmd, 0,
+ sizeof(cmd), (void *)data, 1);
if (ret 0) {
debug(SF: fail to read status register\n);
return ret;
@@ -343,7 +344,8 @@ int spi_flash_cmd_read_config(struct spi_flash *flash, void
*data)
int ret;
cmd = CMD_READ_CONFIG;
- ret = spi_flash_read_common(flash, cmd, sizeof(cmd), (void *)data, 1);
+ ret = spi_flash_read_common(flash, cmd, 0,
+ sizeof(cmd), (void *)data, 1);
if (ret 0) {
debug(SF: fail to read config register\n);
return ret;
--
1.7.0.4
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Re: [U-Boot] [PATCH 1/4] SMDK5250: Convert lowlevel_init.S to lowlevel_init_c.c
On Fri, Dec 28, 2012 at 9:08 PM, Rajeshwari Shinde
rajeshwar...@samsung.com wrote:
This patch converts lowlevel_init.S to lowlevel_init_c.c for
SMDK5250.
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
board/samsung/smdk5250/Makefile |1 +
board/samsung/smdk5250/dmc_common.c |4 +-
board/samsung/smdk5250/dmc_init_ddr3.c |6 ++-
board/samsung/smdk5250/lowlevel_init.S | 69 ++---
board/samsung/smdk5250/lowlevel_init_c.c | 70
++
board/samsung/smdk5250/setup.h | 17 ++-
board/samsung/smdk5250/spl_boot.c| 52 ++
spl/Makefile |4 ++
8 files changed, 142 insertions(+), 81 deletions(-)
create mode 100644 board/samsung/smdk5250/lowlevel_init_c.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 47c6a5a..b99ac7f 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -37,6 +37,7 @@ endif
ifdef CONFIG_SPL_BUILD
COBJS += spl_boot.o
+COBJS += lowlevel_init_c.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/samsung/smdk5250/dmc_common.c
b/board/samsung/smdk5250/dmc_common.c
index 109602a..6a26822 100644
--- a/board/samsung/smdk5250/dmc_common.c
+++ b/board/samsung/smdk5250/dmc_common.c
@@ -175,7 +175,7 @@ void dmc_config_memory(struct mem_timings *mem, struct
exynos5_dmc *dmc)
writel(DMC_MEMBASECONFIG1_VAL, dmc-membaseconfig1);
}
-void mem_ctrl_init()
+void mem_ctrl_init(int mem_reset)
does 'reset' is enough?
{
struct spl_machine_param *param = spl_get_machine_params();
struct mem_timings *mem;
@@ -185,7 +185,7 @@ void mem_ctrl_init()
/* If there are any other memory variant, add their init call below */
if (param-mem_type == DDR_MODE_DDR3) {
- ret = ddr3_mem_ctrl_init(mem, param-mem_iv_size);
+ ret = ddr3_mem_ctrl_init(mem, param-mem_iv_size, mem_reset);
if (ret) {
/* will hang if failed to init memory control */
while (1)
diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c
b/board/samsung/smdk5250/dmc_init_ddr3.c
index e050790..4e0693d 100644
--- a/board/samsung/smdk5250/dmc_init_ddr3.c
+++ b/board/samsung/smdk5250/dmc_init_ddr3.c
@@ -40,7 +40,8 @@ static void reset_phy_ctrl(void)
writel(DDR3PHY_CTRL_PHY_RESET, clk-lpddr3phy_ctrl);
}
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+ int mem_reset)
ditto
{
unsigned int val;
struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
@@ -51,7 +52,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned
long mem_iv_size)
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
- reset_phy_ctrl();
+ if (mem_reset)
if (reset)
+ reset_phy_ctrl();
/* Set Impedance Output Driver */
val = (mem-impedance CA_CK_DRVR_DS_OFFSET) |
diff --git a/board/samsung/smdk5250/lowlevel_init.S
b/board/samsung/smdk5250/lowlevel_init.S
index bc6cb6f..469126d 100644
--- a/board/samsung/smdk5250/lowlevel_init.S
+++ b/board/samsung/smdk5250/lowlevel_init.S
@@ -23,74 +23,13 @@
*/
#include config.h
-#include version.h
#include asm/arch/cpu.h
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
.globl lowlevel_init
lowlevel_init:
-
- /* use iRAM stack in bl2 */
- ldr sp, =CONFIG_IRAM_STACK
- stmdb r13!, {ip,lr}
-
- /* check reset status */
- ldr r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
- ldr r1, [r0]
-
- /* AFTR wakeup reset */
- ldr r2, =S5P_CHECK_DIDLE
- cmp r1, r2
- beq exit_wakeup
-
- /* LPA wakeup reset */
- ldr r2, =S5P_CHECK_LPA
- cmp r1, r2
- beq exit_wakeup
-
- /* Sleep wakeup reset */
- ldr r2, =S5P_CHECK_SLEEP
- cmp r1, r2
- beq wakeup_reset
-
/*
-* If U-boot is already running in RAM, no need to relocate U-Boot.
-* Memory controller must be configured before relocating U-Boot
-* in ram.
+* Set the stack pointer, although it will be overwriten by the caller
+* It seems we will not boot if this function is empty.
*/
- ldr r0, =0x0ff /* r0 - Mask Bits*/
- bic r1, pc, r0 /* pc - current addr of code */
- /* r1 - unmasked bits of pc */
- ldr r2, _TEXT_BASE /* r2 - original base addr in ram */
- bic r2, r2, r0 /* r2 - unmasked bits of r2*/
- cmp
Re: [U-Boot] [PATCH V3 1/9] FDT: Add compatible string for DWMMC
Hi,
On Mon, Dec 31, 2012 at 7:58 PM, Amar amarendra...@samsung.com wrote:
Add required compatible information for DWMMC driver.
Changes from V1:
No change.
Changes from V2:
1)Updation of commit message and resubmition of proper patch set.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index ce10bf4..dcd4142 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -76,6 +76,7 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */
COMPAT_WOLFSON_WM8994_CODEC,/* Wolfson WM8994 Sound Codec */
COMPAT_SAMSUNG_EXYNOS_SPI, /* Exynos SPI */
+ COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
You already know that exynos4 series also have DWMMC controller and
it's strange to use this value at exynos4 series.
so can you use 'SAMSUNG_EXYNOS_DWMMC'?
Thank you,
Kyungmin Park
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index aa75710..646d5d6 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -51,6 +51,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS5_SOUND, samsung,exynos-sound),
COMPAT(WOLFSON_WM8994_CODEC, wolfson,wm8994-codec),
COMPAT(SAMSUNG_EXYNOS_SPI, samsung,exynos-spi),
+ COMPAT(SAMSUNG_EXYNOS5_DWMMC, samsung,exynos5250-dwmmc),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
--
1.8.0
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[U-Boot] [PATCH v2 1/2] cmd_sf: Add DIOFR(Dual IO Fast Read) read instruction support
This patch provides a support to read a flash using 'diofr'
read instruction(rd_inst) for 'sf read' and 'sf update' commands.
'diofr' is similar to the dofr(Dual Output Fast Read) except that it
improves performance throughput by allowing input of the
address bits using two bits per SCK via two input pins.
Example:
read 0x2000 length bytes starting at offset 0x0 to memory at 0x1
using diofr read instruction.
u-boot sf read diofr 0x1 0x0 0x2000
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction and diofr read instruction.
u-boot sf update pp diofr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
Changes in v2: Added command help on U_BOOT_CMD
common/cmd_sf.c | 12
include/spi_flash_inst.h |1 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index a07effd..20879e7 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -293,7 +293,9 @@ static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst, u8
*rd_qeb_req)
else if (strcmp(arg, qofr) == 0) {
*rd_inst = CMD_READ_QUAD_OUTPUT_FAST;
*rd_qeb_req = 1;
- } else
+ } else if (strcmp(arg, diofr) == 0)
+ *rd_inst = CMD_READ_DUAL_IO_FAST;
+ else
return 1;
return 0;
@@ -643,11 +645,12 @@ U_BOOT_CMD(
sf read rd_inst addr offset len\n
- read `len' bytes starting at\n
`offset' to memory at `addr' using\n
-afr | asr | dofr | qofr `rd_inst'
read instructions\n
+afr | asr | dofr | qofr | diofr
`rd_inst' read instructions\n
afr (Array Fast Read, 0bh)\n
asr (Array Slow Read, 02b)\n
dofr (Dual Output Fast Read, 3bh)\n
qofr (Quad Output Fast Read, 6bh)\n
+diofr (Dual Input/Output Fast Read,
bbh)\n
sf write wr_inst addr offset len\n
- write `len' bytes from memory\n
at `addr' to flash at `offset'
using\n
@@ -662,10 +665,11 @@ U_BOOT_CMD(
pp | qpp `wr_inst' write instructions
and\n
pp (Page Program, 02h)\n
qpp (Quad Page Program, 32h)\n
-afr | asr | dofr | qofr `rd_inst'
read instructions\n
+afr | asr | dofr | qofr | diofr
`rd_inst' read instructions\n
afr (Array Fast Read, 0bh)\n
asr (Array Slow Read, 02b)\n
dofr (Dual Output Fast Read, 3bh)\n
-qofr (Quad Output Fast Read, 6bh)
+qofr (Quad Output Fast Read, 6bh)\n
+diofr (Dual Input/Output Fast Read,
bbh)
SF_TEST_HELP
);
diff --git a/include/spi_flash_inst.h b/include/spi_flash_inst.h
index 67b22c8..e718e8e 100644
--- a/include/spi_flash_inst.h
+++ b/include/spi_flash_inst.h
@@ -33,5 +33,6 @@
#define CMD_READ_ARRAY_SLOW0x03
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
+#define CMD_READ_DUAL_IO_FAST 0xbb
#endif /* _SPI_FLASH_INST_H_ */
--
1.7.0.4
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[U-Boot] [PATCH v2 2/2] cmd_sf: Add QIOFR(Quad IO Fast Read) read instruction support
This patch provides a support to read a flash using 'qiofr'
read instruction(rd_inst) for 'sf read' and 'sf update' commands.
'qiofr' is similar to the qofr(Quad Output Fast Read) except that it
improves performance throughput by allowing input of the
address bits using four bits per SCK via four input pins.
Example:
read 0x2000 length bytes starting at offset 0x0 to memory at 0x1
using qiofr read instruction.
u-boot sf read qiofr 0x1 0x0 0x2000
erase and write 0x2000 length bytes from memory at 0x1 address to
flash offset at 0x0 using pp write instruction and qiofr read instruction.
u-boot sf update pp qiofr 0x1 0x0 0x2000
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
Changes in v2: Added command help on U_BOOT_CMD
common/cmd_sf.c | 13 +
include/spi_flash_inst.h |1 +
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 20879e7..67368c2 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -295,7 +295,10 @@ static int sf_parse_rd_inst_arg(char *arg, u8 *rd_inst, u8
*rd_qeb_req)
*rd_qeb_req = 1;
} else if (strcmp(arg, diofr) == 0)
*rd_inst = CMD_READ_DUAL_IO_FAST;
- else
+ else if (strcmp(arg, qiofr) == 0) {
+ *rd_inst = CMD_READ_QUAD_IO_FAST;
+ *rd_qeb_req = 1;
+ } else
return 1;
return 0;
@@ -645,12 +648,13 @@ U_BOOT_CMD(
sf read rd_inst addr offset len\n
- read `len' bytes starting at\n
`offset' to memory at `addr' using\n
-afr | asr | dofr | qofr | diofr
`rd_inst' read instructions\n
+afr | asr | dofr | qofr | diofr |
qiofr `rd_inst' read instructions\n
afr (Array Fast Read, 0bh)\n
asr (Array Slow Read, 02b)\n
dofr (Dual Output Fast Read, 3bh)\n
qofr (Quad Output Fast Read, 6bh)\n
diofr (Dual Input/Output Fast Read,
bbh)\n
+qiofr (Quad Input/Output Fast Read,
ebh)\n
sf write wr_inst addr offset len\n
- write `len' bytes from memory\n
at `addr' to flash at `offset'
using\n
@@ -665,11 +669,12 @@ U_BOOT_CMD(
pp | qpp `wr_inst' write instructions
and\n
pp (Page Program, 02h)\n
qpp (Quad Page Program, 32h)\n
-afr | asr | dofr | qofr | diofr
`rd_inst' read instructions\n
+afr | asr | dofr | qofr | diofr |
qiofr `rd_inst' read instructions\n
afr (Array Fast Read, 0bh)\n
asr (Array Slow Read, 02b)\n
dofr (Dual Output Fast Read, 3bh)\n
qofr (Quad Output Fast Read, 6bh)\n
-diofr (Dual Input/Output Fast Read,
bbh)
+diofr (Dual Input/Output Fast Read,
bbh)\n
+qiofr (Quad Input/Output Fast Read,
ebh)
SF_TEST_HELP
);
diff --git a/include/spi_flash_inst.h b/include/spi_flash_inst.h
index e718e8e..556e179 100644
--- a/include/spi_flash_inst.h
+++ b/include/spi_flash_inst.h
@@ -34,5 +34,6 @@
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_DUAL_IO_FAST 0xbb
+#define CMD_READ_QUAD_IO_FAST 0xeb
#endif /* _SPI_FLASH_INST_H_ */
--
1.7.0.4
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Re: [U-Boot] [RFC]: always relocate u-boot before the framebuffer
Hi Jeroen, Hi All, Currently CONFIG_FB_ADDR can be set to specify the location of the frame buffer. Since Linux places the frame buffer at the end of the RAM, it is nice to place it at the same position so the u-boot to linux transition can be made flicker free, by preserving the frame buffer. However u-boot and it's heap prefer to locate themselves at the end of the RAM as well and there is nothing which prevents them to overlap. While this can be set/calculated manually, it would be nicer if the relocation would never take place to the region occupied by the frame buffer. A simple way to do so is to locate u-boot before the frame buffer, like it is already done when the frame buffer address is not set. Currently there are 2 boards using the CONFIG_FB_ADDR and CONFIG_LCD on arm (trats, mimc200). Would it cause any problem to relocate u-boot below the frame buffer on these boards? Regards, Jeroen proposed patch: diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index e0cb635..4d0fc3c 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -371,9 +371,10 @@ void board_init_f(ulong bootflag) gd-fb_base = CONFIG_FB_ADDR; #else /* reserve memory for LCD display (always full pages) */ - addr = lcd_setmem(addr); - gd-fb_base = addr; + gd-fb_base = lcd_setmem(addr); #endif /* CONFIG_FB_ADDR */ + /* always continue placement below the frame buffer to not overlap */ Good idea. I will test it and let you know. -- Best regards, Lukasz Majewski Samsung Poland RD Center | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MPC8555 pci issue
Dear Ashok Kumar Kacham, In message 706dea54d3c60b8c69ea3d22f8d4c216.squir...@mail.bel.co.in you wrote: we have a MPC8555 custom designed board, where we ported u-boot(1.3.1) and linux 2.6.24(without PCI). we have a pci-to-usb U-Boot 1.3.1 is more than 5 years old, and Linux 2.6.24 is nearly 5 years old, too. This is prehistoric code, for which you will not be able to find any free community support any more. Please update to recent code (at least U-Boot v2012.12 / Linux 3.7.1) and try again. If there are still issues, please ask again. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The software required `Windows 95 or better', so I installed Linux. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC]: always relocate u-boot before the framebuffer
Dear Lukasz Majewski, In message 20121231153353.2d9a5dda@amdc308.digital.local you wrote: - addr = lcd_setmem(addr); - gd-fb_base = addr; + gd-fb_base = lcd_setmem(addr); #endif /* CONFIG_FB_ADDR */ + /* always continue placement below the frame buffer to not overlap */ Good idea. I will test it and let you know. Please see my responses. This is definitely NOT a good idea, it will break most (all?) boards that use CONFIG_FB_ADDR in the way it was intended for. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You go slow, be gentle. It's no one-way street -- you know how you feel and that's all. It's how the girl feels too. Don't press. If the girl feels anything for you at all, you'll know. -- Kirk, Charlie X, stardate 1535.8 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/5] am33xx: support for booting via usbeth
This patch adds BOOT_DEVICE define for USB booting and fixes spl_board_init function to call arch_misc_init (this is the place there musb is initialized). Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com --- arch/arm/cpu/armv7/omap-common/boot-common.c | 3 +++ arch/arm/include/asm/arch-am33xx/spl.h | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 0f19141..99dc9d8 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -54,6 +54,9 @@ void spl_board_init(void) #ifdef CONFIG_SPL_NAND_SUPPORT gpmc_init(); #endif +#if defined(CONFIG_AM33XX) defined(CONFIG_SPL_MUSB_NEW_SUPPORT) + arch_misc_init(); +#endif } int board_mmc_init(bd_t *bis) diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 644ff35..e961ce0 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -29,6 +29,7 @@ #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #define BOOT_DEVICE_SPI11 #define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF #endif -- 1.8.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] spl: support for booting via usbeth
In case of usbeth booting just call net_load_image(usb_ether). This patch also adds CONFIG_SPL_USBETH_SUPPORT and CONFIG_SPL_MUSB_NEW_SUPPORT config options to enable linking of SPL against USB gagdet support and new MUSB driver resp. Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com --- common/spl/spl.c | 5 + spl/Makefile | 2 ++ 2 files changed, 7 insertions(+) diff --git a/common/spl/spl.c b/common/spl/spl.c index ff9ba7b..6a5a136 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -221,6 +221,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) #endif break; #endif +#ifdef CONFIG_SPL_USBETH_SUPPORT + case BOOT_DEVICE_USBETH: + spl_net_load_image(usb_ether); + break; +#endif default: debug(SPL: Un-supported Boot Device\n); hang(); diff --git a/spl/Makefile b/spl/Makefile index 6dbb105..cde 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -81,6 +81,8 @@ LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o +LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o +LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -- 1.8.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/5] spl: add possibility to force boot device
Sometimes (for debugging purposes mostly but also to overcome some
hardware limitations) it's desirable to be able to force boot device to
some fixed value. This patch adds this possibility via
CONFIG_SPL_FORCE_BOOT_DEVICE option.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
common/spl/spl.c | 4
1 file changed, 4 insertions(+)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 6a5a136..37f4d38 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -177,7 +177,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
spl_board_init();
#endif
+#ifdef CONFIG_SPL_FORCE_BOOT_DEVICE
+ boot_device = CONFIG_SPL_FORCE_BOOT_DEVICE;
+#else
boot_device = spl_boot_device();
+#endif
debug(boot device - %d\n, boot_device);
switch (boot_device) {
#ifdef CONFIG_SPL_RAM_DEVICE
--
1.8.0.2
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[U-Boot] [PATCH 3/5] am335x_evm: enable support for booting via USB
This adds necessary config options to enable usb booting and fixes board_eth_init() function to take into account that we may have USB ether support in SPL now. Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com --- board/ti/am335x/board.c | 3 ++- include/configs/am335x_evm.h | 8 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index f0eca54..5728c9a 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -425,7 +425,8 @@ int board_eth_init(bd_t *bis) n += rv; #endif try_usbether: -#if defined(CONFIG_USB_ETHER) !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_USB_ETHER) \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) rv = usb_eth_initialize(bis); if (rv 0) printf(Error %d registering USB_ETHER\n, rv); diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ab9549b..2da863d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -238,6 +238,8 @@ #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x4 +#define CONFIG_SPL_MUSB_NEW_SUPPORT +#define CONFIG_SPL_USBETH_SUPPORT #define CONFIG_SPL_LDSCRIPT$(CPUDIR)/omap-common/u-boot-spl.lds /* @@ -279,6 +281,8 @@ #ifdef CONFIG_MUSB_GADGET #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDRde:ad:be:af:00:00 +#define CONFIG_USBNET_DEV_ADDR de:ad:be:af:00:01 #endif /* CONFIG_MUSB_GADGET */ /* Unsupported features */ @@ -301,4 +305,8 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC +#ifdef CONFIG_SPL_BUILD +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +#endif #endif /* ! __CONFIG_AM335X_EVM_H */ -- 1.8.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/5] am335x_evm: support for booting via USB
These series add support for booting via USB on TI AM335X based boards. Tested on BeagleBone. Ilya Yanok (5): spl: support for booting via usbeth am33xx: support for booting via usbeth am335x_evm: enable support for booting via USB spl: add possibility to force boot device am335x_evm: add new config with forced USB booting arch/arm/cpu/armv7/omap-common/boot-common.c | 3 +++ arch/arm/include/asm/arch-am33xx/spl.h | 1 + board/ti/am335x/board.c | 3 ++- boards.cfg | 1 + common/spl/spl.c | 9 + include/configs/am335x_evm.h | 8 spl/Makefile | 2 ++ 7 files changed, 26 insertions(+), 1 deletion(-) -- 1.8.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] am335x_evm: add new config with forced USB booting
Currently AM335X hardware has bug in it's ROM code that prevents USB booting from working normally. So we have to load SPL via serial console instead. But it's feasible to use USB for loading the main U-Boot image. This patch adds additional am335x_evm configuration for this. Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com --- boards.cfg | 1 + 1 file changed, 1 insertion(+) diff --git a/boards.cfg b/boards.cfg index 91504c0..e7c66a9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -229,6 +229,7 @@ integratorap_cm946es arm arm946es integrator armltd integratorcp_cm946es arm arm946esintegrator armltd - integratorcp:CM946ES ca9x4_ct_vxp arm armv7 vexpressarmltd am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 +am335x_evm_usbboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_FORCE_BOOT_DEVICE=BOOT_DEVICE_USBETH am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4 -- 1.8.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
