This patch implements a custom spi_copy funtion to copy u-boot from SF
to RAM. This is faster then iROM spi_copy funtion as this runs spi at
50Mhz and also in WORD mode of operation.
Changed a printf in pinmux.c to debug just to avoid the compilation
error in SPL.
Removed enum for boot mode from
Dear Stephen,
In message 51a6869f.1020...@wwwdotorg.org you wrote:
Since DT is supposed to be a HW description, it shouldn't be using cpp's
built-in macros to compile in different ways; there really isn't a
concept of the target arch of compilation; a .dts file should simply
compile the same
Dear Stephen Warren,
In message 51a68a4c.4060...@wwwdotorg.org you wrote:
Sorry, instead we should strive to be compatible to a reasonably old,
stable version of DTC, like we do for all other tools as well. As
mentioned before - just because RHEL 5 ships an ancient version of -
say -
Dear tiger...@viatech.com.cn,
In message fe7aded5c2218b4786c09cd97dc4c49f8db...@exchbj02.viatech.com.bj you
wrote:
Could i use fopen/fwrite standard C lib functions in U-boot code?
What for? We do not even have a concept of files in U-Boot...
Best regards,
Wolfgang Denk
--
DENX Software
Move pinmux configurations for the DA830 SoCs from board file
to the arch tree so that it can be used for all da830 based devices.
Also, avoids duplicate pinmuxing in case of NAND.
Signed-off-by: Vishwanathrao Badarkhe, Manish manish...@ti.com
---
Depends on:
Dear Stephen,
In message 51a6df7c.30...@wwwdotorg.org you wrote:
It seems to be aimed specifically at enabling use of new dtc features
when present. That seems to be specifically against Wolfgang's goal of
not requiring new dtc features. There's no point allowing use of new dtc
Please stop
The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.
The gpio number should be extracted (shifted back) before that.
Signed-off-by: Andrew Gabbasov
Dear Denk:
U-boot supports FAT file system.
So, i want to read/write a file in USB disk (formatted with fat file system).
So, could i use fopen/fwrite functions?
Best wishes,
-邮件原件-
发件人: Wolfgang Denk [mailto:w...@denx.de]
发送时间: 2013年5月30日 15:50
收件人: Tiger Liu
抄送: u-boot@lists.denx.de
In U-Boot-2013-01 version P3041 board, __stringify is not working.
Enabled the DEBUG mode and got the output as:
*** Warning - bad CRC, using default environment
Destroy Hash Table: 3ffa9b90 table =
Create Hash Table: N=221
INSERT: table 3ffa9b90, filled 1/223 rv 3fe2f858 ==
On 30.05.2013 12:02, Andrew Gabbasov wrote:
The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.
The gpio number should be extracted (shifted back)
Hi Dirk,
From: Behme, Dirk - Bosch
Sent: Thursday, May 30, 2013 14:50
To: Gabbasov, Andrew
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH] mx6: mx6qsabrelite/nitrogen6x: Fix use of gpio
number in SF chip select
[skipped]
To my
On 30.05.2013 13:32, Gabbasov, Andrew wrote:
Hi Dirk,
From: Behme, Dirk - Bosch
Sent: Thursday, May 30, 2013 14:50
To: Gabbasov, Andrew
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH] mx6: mx6qsabrelite/nitrogen6x: Fix use of gpio
number in SF
Misc cleanup.
And also adding a Generic bus init and write functions
for PMIC.
This series is applied on top of u-boot-ti:
git://git.denx.de/u-boot-ti.git
Testing:
Boot tested on OMAP5432 ES2.0, OMAP4460 PANDA.
Verified MAKEALL for armv7/omap boards.
Changes from v1:
* Created new patch for
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap4/prcm-regs.c |3 +++
arch/arm/cpu/armv7/omap5/prcm-regs.c |2 ++
From: Sricharan R r.sricha...@ti.com
SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |6 --
1 file changed, 6 deletions(-)
diff
To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |2 +-
arch/arm/cpu/armv7/omap-common/emif-common.c |2 +-
Voltage scaling can be done in two ways:
- Using SR I2C
- Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |6 ++
Dear tiger...@viatech.com.cn,
please do not top post / full quote. See [1] if you need help.
[1] http://www.netmeister.org/news/learn2quote.html
In message fe7aded5c2218b4786c09cd97dc4c49f8db...@exchbj02.viatech.com.bj you
wrote:
U-boot supports FAT file system.
Yes, it does. And it
Hello Tom and Bo,
While preparing for my ARM PR, I have encountered two merge conflicts.
Their resolution can be found in branch 'merge_from_mainline' of ARM
repo git://git.denx.de/u-boot-arm.
For common/cmd_fpga.c, the merge conflict was trivial -- Simon's
renaming fit somehow caused a need for
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 05/30/2013 08:55 AM, Albert ARIBAUD wrote:
Hello Tom and Bo,
While preparing for my ARM PR, I have encountered two merge
conflicts. Their resolution can be found in branch
'merge_from_mainline' of ARM repo git://git.denx.de/u-boot-arm.
Dear Balaji N,
In message caf8ym8presb4fjrnunmhgjgmq_zquakgf_cfpbqg+hpotev...@mail.gmail.com
you wrote:
In U-Boot-2013-01 version P3041 board, __stringify is not working.
Enabled the DEBUG mode and got the output as:
*** Warning - bad CRC, using default environment
Destroy Hash Table:
The registers that are used for device identification
are changed from OMAP5 to DRA7xx.
Using the correct registers for DRA7xx.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h | 11 +--
include/configs/dra7xx_evm.h |3 ++-
2 files
From: Sricharan R r.sricha...@ti.com
Serial UART is connected to UART1. So add the change
for the same.
Signed-off-by: Sricharan R r.sricha...@ti.com
---
include/configs/dra7xx_evm.h |3 +++
include/configs/omap5_common.h |4
include/configs/omap5_uevm.h |4
3 files
Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c |3 +++
arch/arm/include/asm/omap_common.h |8
2 files changed, 11
From: Balaji T K balaj...@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h |3 ++-
drivers/mmc/omap_hsmmc.c | 26 ++
TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 23 ++
arch/arm/cpu/armv7/omap5/hw_data.c | 38
From: Nishanth Menon n...@ti.com
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without
the
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
From: Sricharan R r.sricha...@ti.com
DRA7 EVM board has the below configuration. Adding the
settings for the same here.
2Gb_1_35V_DDR3L part * 2 on EMIF1
2Gb_1_35V_DDR3L part * 4 on EMIF2
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
From: Sricharan R r.sricha...@ti.com
NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h | 11 ++-
1 file changed, 6 insertions(+), 5
Updating pinmux data as specified in the latest DM
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/include/asm/arch-omap5/mux_dra7xx.h |7 +++--
board/ti/dra7xx/mux_data.h | 38 --
2 files
From: Sricharan R r.sricha...@ti.com
The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
This series update support for DRA7xx family Socs and the data for
DRA752 ES1.0 soc.
This is on top of my recent Misc cleanup series:
http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt155949.html
Testing:
Boot tested on DRA752 ES1.0, OMAP5432 ES2.0, OMAP4460 PANDA
Verified
Hi,
On Mon, May 27, 2013 at 1:14 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Missing return after memcpy is done for memory-mapped SPI flashes,
hence added retun 0 after memcpy done.
The return is missing in below patch
sf: Enable FDT-based configuration
Bo Shen voice.s...@gmail.com on behalf of Bo Shen voice.s...@atmel.com
Hi Albert,
On 05/30/2013 08:55 PM, Albert ARIBAUD wrote:
Hello Tom and Bo,
While preparing for my ARM PR, I have encountered two merge conflicts.
Their resolution can be found in branch 'merge_from_mainline' of ARM
repo
This patch series consists of few corrections dones on already commited
patches,
along with some updates on parts name and few new flash parts are added.
Thanks,
Jagan.
Jagannadha Sutradharudu Teki (8):
sf: spansion: Update the name for S25FL256S flash
sf: spansion: Add support for
Add support for Winbond W25Q80BW SPI flash.
This patch corrected the flash name, nr_blocks and
also commit message header from below patch.
sf: winbond: add W25Q32
(sha1: c969abc47033d6f810d3c9dbdb994ea9d691d038)
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
Add support for Winbond W25QXXXFV SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/winbond.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi/winbond.c
This patch corrected the nr_blocks used for W25Q32DW SPI flash.
nr_blcoks are incorrectly assigned on below patch
sf: winbond: add W25Q32DW
(sha1: 772ba15474f73adc942e817cc072b6e9750836cc)
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
Add support for Winbond W25Q16DW SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/winbond.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index
As the per the ID tabl the flash is under Uniform 64-kB sector
architecture, hence updated with proper name.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spansion.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
This commit is based on the patch from Xie Xiaobo x@freescale.com
with commit head title as sf: spansion: Add support for S25FL128S.
pulled the same code changes into current u-boot tree with little update
on the name field.
http://patchwork.ozlabs.org/patch/218145/
SPANSION recommend
Use the exact names for W25Q 0x40XX ID's flash parts, as the same
sizes of flashes comes with different ID's. so-that the distinguishes
becomes easy with this change.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/winbond.c | 10
Add support for Winbond W25Q128FW SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/winbond.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index
Hi Tom,
On Thu, May 16, 2013 at 11:49 AM, Simon Glass s...@chromium.org wrote:
Hi Tom,
On Thu, May 16, 2013 at 9:26 AM, Tom Rini tr...@ti.com wrote:
On Wed, May 15, 2013 at 07:13:18AM -0700, Simon Glass wrote:
[snip]
I've brought over the patches that I can that don't depend on
From: Behme, Dirk - Bosch
Sent: Thursday, May 30, 2013 15:50
To: Gabbasov, Andrew
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH] mx6: mx6qsabrelite/nitrogen6x: Fix use of gpio
number in SF chip select
On 30.05.2013 13:32, Gabbasov, Andrew
On Thu, May 30, 2013 at 01:24:42AM +0300, Lubomir Popov wrote:
Tested on OMAP4/5 only, but should work on older OMAPs and
derivatives as well.
- Rewritten i2c_read to operate correctly with all types of chips
(old function could not read consistent data from some I2C slaves).
- Optimised
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balaj...@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h |3 ++-
The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.
Also, SPI driver sets the direction and initial value of a gpio,
used as a chip select signal,
Hi Tom,
On 30/05/13 17:37, Tom Rini wrote:
On Thu, May 30, 2013 at 01:24:42AM +0300, Lubomir Popov wrote:
Tested on OMAP4/5 only, but should work on older OMAPs and
derivatives as well.
- Rewritten i2c_read to operate correctly with all types of chips
(old function could not read
On Thu, May 30, 2013 at 05:51:44PM +0300, Lubomir Popov wrote:
Hi Tom,
On 30/05/13 17:37, Tom Rini wrote:
On Thu, May 30, 2013 at 01:24:42AM +0300, Lubomir Popov wrote:
Tested on OMAP4/5 only, but should work on older OMAPs and
derivatives as well.
- Rewritten i2c_read to operate
From: Gabbasov, Andrew
Sent: Thursday, May 30, 2013 18:36
To: Behme, Dirk - Bosch
Cc: u-boot@lists.denx.de
Subject: RE: [U-Boot] [PATCH] mx6: mx6qsabrelite/nitrogen6x: Fix use of gpio
number in SF chip select
[skipped]
So, OK, you convinced me ;-)
On Thu, May 30, 2013 at 06:57:02AM -0700, Simon Glass wrote:
Hi Tom,
On Thu, May 16, 2013 at 11:49 AM, Simon Glass s...@chromium.org wrote:
Hi Tom,
On Thu, May 16, 2013 at 9:26 AM, Tom Rini tr...@ti.com wrote:
On Wed, May 15, 2013 at 07:13:18AM -0700, Simon Glass wrote:
On Thu, 30 May 2013 14:55:41 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Tom and Bo,
While preparing for my ARM PR, I have encountered two merge conflicts.
Their resolution can be found in branch 'merge_from_mainline' of ARM
repo git://git.denx.de/u-boot-arm.
For
2013/5/29 Gabor Juhos juh...@openwrt.org:
The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.
Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if
Hi Albert,
On Thu, May 30, 2013 at 9:21 AM, Albert ARIBAUD
albert.u.b...@aribaud.netwrote:
On Thu, 30 May 2013 14:55:41 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Tom and Bo,
While preparing for my ARM PR, I have encountered two merge conflicts.
Their resolution can
2013.05.30. 18:36 keltezéssel, Daniel Schwierzeck írta:
2013/5/29 Gabor Juhos juh...@openwrt.org:
The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.
Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config
On Thu, May 30, 2013 at 10:37:42AM -0400, Tom Rini wrote:
On Thu, May 30, 2013 at 01:24:42AM +0300, Lubomir Popov wrote:
Tested on OMAP4/5 only, but should work on older OMAPs and
derivatives as well.
- Rewritten i2c_read to operate correctly with all types of chips
(old function
Hi Simon,
On Thu, 30 May 2013 09:38:56 -0700, Simon Glass s...@chromium.org
wrote:
Hi Albert,
On Thu, May 30, 2013 at 9:21 AM, Albert ARIBAUD
albert.u.b...@aribaud.netwrote:
On Thu, 30 May 2013 14:55:41 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Tom and Bo,
On 05/30/2013 01:56 AM, Wolfgang Denk wrote:
Dear Stephen,
In message 51a6df7c.30...@wwwdotorg.org you wrote:
It seems to be aimed specifically at enabling use of new dtc features
when present. That seems to be specifically against Wolfgang's goal of
not requiring new dtc features. There's
Hi Tom,
On Thu, May 30, 2013 at 10:37:42AM -0400, Tom Rini wrote:
On Thu, May 30, 2013 at 01:24:42AM +0300, Lubomir Popov wrote:
Tested on OMAP4/5 only, but should work on older OMAPs and
derivatives as well.
- Rewritten i2c_read to operate correctly with all types of chips
(old
Hello Tom,
The following changes since commit
a71d45d706a5b51c348160163b6c159632273fed:
powerpc/mpc85xx: Clear L1 D-cache lock (2013-05-24 16:54:14 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-arm master
for you to fetch changes up to
Hi Tom,
On Thu, May 30, 2013 at 10:37:42AM -0400, Tom Rini wrote:
On Thu, May 30, 2013 at 01:24:42AM +0300, Lubomir Popov wrote:
Tested on OMAP4/5 only, but should work on older OMAPs and
derivatives as well.
- Rewritten i2c_read to operate correctly with all types of chips
(old
On Mon, Jan 14, 2013 at 03:46:50AM -, Sergey Lapin wrote:
This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:
- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API
Signed-off-by: Robert Winkler robert.wink...@boundarydevices.com
---
board/boundary/nitrogen6x/nitrogen6x.c | 22 ++
include/configs/nitrogen6x.h | 11 ++-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c
Hi
Have you submitted this patch?
Would it be possible to share this patch because we have the same problem?
BR,
Pierre Assal
--
View this message in context:
http://u-boot.10912.n7.nabble.com/JFFS2-seems-to-drop-nand-data-with-ECC-corrections-tp142008p155997.html
Sent from the U-Boot
On Thu, May 30, 2013 at 7:47 AM, Andrew Gabbasov andrew_gabba...@mentor.com
wrote:
The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.
Also,
Dear Robert Winkler,
In message
1369947781-25077-1-git-send-email-robert.wink...@boundarydevices.com you
wrote:
Signed-off-by: Robert Winkler robert.wink...@boundarydevices.com
---
board/boundary/nitrogen6x/nitrogen6x.c | 22 ++
include/configs/nitrogen6x.h |
On Thu, May 30, 2013 at 4:32 PM, Wolfgang Denk w...@denx.de wrote:
Dear Robert Winkler,
In message
1369947781-25077-1-git-send-email-robert.wink...@boundarydevices.com you
wrote:
Signed-off-by: Robert Winkler robert.wink...@boundarydevices.com
---
Hi Albert,
On Thu, May 30, 2013 at 10:37 AM, Albert ARIBAUD
albert.u.b...@aribaud.netwrote:
Hi Simon,
On Thu, 30 May 2013 09:38:56 -0700, Simon Glass s...@chromium.org
wrote:
Hi Albert,
On Thu, May 30, 2013 at 9:21 AM, Albert ARIBAUD
albert.u.b...@aribaud.netwrote:
On Thu, 30
On Mon, May 06, 2013 at 03:17:45PM +0200, Andre Przywara wrote:
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state.
Introduce a monitor handler routine which switches the CPU to
non-secure state by setting the NS and associated bits.
Dear Denk:
Got it!
Thank you!
Best wishes,
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Hi, experts:
I wrote a driver for uboot.
This driver called writel/readl function.
I have included include/asm/io.h.
But when i compiled , it output below error msgs:
undefined reference to `__readwrite_bug'
Best wishes,
___
U-Boot mailing list
On 30.05.2013 16:47, Andrew Gabbasov wrote:
The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.
Also, SPI driver sets the direction and initial
On Mon, May 06, 2013 at 03:17:46PM +0200, Andre Przywara wrote:
While actually switching to non-secure state is one thing, the
more important part of this process is to make sure that we still
have full access to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure
On Mon, May 06, 2013 at 03:17:47PM +0200, Andre Przywara wrote:
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
Some part
On Mon, May 06, 2013 at 03:17:49PM +0200, Andre Przywara wrote:
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While doing the non-secure switch, we have to enable
On Mon, May 06, 2013 at 03:17:48PM +0200, Andre Przywara wrote:
Currently the non-secure switch is only done for the boot processor.
To later allow full SMP support, we have to switch all secondary
cores into non-secure state also.
So we add an entry point for secondary CPUs coming out of
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