[U-Boot] [PATCH v2] lib:crc32: Allow setting of the initial crc32 value
The current approach set the initial value of crc32 calculation to zero,
which is correct for calculating checksum of the whole chunk of data.
It however, lacks the flexibility, when one wants to calculate CRC32 of
a file comprised of many smaller parts received separately.
In the proposed approach the output value is used as a starting condition
for the proper crc32 calculation at crc32_wd function. This behavior is
identical to the one provided by crc32() method implementation.
Additionally comments were appropriately updated.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Cc: Marek Vasut ma...@denx.de
---
Changes for v2:
- Replace casting from (u8*) to (u32*) with memcpy
---
include/hash.h |2 +-
include/u-boot/crc.h |3 ++-
lib/crc32.c |7 +--
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/hash.h b/include/hash.h
index dc21678..abf704d 100644
--- a/include/hash.h
+++ b/include/hash.h
@@ -101,7 +101,7 @@ int hash_command(const char *algo_name, int flags,
cmd_tbl_t *cmdtp, int flag,
* @algo_name: Hash algorithm to use
* @data: Data to hash
* @len: Lengh of data to hash in bytes
- * @output:Place to put hash value
+ * @output:Place to put hash value - also the initial value (crc32)
* @output_size: On entry, pointer to the number of bytes available in
* output. On exit, pointer to the number of bytes used.
* If NULL, then it is assumed that the caller has
diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h
index 754ac72..7a87911 100644
--- a/include/u-boot/crc.h
+++ b/include/u-boot/crc.h
@@ -19,7 +19,8 @@ uint32_t crc32_no_comp (uint32_t, const unsigned char *,
uint);
*
* @input: Input buffer
* @ilen: Input buffer length
- * @output:Place to put checksum result (4 bytes)
+ * @output:Place to provide initial CRC32 value and afterwards
+ * put checksum result (4 bytes)
* @chunk_sz: Trigger watchdog after processing this many bytes
*/
void crc32_wd_buf(const unsigned char *input, uint ilen,
diff --git a/lib/crc32.c b/lib/crc32.c
index 9759212..80e078f 100644
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -255,9 +255,12 @@ uint32_t ZEXPORT crc32_wd (uint32_t crc,
void crc32_wd_buf(const unsigned char *input, unsigned int ilen,
unsigned char *output, unsigned int chunk_sz)
{
- uint32_t crc;
+ uint32_t crc = 0;
- crc = crc32_wd(0, input, ilen, chunk_sz);
+ if (*output)
+ memcpy(crc, output, sizeof(crc));
+
+ crc = crc32_wd(crc, input, ilen, chunk_sz);
crc = htonl(crc);
memcpy(output, crc, sizeof(crc));
}
--
1.7.10.4
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Re: [U-Boot] [Question] Linux Boot with u-boot 2014.04 on Zynq board
Hi Masahiro,
On 05/07/2014 07:47 AM, Masahiro Yamada wrote:
Hi Michal,
Sorry for late reply. (I'm back from my vacations.)
No problem at all.
Before you build u-boot you have to copy ps7_init.c/h from your
hw design to the u-boot if you want to use SPL.
Oops, I forgot to mention this.
I did that.
ok. Then I expect you are able to see at least u-boot SPL messages.
Yes. I can see them.
That's a great start.
This is what I am getting - u-boot.img has full u-boot.
U-Boot SPL 2014.01-00816-ge0c1813-dirty (Jan 22 2014 - 17:56:37)
mmc boot
reading download.bit
design filename = system.ncd;HW_TIMEOUT=FALSE;UserID=0x
part number = 7z020clg484
date = 2013/07/22
time = 17:18:11
bytes in bitstream = 4045564
zynq_load: Align buffer at 16c to 100(swap 1)
reading system.dtb
spl: error reading image system.dtb, err - -1
reading u-boot.img
reading u-boot.img
U-Boot 2014.01 (Mar 19 2014 - 08:12:51)
Memory: ECC disabled
DRAM: 1 GiB
MMC: zynq_sdhci: 0
SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16
MiB
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Net: Gem.e000b000
U-BOOT for zynq-zc702
Gem.e000b000 Waiting for PHY auto negotiation to complete done
BOOTP broadcast 1
BOOTP broadcast 2
Abort
Hit any key to stop autoboot: 0
U-Boot-PetaLinux
Thanks!
Now I understand how to boot u-boot and Linux.
You can run Linux directly from SPL. I have tried that but without
FIT it is not so nice.
Full u-boot image of zynq enables CONFIG_OF_SEPARATE, right?
I think u-boot.img does not include device tree.
In mainline yes but I am not using it. It is nice for playing
but it is fine just to disable it and you don't need to use dts at all.
Just disable it in zynq config file.
I am not convinced why unsupported CONFIG_OF_SEPARATE is enabled.
Jagan has enabled it - don't know why but it is enabled by default.
U-boot mainline and u-boot-xlnx diverged with this point.
Which way are you going in your future development?
U-Boot control with device tree? or without device tree?
yes. I have tried OF_SEPARATE and if you copy DTS from the kernel (our repo)
you can use it and should work. At least worked when I have tried it.
u-boot should be configured from device-tree.
We are pushing a lot of drivers to mainline and we are reviewing the whole
binding to ensure that it is correct that's why I haven't pushed
any DTS file to u-boot source code for reference boards.
My question is, how to pass an init ramdisk?
I am using cpio compiled in directly in the kernel.
In which file-name should I copy init ramdisk
into SD card?
Xilinx OSL versions are using initramdisk
which you can download here.
http://www.wiki.xilinx.com/Zynq+2014.1+Release
Yes. I am using this.
ok. Then what are you trying to do? Just use latest u-boot?
Yes.
I want to run U-boot and Linux on a Zynq board.
I also want to use new features in the U-Boot mainline such as Kbuild.
That is my motivation to try to run u-boot-2014.04 on a zynq board.
ok. Just disable OF_CONTROL for now and I haven't pushed that SPL fpga
feature because it needs to be cleanup.
How should I load the init ramdisk from the SD card?
And this is the command which OSL version are using.
sdboot=if mmcinfo; then \
run uenvboot; \
echo Copying Linux from SD to RAM... \
fatload mmc 0 0x300 ${kernel_image} \
fatload mmc 0 0x2A0 ${devicetree_image} \
fatload mmc 0 0x200 ${ramdisk_image} \
bootm 0x300 0x200 0x2A0; \
fi\0 \
Yes. I know this works.
But in my understanding, SPL cannot use this command.
My question is how SPL can load the init ramdisk.
It looks like spl_load_image_fat_os() function loads
system.dtb and uImage.
But I could not find which code loads ramdisk.
Not supported yet?
yes, I think it is not supported.
I haven't had a time but Simon mentioned that they have
enabled ITS format in SPL and it should be straight forward
to do so. Then you can just use full ITS instead of DTB, kernel, ramdisk
in separate images.
This sounds reasonable!
I am looking forward to it.
my too. :-)
thanks,
Michal
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Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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Re: [U-Boot] [PATCH 04/11] kconfig: add basic Kconfig files
Hi Scott, On Thu, 1 May 2014 13:21:08 -0500 Scott Wood scottw...@freescale.com wrote: On Thu, 2014-04-24 at 14:04 +0900, Masahiro Yamada wrote: +config KCONFIG_OBJDIR + string + option env=KCONFIG_OBJDIR + +config BUILD_MODE + string + default SPL if $KCONFIG_OBJDIR=spl/ + default TPL if $KCONFIG_OBJDIR=tpl/ + default Main Why does this need to be a string? I want to show $BUILD_MODE in the top menu. +# see Documentation/kbuild/kconfig-language.txt. +# +mainmenu U-Boot $UBOOTVERSION $BUILD_MODE Configuration here. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 0/3] Android Fastboot support
Hi Rob, From: Rob Herring r...@kernel.org This is the 3nd version since I revived the fastboot patches Sebastian submitted. I'm reviving the Android Fastboot support after 2+ years since the last posting[1]. The previous postings had some questions about licensing and source of some code. I believe I've traced the history sufficiently that the copyrights and source information are complete and correct. The Android code used or referenced is BSD 2-clause license. This was originally raised by Wolfgang that it was not compatible with GPLv2+. I believe that has since been demonstrated and agreed that the BSD 2-clause license is compatible with u-boot. As far as the history of the code, I have traced that back. The u-boot code started in 2008/2009 by Tom Rix @ Windriver. This initial support was then adopted and extended by TI (eMMC support primarily, not included here) in their OMAP u-boot tree[2]. In 2011, the TI code was used as a basis for upstream patches by Sebastian Siewior @ Linutronix. The code has been rearranged quite a bit since the original, but the content is pretty much the same. Some of the re-arranging left stale or missing copyrights in the v2 version which I have corrected. This version is rebased on u-boot usb tree with the recent USB downloader gadget registration changes. The primary change is documentation added to README for new config options. I've tested this series on a BeagleBoard. Applied to u-boot-dfu tree. Rob, thanks for development. -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 10/10] ARM: HYP/non-sec/PSCI: emit DT nodes
On Fri, May 02 2014 at 9:13:08 pm BST, Jon Loeliger loeli...@gmail.com wrote:
On Sat, Apr 26, 2014 at 7:17 AM, Marc Zyngier marc.zyng...@arm.com wrote:
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
new file mode 100644
index 000..0b0d6a7
--- /dev/null
+++ b/arch/arm/cpu/armv7/virt-dt.c
+
+static int fdt_psci(void *fdt)
+{
+#ifdef CONFIG_ARMV7_PSCI
+ int nodeoff;
+ int tmp;
+
+ nodeoff = fdt_path_offset(fdt, /cpus);
+ if (nodeoff 0) {
+ printf(couldn't find /cpus\n);
+ return nodeoff;
+ }
+
+ /* add 'enable-method = psci' to each cpu node */
+ for (tmp = fdt_first_subnode(fdt, nodeoff);
+tmp = 0;
+tmp = fdt_next_subnode(fdt, tmp)) {
+ const struct fdt_property *prop;
+ int len;
+
+ prop = fdt_get_property(fdt, tmp, device_type, len);
+ if (!prop)
+ continue;
+ if (len 4)
+ continue;
+ if (strcmp(prop-data, cpu))
+ continue;
+
+ fdt_setprop_string(fdt, tmp, enable-method, psci);
+ }
+
+ nodeoff = fdt_path_offset(fdt, /psci);
+ if (nodeoff 0) {
+ nodeoff = fdt_path_offset(fdt, /);
+ if (nodeoff 0)
+ return nodeoff;
+
+ nodeoff = fdt_add_subnode(fdt, nodeoff, psci);
+ if (nodeoff 0)
+ return nodeoff;
+ }
+
+ tmp = fdt_setprop_string(fdt, nodeoff, compatible, arm,psci);
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_string(fdt, nodeoff, method, smc);
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_u32(fdt, nodeoff, cpu_suspend,
ARM_PSCI_FN_CPU_SUSPEND);
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_u32(fdt, nodeoff, cpu_off, ARM_PSCI_FN_CPU_OFF);
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_u32(fdt, nodeoff, cpu_on, ARM_PSCI_FN_CPU_ON);
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_u32(fdt, nodeoff, migrate, ARM_PSCI_FN_MIGRATE);
+ if (tmp)
+ return tmp;
+#endif
+ return 0;
+}
Hi Jon,
So, I wonder if it would be better to be a bit more selective or
cautious about adding these nodes and properties. Specifically, if
they are already present in the device tree itself, perhaps they
should be honored and left alone?
Well, we have exactly two possibilities:
- PSCI is provided by the platform's firmware, and we'd better not touch
the DT at all.
- PSCI is provided U-Boot, and we *own* the PSCI related nodes.
I don't think there is an alternative to that, because either U-Boot
or the firmware will install its own secure vectors. The DT manipulation
code just reflect this situation.
I understand that U-Boot gets to define what it implements, and that if
the secure monitor code doesn't actually implement something, or for
that matter *does* implement it, it makes sense for U-Boot to be able
to state those facts in a device tree. However, the DTS may also be
stating what it has implemented or willing to honor on the Linux side
as well. So, yeah, there has to be agreement here.
But who gets to make the final adjustment to the device tree? U-boot
with this code, or the DTS author who may have hand coded specific
wishes and loaded a specific device tree?
We could have an environment variable named
i_know_this_looks_silly_but_nevertheless_please_pretty_please_leave_my_cpu_nodes_alone?
M.
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Re: [U-Boot] [PATCH v4 06/10] ARM: HYP/non-sec: allow relocation to secure RAM
On Fri, May 02 2014 at 9:30:05 pm BST, Jon Loeliger loeli...@gmail.com wrote: Hi Jon, I finally have all this working for me on an A9 system too! Awesome! Ship it! ;-) However, there were a few things that I had to change a bit. For example, by CPUs will always come out of reset at 0x0 and I do not have the ability to set their first-fetch address to anything else. To accommodate this, I need to ensure that the _monitor_vectors are loaded at address 0x0, and that the first entry in the exception vector (for reset) jumped to some notion of secure_reset code. So I changed this code: diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index b5c946f..2a43e3c 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -10,10 +10,13 @@ #include linux/linkage.h #include asm/gic.h #include asm/armv7.h +#include asm/proc-armv/ptrace.h .arch_extension sec .arch_extension virt + .pushsection ._secure.text, ax + .align 5 /* the vector table for secure state and HYP mode */ _monitor_vectors: @@ -22,51 +25,86 @@ _monitor_vectors: adr pc, _secure_monitor .word 0 .word 0 - adr pc, _hyp_trap + .word 0 .word 0 .word 0 +.macro is_cpu_virt_capable tmp + mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1 + and \tmp, \tmp, #CPUID_ARM_VIRT_MASK@ mask virtualization bits + cmp \tmp, #(1 CPUID_ARM_VIRT_SHIFT) +.endm So that it did this too: @@ -20,15 +20,23 @@ .align 5 /* the vector table for secure state and HYP mode */ _monitor_vectors: - .word 0 /* reset */ - .word 0 /* undef */ - adr pc, _secure_monitor + ldr pc, _secure_reset /* reset */ + .word 0 /* undef */ + adr pc, _secure_monitor /* SMC */ .word 0 .word 0 .word 0 .word 0 .word 0 + +_secure_reset: +#ifdef CONFIG_SECURE_MONITOR_RESET_FUNCTION + .word CONFIG_SECURE_MONITOR_RESET_FUNCTION +#else + .word 0 +#endif + .macro is_cpu_virt_capable tmp That enabled me to define CONFIG_SECURE_MONITOR_RESET_FUNCTION in my config header file: /* * With the Secure Monitor at 0x0, its reset vector must also * then point off to the correct out-of-reset entry function. */ #define CONFIG_SECURE_MONITOR_RESET_FUNCTION_myplatform_cpu_entry #define CONFIG_ARMV7_SECURE_BASE0x0 That _myplatform_cpu_entry corresponds to your sunxi_cpu_entry code. Yup, makes sense. Nit-pick: make the _secure_reset a weak symbol that your platform code will overload, just like the rest of the PSCI stuff. Saves the #ifdef horror; ;-) So, yeah, I know that isn't a proper patch and all. :-) I'm just sending you more information to ponder for this patch series! If you would like to generalize your patch this way, please feel free to do so. If not, I can send a proper patch after this hits mainline or so. My prefered way would be indeed to have a proper patch on top of this to handle the coming out of reset case. You'll get proper credit for the idea! :-) Thanks, M. -- Without deviation from the norm, progress is not possible. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 06/10] ARM: HYP/non-sec: allow relocation to secure RAM
On Fri, May 02 2014 at 10:03:37 pm BST, Jon Loeliger loeli...@gmail.com wrote: Mark, In your nonsec_init code, you suggest this change: + mrc p15, 0, r0, c1, c1, 2 movwr1, #0x3fff - movtr1, #0x0006 - mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec + movtr1, #0x0004 + orr r0, r0, r1 + mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec Leaving: mrc p15, 0, r0, c1, c1, 2 movwr1, #0x3fff movtr1, #0x0004 orr r0, r0, r1 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec That sets all the co-processor bits, but the man page suggests that only Just to be clear: which document are you referring to? copros with bits 10 and 11 should be modified. It also seems that if the The ARM ARM says that NSACR[13:0] is either RAZ/WI or writable from secure for unimplemented coprocessors. So I believe the above is safe. If you wanted to be really picky, you'd start by reading CPACR, write either 1 or 3 to all the CPn fields, read it back again, see what sticks, and populate NSACR accordingly. Did I hear someone saying Boring? ;-) PLE is enabled, we should mark it NS-enabled at bit 16 also:. Perhaps: mrcp15, 0, r0, c1, c1, 2 movwr1, #0x0c00 movtr1, #0x0005 orrr0, r0, r1 mcrp15, 0, r0, c1, c1, 2@ NSACR = all copros to non-sec We're getting into IMPDEF territory pretty quickly here. PLE only exists on A9, and is optionnal there (and probably doesn't exist on all versions, if memory serves well...). This could be implemented as a per-platform optional feature, though. What do you think? M. -- Without deviation from the norm, progress is not possible. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] booting signed Images
Hello Simon, Am 05.05.2014 20:31, schrieb Simon Glass: Hi Wolfgang, On 5 May 2014 11:55, Wolfgang Denkw...@denx.de wrote: Dear Simon, In messageCAPnjgZ2-qC8YK8t2DvmzXWKy3Wd+=7VY1Ti=jm98lf96plf...@mail.gmail.com you wrote: Should we not prevent booting uImages or not signed FIT Images when CONFIG_FIT_SIGNATURE is defined? Or at least prevent booting such unsigned images through an U-Boot env variable. What Do you think? There is a 'required' property in the public keys which is intended to support this. If you mark a key as 'required then it will need to be verified by any image that is loaded. There is a test for this case, but it may not be comprehensive. But what about legacy uImage files? It appears nothing would stop booting one of those? That's right, there is nothing to stop that at present. The verification happens either on each image (for per-image signing) or on the selected configuration as a whole (in fit_image_load() when it sees the kernel being loaded). One simple solution might be to check a CONFIG option in boot_get_kernel() and disable support for IMAGE_FORMAT_LEGACY. The question is here, do we introduce a new config option for this, or do we use for example CONFIG_FIT_SIGNATURE to disable it? I prefer to check CONFIG_FIT_SIGNATURE, and disable IMAGE_FORMAT_LEGACY complete. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 00/10] ARMv7: add PSCI support to U-Boot
On Mon, May 05 2014 at 3:34:31 pm BST, Jon Loeliger loeli...@gmail.com wrote: Mark, Not sure on which patch of your series to base the following comment, but thought it was worth bringing up for discussion nevertheless. So, over in U-Boot ARMv7's arch/arm/cpu/armv7/start.S code, there is a bit of code under the enty-point named cpu_init_cp15 that does some I-Cache/MMU/state and Errata fi-xup for the boot CPU. As it should. That's all splendid. However, any secondary CPU coming out of reset *after* the U-Boot is gone and only the secure monitor remains will still need to execute code that is substantially similar if not exactly the same. That means the same code block (that cpu_init_cp15 code) needs to be assembled into the original out-of-reset sequence for the boot CPU, and also needs to be assembled into the secure monitor code for secondary CPU out-of-reset sequences. We clearly can not directly refactor that function, extracting it and reusing it wiith the same entry-point as it needs to be linked into two different sections. We could put it in some header file and #include it into both places. We could define a macro and instantiate it in each place. We could do some hacky assemble it twice with different names thing. Thoughts? Yes, that makes perfect sense. Can we put this into a separate object file and play some link-time hackery instead? Otherwise, the include thingy seems fine. Cheers, M. -- Without deviation from the norm, progress is not possible. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Porting New Board
Hey guys, I am new to u-Boot and New to porting android software / bootloaders ETC,... to new hardware. I Posses the 2 following samsung devices, 1) The Samsung Tab Pro 10.1 SM-T520 product name Picassowifi and 2) the Canadian d2LTE qualcom Galaxy s3 I desire to port u-Boot to the SM-T520 and I have just this side of no idea where to start. Could anyone help me out a bit and get me started? My Dev environment is a Ubuntu Vm on my laptop and I have downloaded quite a few different resources and toolchains already for compiling android software. Thanks, David Nelson ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] trats2: config: fix: Set default console to ttySAC2
Dear Lukasz Majewski, On 09/04/14 17:44, Lukasz Majewski wrote: During providing device tree support for Exynos4 based boards, a tiny mistake has creeped in the 1ecab0f commit. This commit restores proper setting of default console for the trats2 board. Signed-off-by: Lukasz Majewski l.majew...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/trats2.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index aee9ee2..0760309 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -53,7 +53,7 @@ #define CONFIG_BOOTARGS Please use defined boot #define CONFIG_BOOTCOMMAND run mmcboot -#define CONFIG_DEFAULT_CONSOLE console=ttySAC1,115200n8\0 +#define CONFIG_DEFAULT_CONSOLE console=ttySAC2,115200n8\0 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] trats: config: fix: Set default console to ttySAC2
Dear Lukasz Majewski, On 09/04/14 17:44, Lukasz Majewski wrote: During providing device tree support for Exynos4 based boards, a tiny mistake has creeped in the fe60164 commit. This commit restores proper setting of default console for the trats board. Signed-off-by: Lukasz Majewski l.majew...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/trats.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/trats.h b/include/configs/trats.h index bf2c869..1d81a29 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -60,7 +60,7 @@ #define CONFIG_BOOTARGS Please use defined boot #define CONFIG_BOOTCOMMAND run mmcboot -#define CONFIG_DEFAULT_CONSOLE console=ttySAC1,115200n8\0 +#define CONFIG_DEFAULT_CONSOLE console=ttySAC2,115200n8\0 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 5/5] samsung: misc: remove download mode info screen
Dear Przemyslaw Marczak,
On 06/05/14 17:45, Przemyslaw Marczak wrote:
Hello Minkyu,
On 05/05/2014 03:27 PM, Minkyu Kang wrote:
Dear Przemyslaw Marczak,
On 30 April 2014 20:28, Przemyslaw Marczak p.marc...@samsung.com
mailto:p.marc...@samsung.com wrote:
This change removes LCD menu download mode info screen.
Now key press timeout is checked in function download_menu()
and menu options are displayed directly after PWR + VOLUP keys.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
mailto:p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com mailto:mk7.k...@samsung.com
---
Changes v4:
- new commit
Changes v5:
- none
---
board/samsung/common/misc.c | 73
+++--
1 file changed, 31 insertions(+), 42 deletions(-)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 2ea275e..03106fd 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -261,7 +261,7 @@ static void display_download_menu(int mode)
selection[mode] = [=];
lcd_clear();
- lcd_printf(\n\t\tDownload Mode Menu\n);
+ lcd_printf(\n\n\t\tDownload Mode Menu\n\n);
for (i = 0; i = BOOT_MODE_EXIT; i++)
lcd_printf(\t%s %s - %s\n\n, selection[i],
@@ -274,10 +274,38 @@ static void download_menu(void)
int mode = 0;
int last_mode = 0;
int run;
- int key;
+ int key = 0;
+ int timeout = 15; /* sec */
+ int i;
display_download_menu(mode);
+ lcd_puts(\n);
+
+ /* Start count if no key is pressed */
+ while (check_keys())
+ continue;
+
+ while (timeout--) {
+ lcd_printf(\r\tNormal boot will start in: %2.d
seconds.,
+ timeout);
+
+ /* about 1000 ms in for loop */
+ for (i = 0; i 10; i++) {
+ mdelay(100);
+ key = check_keys();
+ if (key)
+ break;
+ }
+ if (key)
maybe, unnecessary if statement.
Please take a notice that there are two loops: while and for,
so the second if (key) is necessary for break a while loop on user
event.
Ah, I see :)
actually, I doubt that need to two loops... anyway OK.
Thanks,
Minkyu Kang.
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[U-Boot] [PATCH] arm, davinci: Use CONFIG_SPL_PAD_TO for padding the SPL in an ais image
The commits commit b7b5f1a16ca66dfdd817e7339f0e263a5b9f2758 Author: Albert ARIBAUD albert.u.b...@aribaud.net da850evm, da850_am18xxevm: convert to CONFIG_SPL_MAX_FOOTPRINT and commit e7497891e34efe5cb2b3a3dc7c6c096c012ede28 Author: Albert ARIBAUD albert.u.b...@aribaud.net cam_enc_4xx: convert to CONFIG_SPL_MAX_FOOTPRINT replaced CONFIG_SPL_MAX_SIZE by CONFIG_SPL_MAX_FOOTPRINT. However, CONFIG_SPL_MAX_SIZE is used in the Makefile for padding the SPL when preparing an u-boot.ais image. By removing CONFIG_SPL_MAX_SIZE said commits broke the ais image of the da850evm and cam_enc_4xx configurations. This patch converts the u-boot.ais target to use CONFIG_SPL_PAD_TO instead of CONFIG_SPL_MAX_SIZE for padding the SPL and adds a #define CONFIG_SPL_PAD_TO where it is required. Signed-off-by: Christian Riesch christian.rie...@omicron.at Reported-by: Tom Taylor ttaylor.ta...@gmail.com Cc: Sudhakar Rajashekhara sudhakar@ti.com Cc: Heiko Schocher h...@denx.de Cc: Albert ARIBAUD albert.u.b...@aribaud.net --- Sent again since date was wrong in my earlier email. Sorry for that. Christian Makefile |2 +- include/configs/da850evm.h |1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ff38a43..869f442 100644 --- a/Makefile +++ b/Makefile @@ -890,7 +890,7 @@ MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \ spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) -OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE) +OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE $(call if_changed,pad_cat) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 509fe20..0ca0c8d 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -386,6 +386,7 @@ #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_TEXT_BASE 0x8000 #define CONFIG_SPL_MAX_FOOTPRINT 32768 +#define CONFIG_SPL_PAD_TO 32768 #endif /* Load U-Boot Image From MMC */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] gpio: at91: add sanity check for the NULL pointer
We need check the NULL pointer as at91_pio_get_port() may return NULL.
Also print a error message when at91_pio_get_port() failed otherwise we
cannot notice the failure.
Signed-off-by: Josh Wu josh...@atmel.com
---
drivers/gpio/at91_gpio.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 0b70071..6517af1 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -34,6 +34,7 @@ static struct at91_port *at91_pio_get_port(unsigned port)
#endif
#endif
default:
+ printf(Error: at91_gpio: Fail to get PIO base!\n);
return NULL;
}
}
@@ -200,7 +201,7 @@ int at91_set_pio_output(unsigned port, u32 pin, int value)
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if ((port ATMEL_PIO_PORTS) (pin 32)) {
+ if (at91_port (port ATMEL_PIO_PORTS) (pin 32)) {
mask = 1 pin;
writel(mask, at91_port-idr);
writel(mask, at91_port-pudr);
--
1.7.9.5
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Re: [U-Boot] [PATCH v2] lib:crc32: Allow setting of the initial crc32 value
On Wednesday, May 07, 2014 at 08:10:20 AM, Lukasz Majewski wrote:
[...]
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -255,9 +255,12 @@ uint32_t ZEXPORT crc32_wd (uint32_t crc,
void crc32_wd_buf(const unsigned char *input, unsigned int ilen,
unsigned char *output, unsigned int chunk_sz)
{
- uint32_t crc;
+ uint32_t crc = 0;
- crc = crc32_wd(0, input, ilen, chunk_sz);
+ if (*output)
+ memcpy(crc, output, sizeof(crc));
Won't some sort of put_unaligned() work here ? The $crc is uint32_t afterall,
so
it might be a jiff faster. Please correct me if I'm wrong.
+
+ crc = crc32_wd(crc, input, ilen, chunk_sz);
crc = htonl(crc);
memcpy(output, crc, sizeof(crc));
}
Best regards,
Marek Vasut
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[U-Boot] [PATCH] powerpc/mpc85xx: Added B4460 support
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: Sandeep Singh sand...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/cpu.c |1 +
arch/powerpc/include/asm/processor.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 35795c4..216418b 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -64,6 +64,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T4160, T4160, 0),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
+ CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index 72f30fe..5d7d26e 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1116,6 +1116,7 @@
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
+#define SVR_B4460 0x868003
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
--
1.7.6.GIT
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Re: [U-Boot] [PATCHv2] ARM: exynos: remove the unused code
On 30/04/14 09:09, Jaehoon Chung wrote: mmc boot command didn't use anywhere. It can be replace mmc dev command. Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com --- Changelog v2: - Fixed the different address for loading and uploading. include/configs/s5pc210_universal.h |7 ++- include/configs/trats.h |7 ++- include/configs/trats2.h| 11 +++ 3 files changed, 7 insertions(+), 18 deletions(-) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mmc: atmel_mci: fix print incorrect buffer content for debug
Signed-off-by: Josh Wu josh...@atmel.com
---
drivers/mmc/gen_atmel_mci.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index acca026..eb2fe1c 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -244,7 +244,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct
mmc_data *data)
if (data-flags MMC_DATA_READ)
{
printf(Read Data:\n);
- print_buffer(0, data-dest, 1,
+ print_buffer(0, data-dest + word_count * 4 *
block_count, 1,
word_count*4, 0);
}
#endif
--
1.7.9.5
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[U-Boot] REGARDING UPDATION OF UBOOT AND UBL
Hello , I am a newbie to linux internals.I am trying to do a firmware updation scheme by combining ubl,uboot,kernel and filesystem for davinci processor.i suceed in making an image comprising of all four. I am confused whether this scheme works or not. I dont know how to integrate the headers to both ubl and uboot image. I think if i can integrate headers to uboot and ubl binary i can suceed in my firmware updation scheme.plz help.Thank you for your attention. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
Hi Tim,
On 06/05/2014 20:18, Tim Harvey wrote:
Stefano / York,
While preparing for a v3 patch series of my IMX6 SPL bootloader, I
find that commit dec1861be90c948ea9fb771927d3d26a994d2e20 [1] breaks
the above code because gd is now needed within setup_i2c.
I've always been a bit fuzzy on the order of the above calls so I dug
through the code and I think I understand things better. Please
correct any wrong assumptions I'm making below:
- assignment to gd should 'always' be first (before anything needs
it, so why not do it first)
- arch_cpu_init() should go next as this sets up very low level
CPU/SoC resources (in this case AIPS config and watchdog disable)
- board_early_init_f() should be next as that sets up any board-specific
iomux
- any additional iomux necessary for SPL should go next (I take care
of i2c iomux and setup here)
- timer_init() next as you need a timer for UART and mxc i2c (for
delays and busy checks)
- preloader_console_init() next as we are now able to send something
over the UART (this gives me early debug for sdram config now too!)
- sdram setup goes next
- after sdram is setup, the bss can be cleared
- board_init_r - pass over to generic SPL code which will load/call
an image based on boot device
I think your analyses is correct.
So, if the above is correct, I should rework the above function as follows:
void board_init_f(ulong dummy)
{
struct ventana_board_info ventana_info;
int board_model;
/* Set global data pointer. */
gd = gdata;
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* read/validate EEPROM info to determine board model and SDRAM cfg */
board_model = read_eeprom(I2C_GSC, ventana_info);
/* provide some some default: 32bit 128MB */
if (GW_UNKNOWN == board_model) {
ventana_info.sdram_width = 2;
ventana_info.sdram_size = 3;
}
/* configure MMDC for SDRAM width/size and per-model calibration */
spl_dram_init(8 ventana_info.sdram_width,
16 ventana_info.sdram_size,
board_model);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
It seems reasonable, go on this way.
Regards,
Stefano
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Re: [U-Boot] [PATCH v2] lib:crc32: Allow setting of the initial crc32 value
Hi Marek,
On Wednesday, May 07, 2014 at 08:10:20 AM, Lukasz Majewski wrote:
[...]
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -255,9 +255,12 @@ uint32_t ZEXPORT crc32_wd (uint32_t crc,
void crc32_wd_buf(const unsigned char *input, unsigned int ilen,
unsigned char *output, unsigned int chunk_sz)
{
- uint32_t crc;
+ uint32_t crc = 0;
- crc = crc32_wd(0, input, ilen, chunk_sz);
+ if (*output)
+ memcpy(crc, output, sizeof(crc));
Won't some sort of put_unaligned() work here ? The $crc is uint32_t
afterall, so it might be a jiff faster.
We are concerned here with the use case of copying 4 bytes from
unaligned buffer defined on some architectures.
I suppose, that the performance would be the same for both.
However, since memcpy() is already used in this function, I would
prefer to use it here.
Please correct me if I'm
wrong.
+
+ crc = crc32_wd(crc, input, ilen, chunk_sz);
crc = htonl(crc);
memcpy(output, crc, sizeof(crc));
}
Best regards,
Marek Vasut
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH v2] lib:crc32: Allow setting of the initial crc32 value
Dear Lukasz Majewski, In message 1399443021-11748-1-git-send-email-l.majew...@samsung.com you wrote: The current approach set the initial value of crc32 calculation to zero, which is correct for calculating checksum of the whole chunk of data. ... + if (*output) + memcpy(crc, output, sizeof(crc)); + + crc = crc32_wd(crc, input, ilen, chunk_sz); crc = htonl(crc); memcpy(output, crc, sizeof(crc)); You can actually remove the if (*output) because output has always to be a non-null pointer, as we're going to store the result there. Which means that you cannot use this to implicitly initialize crc =0, whichin turn means you MUST add porper initialization to all callers of that function. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Die Freiheit des Menschen liegt nicht darin, dass er tun kann, was er will, sondern darin, dass er nicht tun muss, was er nicht will. -- Jean-Jacques Rousseau ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM: zynq: sdhci clock frequency init question
Hi Krunal, sorry for delay. On 04/25/2014 06:19 PM, Krunal Desai wrote: Hi all - I noticed that in zynq_sdhci.c, responsible for initializing PS SD controller(s), host controller max clock frequency is always set to 52MHz (http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/mmc/zynq_sdhci.c;h=fdce2c2c10ec85c4a291532f927eae4a0b5627c9;hb=master#l34). In cases where user is using EMIO connectivity, max clock speed is limited to 25MHz. This results in out-of-spec operation as the divider calculation logic trusts the input to add_sdhci() and does not check the SLCR itself to confirm what the IO clock to SD controller actually is. I think I saw OF/device-tree support patched in recently (I am on the 2013.4 tag); I think the right way to solve this is add capability in zynq_sdhci_init to read device-tree for 'clock-frequency' property, and use that to populate the arguments to add_sdhci() with that information, defaulting to a safe minimum (25MHz?) if no entry is found. Otherwise, I suppose a config could be added akin to 'ZYNQ_SD0_MIO'/'ZYNQ_SD1_MIO' to populate the correct minimum value. Does this sound sane? I am thinking of implementing that as a patch for ourselves internally, but I think it will be of value to the greater community as well. we didn't test this configuration that's why 52MHz is there as default case. I think that should be easily possible to detect MIO setting as we are doing for qspi/nand/usb. We have this code in our xilinx repository and I have sent patches for mainline review 2 weeks ago or something like that. I haven't got any NACK and I am going to send pull request to ARM custodian when I fix fpga patches. It means detection via MIO setting is reasonable way how to do it. When you know that this go through EMIO 25MHz should be used. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] lib:crc32: Allow setting of the initial crc32 value
Hi Wolfgang, Dear Lukasz Majewski, In message 1399443021-11748-1-git-send-email-l.majew...@samsung.com you wrote: The current approach set the initial value of crc32 calculation to zero, which is correct for calculating checksum of the whole chunk of data. ... + if (*output) + memcpy(crc, output, sizeof(crc)); + + crc = crc32_wd(crc, input, ilen, chunk_sz); crc = htonl(crc); memcpy(output, crc, sizeof(crc)); You can actually remove the if (*output) because output has always to be a non-null pointer, as we're going to store the result there. I think, that the above statement would be correct if I had checked the if (output). The problem here is that *output refers to uint8 and only first/last byte is checked. This is obviously wrong. You are right that this check is not needed. Which means that you cannot use this to implicitly initialize crc =0, whichin turn means you MUST add porper initialization to all callers of that function. Ok. Best regards, Wolfgang Denk -- Best regards, Lukasz Majewski Samsung RD Institute Poland (SRPOL) | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 8/8] [omap3][overo] Allow overo to boot with device tree
On Tue, May 06, 2014 at 04:56:08PM -0700, Ash Charles wrote: On Tue, May 6, 2014 at 11:14 AM, Tom Rini tr...@ti.com wrote: Please see DEFAULT_LINUX_BOOT_ENV and the related discussions. If you have less than 128MB DDR we can sort something out, but if you have 256MB it's really advised to use 0x8800 for the DT (see Documentation/arm/Booting in the kernel). Overo doesn't pull in the configuration from include/configs/ti_armv7_common.h where DEFAULT_LINUX_BOOT_ENV is defined. Might a v2 using the settings defined by DEFAULT_LINUX_BOOT_ENV in the overo config be acceptable? I'd like to start by seeing if we can adopt the files (ti_omap3_common.h which grabs ti_armv7_common.h). The intention is to have the really common parts there and the board specific elsewhere. It's indeed not quite perfect and we probably need to push a few things back up to the board, even if they're repeated frequently. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] lib:crc32:hash: Allow setting of the initial crc32 value
The current approach set the initial value of crc32 calculation to zero,
which is correct for calculating checksum of the whole chunk of data.
It however, lacks the flexibility, when one wants to calculate CRC32 of
a file comprised of many smaller parts received separately.
In the proposed approach the output value is used as a starting condition
for the proper crc32 calculation at crc32_wd function. This behavior is
identical to the one provided by crc32() method implementation.
Additionally comments were appropriately updated.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Cc: Marek Vasut ma...@denx.de
---
Changes for v2:
- Replace casting from (u8*) to (u32*) with memcpy
Changes for v3:
- Remove check on the output pointer
- As precaution, zero out the output buffer
---
common/hash.c|6 ++
include/hash.h |2 +-
include/u-boot/crc.h |3 ++-
lib/crc32.c |3 ++-
4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/common/hash.c b/common/hash.c
index 7627b84..84c0a78 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -360,6 +360,12 @@ int hash_command(const char *algo_name, int flags,
cmd_tbl_t *cmdtp, int flag,
u8 vsum[HASH_MAX_DIGEST_SIZE];
void *buf;
+ /*
+* This is a precaution for crc32, which allows output to be
+* overloaded to provide initial value of crc32.
+*/
+ memset(output, 0, sizeof(output));
+
if (hash_lookup_algo(algo_name, algo)) {
printf(Unknown hash algorithm '%s'\n, algo_name);
return CMD_RET_USAGE;
diff --git a/include/hash.h b/include/hash.h
index dc21678..abf704d 100644
--- a/include/hash.h
+++ b/include/hash.h
@@ -101,7 +101,7 @@ int hash_command(const char *algo_name, int flags,
cmd_tbl_t *cmdtp, int flag,
* @algo_name: Hash algorithm to use
* @data: Data to hash
* @len: Lengh of data to hash in bytes
- * @output:Place to put hash value
+ * @output:Place to put hash value - also the initial value (crc32)
* @output_size: On entry, pointer to the number of bytes available in
* output. On exit, pointer to the number of bytes used.
* If NULL, then it is assumed that the caller has
diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h
index 754ac72..7a87911 100644
--- a/include/u-boot/crc.h
+++ b/include/u-boot/crc.h
@@ -19,7 +19,8 @@ uint32_t crc32_no_comp (uint32_t, const unsigned char *,
uint);
*
* @input: Input buffer
* @ilen: Input buffer length
- * @output:Place to put checksum result (4 bytes)
+ * @output:Place to provide initial CRC32 value and afterwards
+ * put checksum result (4 bytes)
* @chunk_sz: Trigger watchdog after processing this many bytes
*/
void crc32_wd_buf(const unsigned char *input, uint ilen,
diff --git a/lib/crc32.c b/lib/crc32.c
index 9759212..f57eb87 100644
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -257,7 +257,8 @@ void crc32_wd_buf(const unsigned char *input, unsigned int
ilen,
{
uint32_t crc;
- crc = crc32_wd(0, input, ilen, chunk_sz);
+ memcpy(crc, output, sizeof(crc));
+ crc = crc32_wd(crc, input, ilen, chunk_sz);
crc = htonl(crc);
memcpy(output, crc, sizeof(crc));
}
--
1.7.10.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/9] fpga: spartan2: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
board/esd/pmc440/fpga.c | 2 +-
board/matrix_vision/mvsmr/fpga.c | 2 +-
drivers/fpga/spartan2.c | 40
drivers/fpga/xilinx.c| 14 +++---
include/spartan2.h | 32
include/xilinx.h | 2 +-
6 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index b7b62dd94dbb..cef205088270 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -47,7 +47,7 @@ Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
};
#endif
-Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
+xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_pre_config_fn,
ngcc_fpga_pgm_fn,
ngcc_fpga_clk_fn,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index 88035a9e9e39..639bc7c75b9d 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -27,7 +27,7 @@ Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
};
Xilinx_desc spartan3 = {
- Xilinx_Spartan2,
+ xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
(void *) fpga_fns,
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 6eab1b51e556..bd317095c656 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -31,29 +31,29 @@
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
+static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_sp_info(Xilinx_desc *desc ); */
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
+static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_ss_info(Xilinx_desc *desc ); */
/* - */
/* Spartan-II Generic Implementation */
-int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Load\n, __FUNCTION__);
- ret_val = Spartan2_ss_load (desc, buf, bsize);
+ ret_val = spartan2_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Load\n, __FUNCTION__);
- ret_val = Spartan2_sp_load (desc, buf, bsize);
+ ret_val = spartan2_sp_load(desc, buf, bsize);
break;
default:
@@ -64,19 +64,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf,
size_t bsize)
return ret_val;
}
-int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Dump\n, __FUNCTION__);
- ret_val = Spartan2_ss_dump (desc, buf, bsize);
+ ret_val = spartan2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Dump\n, __FUNCTION__);
- ret_val = Spartan2_sp_dump (desc, buf, bsize);
+ ret_val = spartan2_sp_dump(desc, buf, bsize);
break;
default:
@@ -87,7 +87,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int Spartan2_info( Xilinx_desc *desc )
+int spartan2_info(Xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -96,10 +96,10 @@ int Spartan2_info( Xilinx_desc *desc )
/* - */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;/* assume the worst */
- Xilinx_Spartan2_Slave_Parallel_fns *fn = desc-iface_fns;
+ xilinx_spartan2_slave_parallel_fns *fn = desc-iface_fns;
PRINTF (%s: start with interface functions @ 0x%p\n,
[U-Boot] [PATCH v2 2/9] fpga: spartan3: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
board/armadeus/apf27/fpga.c | 4 ++--
board/astro/mcf5373l/fpga.c | 4 ++--
board/balloon3/balloon3.c| 2 +-
board/esd/pmc440/fpga.c | 4 ++--
board/matrix_vision/mvsmr/fpga.c | 2 +-
board/spear/x600/fpga.c | 2 +-
board/teejet/mt_ventoux/mt_ventoux.c | 2 +-
drivers/fpga/spartan3.c | 40 ++--
drivers/fpga/xilinx.c| 14 ++---
include/spartan3.h | 38 +-
include/xilinx.h | 2 +-
11 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
index 0c08c0640ef2..56fde200e794 100644
--- a/board/armadeus/apf27/fpga.c
+++ b/board/armadeus/apf27/fpga.c
@@ -26,7 +26,7 @@
* Spartan2 code is used to download our Spartan 3 :) code is compatible.
* Just take care about the file size
*/
-Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
+xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_pre_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -43,7 +43,7 @@ Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+ {xilinx_spartan3,
slave_parallel,
1196128l/8,
(void *)fpga_fns,
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index c679ad7f65c6..152ff1f58c97 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -363,7 +363,7 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int
cookie)
* relocated at runtime.
* FIXME: relocation not yet working for coldfire, see below!
*/
-Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_pre_config_fn,
xilinx_pgm_fn,
xilinx_clk_fn,
@@ -375,7 +375,7 @@ Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
};
Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+ {xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)xilinx_fns,
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
index 04e0574658ac..4aa66052da9c 100644
--- a/board/balloon3/balloon3.c
+++ b/board/balloon3/balloon3.c
@@ -191,7 +191,7 @@ int fpga_cs_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
-Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index cef205088270..18a1b63088d6 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define USE_SP_CODE
#ifdef USE_SP_CODE
-Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -36,7 +36,7 @@ Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
fpga_post_config_fn,
};
#else
-Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index 639bc7c75b9d..b20745524394 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -16,7 +16,7 @@
#include fpga.h
#include mvsmr.h
-Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+xilinx_spartan3_slave_serial_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
index c06c9947..c26eba42845c 100644
--- a/board/spear/x600/fpga.c
+++ b/board/spear/x600/fpga.c
@@ -163,7 +163,7 @@ static int fpga_wr_fn(int assert_write, int flush, int
cookie)
return assert_write;
}
-static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
+static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c
b/board/teejet/mt_ventoux/mt_ventoux.c
index c32d554ea429..a36176494e42 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -190,7 +190,7 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
-Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
+xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 3edc5c2c66a6..e40abbfb9460 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@
[U-Boot] [PATCH v2 4/9] fpga: xilinx: Avoid CamelCase for in Xilinx_desc
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
board/armadeus/apf27/fpga.c | 2 +-
board/astro/mcf5373l/fpga.c | 2 +-
board/balloon3/balloon3.c| 2 +-
board/esd/pmc440/fpga.c | 2 +-
board/gen860t/fpga.c | 2 +-
board/matrix_vision/mvsmr/fpga.c | 2 +-
board/spear/x600/fpga.c | 2 +-
board/teejet/mt_ventoux/mt_ventoux.c | 2 +-
board/xilinx/zynq/board.c| 14 +++---
drivers/fpga/spartan2.c | 26 +-
drivers/fpga/spartan3.c | 26 +-
drivers/fpga/virtex2.c | 22 +++---
drivers/fpga/xilinx.c| 14 +++---
drivers/fpga/zynqpl.c| 6 +++---
include/spartan2.h | 6 +++---
include/spartan3.h | 6 +++---
include/virtex2.h| 6 +++---
include/xilinx.h | 10 +-
include/zynqpl.h | 6 +++---
19 files changed, 79 insertions(+), 79 deletions(-)
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
index 56fde200e794..7d6e1e462c99 100644
--- a/board/armadeus/apf27/fpga.c
+++ b/board/armadeus/apf27/fpga.c
@@ -42,7 +42,7 @@ xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_post_fn,
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_parallel,
1196128l/8,
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index 152ff1f58c97..9dc82c5737c2 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -374,7 +374,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_fastwr_fn
};
-Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
index 4aa66052da9c..aa108ca15390 100644
--- a/board/balloon3/balloon3.c
+++ b/board/balloon3/balloon3.c
@@ -207,7 +207,7 @@ xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
(void *)balloon3_fpga_fns, 0);
/* Initialize the FPGA */
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index 18a1b63088d6..f876da855b13 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -57,7 +57,7 @@ xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(
#ifdef USE_SP_CODE
slave_parallel,
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index 48a4222ac410..dd0ef707d6d5 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -56,7 +56,7 @@ xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index b20745524394..518992578c1e 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -26,7 +26,7 @@ xilinx_spartan3_slave_serial_fns fpga_fns = {
0
};
-Xilinx_desc spartan3 = {
+xilinx_desc spartan3 = {
xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
index c26eba42845c..b256222e1864 100644
--- a/board/spear/x600/fpga.c
+++ b/board/spear/x600/fpga.c
@@ -173,7 +173,7 @@ static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
fpga_post_config_fn,
};
-static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(slave_serial, x600_fpga_fns, 0)
};
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c
b/board/teejet/mt_ventoux/mt_ventoux.c
index a36176494e42..b4a0a72bd0fe 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -200,7 +200,7 @@ xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
+xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
(void *)mt_ventoux_fpga_fns, 0);
/* Initialize the FPGA */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 485a5e4a2492..c8cc2bc93446 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -14,15 +14,15 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FPGA
-Xilinx_desc fpga;
+xilinx_desc fpga;
[U-Boot] [PATCH v2 3/9] fpga: virtex2: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
board/gen860t/fpga.c | 4 ++--
drivers/fpga/virtex2.c | 34 +-
drivers/fpga/xilinx.c | 14 +++---
include/virtex2.h | 34 +-
include/xilinx.h | 2 +-
5 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index b7984dd0fec1..48a4222ac410 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Note that these are pointers to code that is in Flash. They will be
* relocated at runtime.
*/
-Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
+xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -57,7 +57,7 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Virtex2,
+ {xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
(void *) fpga_fns,
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index b5a895d41a73..1cd9046a2487 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -84,25 +84,25 @@
#define CONFIG_SYS_FPGA_WAIT_CONFIGCONFIG_SYS_HZ/5 /* 200 ms */
#endif
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Load\n, __FUNCTION__);
- ret_val = Virtex2_ss_load (desc, buf, bsize);
+ ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
PRINTF (%s: Launching Slave Parallel Load\n, __FUNCTION__);
- ret_val = Virtex2_ssm_load (desc, buf, bsize);
+ ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
@@ -112,19 +112,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf,
size_t bsize)
return ret_val;
}
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Dump\n, __FUNCTION__);
- ret_val = Virtex2_ss_dump (desc, buf, bsize);
+ ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Dump\n, __FUNCTION__);
- ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+ ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
@@ -134,7 +134,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int Virtex2_info (Xilinx_desc * desc)
+int virtex2_info(Xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -153,10 +153,10 @@ int Virtex2_info (Xilinx_desc * desc)
*INIT_B and DONE lines. If both are high, configuration has
*succeeded. Congratulations!
*/
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc-iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc-iface_fns;
PRINTF (%s:%d: Start with interface functions @ 0x%p\n,
__FUNCTION__, __LINE__, fn);
@@ -352,10 +352,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void
*buf, size_t bsize)
/*
* Read the FPGA configuration data
*/
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc-iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc-iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
@@ -404,13 +404,13 @@ static int
[U-Boot] [PATCH v2 5/9] fpga: xilinx: Fix the rest of CamelCases
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Fix compilation errors in Astro
board/astro/mcf5373l/fpga.c | 38 +++---
include/spartan2.h | 40
include/spartan3.h | 44 ++--
include/virtex2.h | 34 +-
include/xilinx.h| 42 +-
5 files changed, 99 insertions(+), 99 deletions(-)
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index 9dc82c5737c2..81ec19206577 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -203,7 +203,7 @@ int astro5373l_altera_load(void)
}
/* Set the FPGA's PROG_B line to the specified level */
-int xilinx_pgm_fn(int assert, int flush, int cookie)
+int xilinx_pgm_config_fn(int assert, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@@ -218,7 +218,7 @@ int xilinx_pgm_fn(int assert, int flush, int cookie)
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
* asserted (low).
*/
-int xilinx_init_fn(int cookie)
+int xilinx_init_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@@ -226,7 +226,7 @@ int xilinx_init_fn(int cookie)
}
/* Test the state of the active-high FPGA DONE pin */
-int xilinx_done_fn(int cookie)
+int xilinx_done_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@@ -234,7 +234,7 @@ int xilinx_done_fn(int cookie)
}
/* Abort an FPGA operation */
-int xilinx_abort_fn(int cookie)
+int xilinx_abort_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
/* ensure all SPI peripherals and FPGAs are deselected */
@@ -300,7 +300,7 @@ int xilinx_post_config_fn(int cookie)
return rc;
}
-int xilinx_clk_fn(int assert_clk, int flush, int cookie)
+int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@@ -311,7 +311,7 @@ int xilinx_clk_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
-int xilinx_wr_fn(int assert_write, int flush, int cookie)
+int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@@ -322,7 +322,7 @@ int xilinx_wr_fn(int assert_write, int flush, int cookie)
return assert_write;
}
-int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
+int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
{
size_t bytecount = 0;
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@@ -365,13 +365,13 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush,
int cookie)
*/
xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_pre_config_fn,
- xilinx_pgm_fn,
- xilinx_clk_fn,
- xilinx_init_fn,
- xilinx_done_fn,
- xilinx_wr_fn,
+ xilinx_pgm_config_fn,
+ xilinx_clk_config_fn,
+ xilinx_init_config_fn,
+ xilinx_done_config_fn,
+ xilinx_wr_config_fn,
0,
- xilinx_fastwr_fn
+ xilinx_fastwr_config_fn
};
xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
@@ -395,12 +395,12 @@ int astro5373l_xilinx_load(void)
* so set stuff here instead of static initialisation:
*/
xilinx_fns.pre = xilinx_pre_config_fn;
- xilinx_fns.pgm = xilinx_pgm_fn;
- xilinx_fns.clk = xilinx_clk_fn;
- xilinx_fns.init = xilinx_init_fn;
- xilinx_fns.done = xilinx_done_fn;
- xilinx_fns.wr = xilinx_wr_fn;
- xilinx_fns.bwr = xilinx_fastwr_fn;
+ xilinx_fns.pgm = xilinx_pgm_config_fn;
+ xilinx_fns.clk = xilinx_clk_config_fn;
+ xilinx_fns.init = xilinx_init_config_fn;
+ xilinx_fns.done = xilinx_done_config_fn;
+ xilinx_fns.wr = xilinx_wr_config_fn;
+ xilinx_fns.bwr = xilinx_fastwr_config_fn;
xilinx_fpga[i].iface_fns = (void *)xilinx_fns;
fpga_add(fpga_xilinx, xilinx_fpga[i]);
}
diff --git a/include/spartan2.h b/include/spartan2.h
index 33b25e6b8b94..25db6e7a60db 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -16,30 +16,30 @@ int spartan2_info(xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fncs;
- Xilinx_wr_fnwr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+
[U-Boot] [PATCH v2 7/9] fpga: zynq: Remove sparse warnings
Warnings: drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: None drivers/fpga/zynqpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index dcd34951ad68..0a134e524c44 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -147,9 +147,9 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } /* Loop can be huge - support CTRL + C */ if (ctrlc()) - return 0; + return NULL; } - return 0; + return NULL; } static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) -- 1.8.2.3 pgpMXjUaawk7g.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 8/9] fpga: zynq: Use helper functions for zynq dma
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Use zynq_dma_xfer_init, zynq_align_dma_buffer,
zynq_dma_transfer helper function performing dma
transfers so that the code can be reused easily for
different cases of dma transfer.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/fpga/zynqpl.c | 201 +-
1 file changed, 115 insertions(+), 86 deletions(-)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 0a134e524c44..ef6d1caca410 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -152,70 +152,52 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap)
return NULL;
}
-static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
{
- unsigned long ts; /* Timestamp */
- u32 partialbit = 0;
- u32 i, control, isr_status, status, swap, diff;
- u32 *buf_start;
+ unsigned long ts;
+ u32 isr_status;
- /* Detect if we are going working with partial or full bitstream */
- if (bsize != desc-size) {
- printf(%s: Working with partial bitstream\n, __func__);
- partialbit = 1;
- }
-
- buf_start = check_data((u8 *)buf, bsize, swap);
- if (!buf_start)
- return FPGA_FAIL;
-
- /* Check if data is postpone from start */
- diff = (u32)buf_start - (u32)buf;
- if (diff) {
- printf(%s: Bitstream is not validated yet (diff %x)\n,
- __func__, diff);
- return FPGA_FAIL;
- }
+ /* Set up the transfer */
+ writel((u32)srcbuf, devcfg_base-dma_src_addr);
+ writel(dstbuf, devcfg_base-dma_dst_addr);
+ writel(srclen, devcfg_base-dma_src_len);
+ writel(dstlen, devcfg_base-dma_dst_len);
- if ((u32)buf SZ_1M) {
- printf(%s: Bitstream has to be placed up to 1MB (%x)\n,
- __func__, (u32)buf);
- return FPGA_FAIL;
- }
+ isr_status = readl(devcfg_base-int_sts);
- if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
- u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+ /* Polling the PCAP_INIT status for Set */
+ ts = get_timer(0);
+ while (!(isr_status DEVCFG_ISR_DMA_DONE)) {
+ if (isr_status DEVCFG_ISR_ERROR_FLAGS_MASK) {
+ debug(%s: Error: isr = 0x%08X\n, __func__,
+ isr_status);
+ debug(%s: Write count = 0x%08X\n, __func__,
+ readl(devcfg_base-write_count));
+ debug(%s: Read count = 0x%08X\n, __func__,
+ readl(devcfg_base-read_count));
- /*
-* This might be dangerous but permits to flash if
-* ARCH_DMA_MINALIGN is greater than header size
-*/
- if (new_buf buf_start) {
- debug(%s: Aligned buffer is after buffer start\n,
- __func__);
- new_buf -= ARCH_DMA_MINALIGN;
+ return FPGA_FAIL;
}
+ if (get_timer(ts) CONFIG_SYS_FPGA_PROG_TIME) {
+ printf(%s: Timeout wait for DMA to complete\n,
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(devcfg_base-int_sts);
+ }
- printf(%s: Align buffer at %x to %x(swap %d)\n, __func__,
- (u32)buf_start, (u32)new_buf, swap);
-
- for (i = 0; i (bsize/4); i++)
- new_buf[i] = load_word(buf_start[i], swap);
-
- swap = SWAP_DONE;
- buf = new_buf;
- } else if (swap != SWAP_DONE) {
- /* For bitstream which are aligned */
- u32 *new_buf = (u32 *)buf;
+ debug(%s: DMA transfer is done\n, __func__);
- printf(%s: Bitstream is not swapped(%d) - swap it\n, __func__,
- swap);
+ /* Clear out the DMA status */
+ writel(DEVCFG_ISR_DMA_DONE, devcfg_base-int_sts);
- for (i = 0; i (bsize/4); i++)
- new_buf[i] = load_word(buf_start[i], swap);
+ return FPGA_SUCCESS;
+}
- swap = SWAP_DONE;
- }
+static int zynq_dma_xfer_init(u32 partialbit)
+{
+ u32 status, control, isr_status;
+ unsigned long ts;
/* Clear loopback bit */
clrbits_le32(devcfg_base-mctrl, DEVCFG_MCTRL_PCAP_LPBK);
@@ -297,6 +279,83 @@ static int zynq_load(xilinx_desc *desc, const void *buf,
size_t bsize)
writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, devcfg_base-status);
}
+ return
[U-Boot] [PATCH v2 6/9] fpga: xilinx: Simplify load/dump/info function handling
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Exchange fpga_op and name in xilinx_desc because spartan2/3, virtex2
are not using names.
- Fix warning reported by Tom
board/spear/x600/fpga.c:177:2: warning: initialization from incompatible
pointer type [enabled by default]
board/spear/x600/fpga.c:177:2: warning: (near initialization for
‘fpga[0].name’) [enabled by default]
- Add fix for apf27 and astro
Based on http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/182419
I have checked that symbols are available in u-boot.map.
---
board/armadeus/apf27/fpga.c | 1 +
board/astro/mcf5373l/fpga.c | 3 +-
drivers/fpga/spartan2.c | 12 +++-
drivers/fpga/spartan3.c | 12 +++-
drivers/fpga/virtex2.c | 12 +++-
drivers/fpga/xilinx.c | 159 ++--
drivers/fpga/zynqpl.c | 13 ++--
include/spartan2.h | 28
include/spartan3.h | 36 +-
include/virtex2.h | 28
include/xilinx.h| 7 ++
include/zynqpl.h| 16 ++---
12 files changed, 104 insertions(+), 223 deletions(-)
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
index 7d6e1e462c99..65a4812c35b8 100644
--- a/board/armadeus/apf27/fpga.c
+++ b/board/armadeus/apf27/fpga.c
@@ -48,6 +48,7 @@ xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
1196128l/8,
(void *)fpga_fns,
0,
+spartan3_op,
3s200aft256}
};
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index 81ec19206577..1d044d96a563 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -379,7 +379,8 @@ xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)xilinx_fns,
-0}
+0,
+spartan3_op}
};
/* Initialize the fpga. Return 1 on success, 0 on failure. */
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 0796729436cb..705405614033 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -41,7 +41,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize);
/* - */
/* Spartan-II Generic Implementation */
-int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -64,7 +64,7 @@ int spartan2_load(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -87,7 +87,7 @@ int spartan2_dump(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan2_info(xilinx_desc *desc)
+static int spartan2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -447,3 +447,9 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize)
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan2_op = {
+ .load = spartan2_load,
+ .dump = spartan2_dump,
+ .info = spartan2_info,
+};
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 1304b4c646e3..5c9412c2f63b 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize);
/* - */
/* Spartan-II Generic Implementation */
-int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -68,7 +68,7 @@ int spartan3_load(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -91,7 +91,7 @@ int spartan3_dump(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan3_info(xilinx_desc *desc)
+static int spartan3_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -465,3 +465,9 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize)
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan3_op = {
+ .load = spartan3_load,
+ .dump = spartan3_dump,
+ .info = spartan3_info,
+};
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index
[U-Boot] [PATCH v2 9/9] fpga: zynq: Use helper function zynq_validate_bitstream
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Use helper function zynq_validate_bitstream so that the
code can be reused easily for different cases of dma transfer.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
drivers/fpga/zynqpl.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index ef6d1caca410..c066f21d79f3 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -320,20 +320,20 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32
swap)
return buf;
}
-static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
+ size_t bsize, u32 blocksize, u32 *swap,
+ u32 *partialbit)
{
- unsigned long ts; /* Timestamp */
- u32 partialbit = 0;
- u32 isr_status, swap, diff;
u32 *buf_start;
+ u32 diff;
/* Detect if we are going working with partial or full bitstream */
if (bsize != desc-size) {
printf(%s: Working with partial bitstream\n, __func__);
- partialbit = 1;
+ *partialbit = 1;
}
+ buf_start = check_data((u8 *)buf, blocksize, swap);
- buf_start = check_data((u8 *)buf, bsize, swap);
if (!buf_start)
return FPGA_FAIL;
@@ -351,7 +351,25 @@ static int zynq_load(xilinx_desc *desc, const void *buf,
size_t bsize)
return FPGA_FAIL;
}
- if (zynq_dma_xfer_init(partialbit))
+ if (zynq_dma_xfer_init(*partialbit))
+ return FPGA_FAIL;
+
+ return 0;
+}
+
+
+static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+{
+ unsigned long ts; /* Timestamp */
+ u32 partialbit = 0;
+ u32 isr_status, swap;
+
+ /*
+* send bsize inplace of blocksize as it was not a bitstream
+* in chunks
+*/
+ if (zynq_validate_bitstream(desc, buf, bsize, bsize, swap,
+ partialbit))
return FPGA_FAIL;
buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
--
1.8.2.3
pgpjo2K9G9AgV.pgp
Description: PGP signature
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[U-Boot] [PATCH v2 0/9] FPGA subsystem changes
Hi, Tom reported me one warning in spear board and I have run buildman for all boards which have xilinx_desc in board folder. Below is the report for this patch series. Thanks, Michal [u-boot]$ ./tools/buildman/buildman -b xnext/fpga apf27 zynq spear astro balloon3 pmc440 gen860t mvsmr mt_ventoux -se Summary of 10 commits for 35 boards (4 threads, 1 job per thread) 01: Merge branch 'next' of git://git.denx.de/u-boot-sh m68k: + astro_mcf5373l +/mnt/disk/xnext/fpga/.bm-work/00/arch/m68k/cpu/mcf532x/cpu_init.c: In function 'cpu_init_f': +/mnt/disk/xnext/fpga/.bm-work/00/arch/m68k/cpu/mcf532x/cpu_init.c:211:10: warning: unused variable 'wdog' [-Wunused-variable] +/mnt/disk/xnext/fpga/.bm-work/00/arch/m68k/lib/bootm.c: In function 'do_bootm_linux': +/mnt/disk/xnext/fpga/.bm-work/00/arch/m68k/lib/bootm.c:53:8: warning: unused variable 'rd_len' [-Wunused-variable] +/mnt/disk/xnext/fpga/.bm-work/00/arch/m68k/lib/bootm.c:99:12: warning: 'initrd_start' may be used uninitialized in this function [-Wuninitialized] +/mnt/disk/xnext/fpga/.bm-work/00/arch/m68k/lib/bootm.c:99:12: warning: 'initrd_end' may be used uninitialized in this function [-Wuninitialized] +/mnt/disk/xnext/fpga/.bm-work/00/arch/m68k/lib/bootm.c:99:12: warning: 'cmd_start' may be used uninitialized in this function [-Wuninitialized] +/mnt/disk/xnext/fpga/.bm-work/00/arch/m68k/lib/bootm.c:99:12: warning: 'cmd_end' may be used uninitialized in this function [-Wuninitialized] +/mnt/disk/xnext/fpga/.bm-work/00/board/astro/mcf5373l/mcf5373l.c: In function 'initdram': +/mnt/disk/xnext/fpga/.bm-work/00/board/astro/mcf5373l/mcf5373l.c:83:5: warning: pointer targets in passing argument 1 of 'get_ram_size' differ in signedness [-Wpointer-sign] +/mnt/disk/xnext/fpga/.bm-work/00/include/common.h:470:6: note: expected 'long int *' but argument is of type 'long unsigned int *' +/mnt/disk/xnext/fpga/.bm-work/00/board/astro/mcf5373l/fpga.c:168:2: warning: initialization from incompatible pointer type [enabled by default] +/mnt/disk/xnext/fpga/.bm-work/00/board/astro/mcf5373l/fpga.c:168:2: warning: (near initialization for 'altera_fns.write') [enabled by default] +/mnt/disk/xnext/fpga/.bm-work/00/board/astro/mcf5373l/fpga.c: In function 'astro5373l_altera_load': +/mnt/disk/xnext/fpga/.bm-work/00/board/astro/mcf5373l/fpga.c:196:20: warning: assignment from incompatible pointer type [enabled by default] 02: fpga: spartan2: Avoid CamelCase 03: fpga: spartan3: Avoid CamelCase 04: fpga: virtex2: Avoid CamelCase 05: fpga: xilinx: Avoid CamelCase for in Xilinx_desc 06: fpga: xilinx: Fix the rest of CamelCases 07: fpga: xilinx: Simplify load/dump/info function handling 08: fpga: zynq: Remove sparse warnings 09: fpga: zynq: Use helper functions for zynq dma 10: fpga: zynq: Use helper function zynq_validate_bitstream Changes in v2: - Fix compilation errors in Astro - Exchange fpga_op and name in xilinx_desc because spartan2/3, virtex2 are not using names. - Fix warning reported by Tom board/spear/x600/fpga.c:177:2: warning: initialization from incompatible pointer type [enabled by default] board/spear/x600/fpga.c:177:2: warning: (near initialization for ‘fpga[0].name’) [enabled by default] - Add fix for apf27 and astro Michal Simek (7): fpga: spartan2: Avoid CamelCase fpga: spartan3: Avoid CamelCase fpga: virtex2: Avoid CamelCase fpga: xilinx: Avoid CamelCase for in Xilinx_desc fpga: xilinx: Fix the rest of CamelCases fpga: xilinx: Simplify load/dump/info function handling fpga: zynq: Remove sparse warnings Siva Durga Prasad Paladugu (2): fpga: zynq: Use helper functions for zynq dma fpga: zynq: Use helper function zynq_validate_bitstream board/armadeus/apf27/fpga.c | 7 +- board/astro/mcf5373l/fpga.c | 47 +++ board/balloon3/balloon3.c| 4 +- board/esd/pmc440/fpga.c | 8 +- board/gen860t/fpga.c | 6 +- board/matrix_vision/mvsmr/fpga.c | 6 +- board/spear/x600/fpga.c | 4 +- board/teejet/mt_ventoux/mt_ventoux.c | 4 +- board/xilinx/zynq/board.c| 14 +-- drivers/fpga/spartan2.c | 46 --- drivers/fpga/spartan3.c | 46 --- drivers/fpga/virtex2.c | 40 +++--- drivers/fpga/xilinx.c| 179 +++ drivers/fpga/zynqpl.c| 234 +-- include/spartan2.h | 72 ++- include/spartan3.h | 84 ++--- include/virtex2.h| 66 +- include/xilinx.h | 65 +- include/zynqpl.h | 16 ++- 19 files changed, 438 insertions(+), 510 deletions(-) -- 1.8.2.3 pgp9hMvHeB1YQ.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] drivers/usb : Introduce APIs for fsl usb registers
Introduce new APIs to write fsl usb registers that have w1c bits.
Existing API framework do not take care of w1c bits
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 17 -
include/usb/ehci-fsl.h | 6 ++
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6cb4d98..3be69c4 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -104,15 +104,22 @@ int ehci_hcd_init(int index, enum usb_init_type init,
if (!strncmp(phy_type, utmi, 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
- setbits_be32(ehci-control, PHY_CLK_SEL_UTMI);
- setbits_be32(ehci-control, UTMI_PHY_EN);
+ fsl_usb_setbits(ehci-control, PHY_CLK_SEL_UTMI,
+ CONTROL_REGISTER_W1C_MASK);
+ fsl_usb_setbits(ehci-control, UTMI_PHY_EN,
+ CONTROL_REGISTER_W1C_MASK);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
out_le32((*hcor)-or_portsc[0], PORT_PTS_UTMI);
- setbits_be32(ehci-control, USB_EN);
+ fsl_usb_setbits(ehci-control, USB_EN,
+ CONTROL_REGISTER_W1C_MASK);
} else {
- setbits_be32(ehci-control, PHY_CLK_SEL_ULPI);
- clrsetbits_be32(ehci-control, UTMI_PHY_EN, USB_EN);
+ fsl_usb_setbits(ehci-control, PHY_CLK_SEL_ULPI,
+ CONTROL_REGISTER_W1C_MASK);
+ fsl_usb_clrbits(ehci-control, UTMI_PHY_EN,
+ CONTROL_REGISTER_W1C_MASK);
+ fsl_usb_setbits(ehci-control, USB_EN,
+ CONTROL_REGISTER_W1C_MASK);
udelay(1000); /* delay required for PHY Clk to appear */
if (!usb_phy_clk_valid(ehci))
return -EINVAL;
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index c9ee1d5..fb3d6b4 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -11,6 +11,12 @@
#include asm/processor.h
+#define CONTROL_REGISTER_W1C_MASK 0x0002 /* W1C: PHY_CLK_VALID */
+#define fsl_usb_setbits(_addr, _v, _mask) out_be32((_addr), \
+ ((in_be32(_addr) ~_mask) | _v))
+#define fsl_usb_clrbits(_addr, _v, _mask) out_be32((_addr), \
+ ((in_be32(_addr) ~_mask) ~_v))
+
/* Global offsets */
#define FSL_SKIP_PCI 0x100
--
1.7.11.7
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Re: [U-Boot] Latest u-boot release on BeagleBone Black for FreeBSD
On Wed, 2014-05-07 at 10:09 +0800, Xuebing Wang wrote:
On 05/04/2014 07:33 PM, Jeroen Hofstee wrote:
Hello Xuebing, (freebsd-arm added on cc),
On di, 2014-04-08 at 16:52 +0800, Xuebing Wang wrote:
Hi u-boot community,
I am trying to port u-boot (release u-boot-2014.04-rc3.tar.bz2) to
FreeBSD on BeagleBone Black.
In FreeBSD, there is a u-boot loader (named ubldr), which can call
u-boot API to get fdt (Flat Device Tree) data.
I have to comment out below 3 lines, in order to get correct fdt data in
FreeBSD ubldr from u-boot. Would you please advice what is the best way
to fix this?
In file common/env_common.c:
const uchar *env_get_addr(int index)
{
// if (gd-env_valid)
// return (uchar *)(gd-env_addr + index);
// else
return default_environment[index];
}
Assuming that you checked that your environment is valid you might be
facing the fact that the gd pointer is corrupted. gd is a pointer to the
global data and used for storing globals which are available before
and after relocation. On (32bit) ARM this value used to be stored in
register r8 but moved to r9 (llvm cannot reserve an arbitrary register,
but can reserve r9 for platform specific usage). If ubldr uses r9 you
end up with a invalid gd pointer when calling back into u-boot. ubldr
now reserves r8 and r9 so a recent version should work fine on an older
U-boot as well as current master.
Can you check the latest ubldr?
Hi Jeroen,
Thanks for your response.
1) Today, I tested ubldr in the snapshot build
FreeBSD-11.0-CURRENT-arm-armv6-BEAGLEBONE-20140428-r265054.img.bz2
without commenting out those 3 lines, I still can not get fdt ls in
ubldr command line.
After commenting out those 3 lines and rebuild u-boot, I can get fdt
ls in ubldr command line.
Note: All my previous test was based on
FreeBSD-11.0-CURRENT-arm-armv6-BEAGLEBONE-20140323-r263665.img.bz2
2) Would you please point to me which revision that reserves both r8 and r9?
Thanks.
Regards,
Jeroen
I think you should be debugging this from the ubldr side. If 'fdt ls'
fails to load the dtb when the u-boot global env is present, then what
we need to know is what result is being returned when ubldr looks up the
fdtaddr and/or fdt_addr variables. Does it get an address for the dtb
at all? Is the address invalid? Is it valid but it points to something
that doesn't look like a valid dtb header?
-- Ian
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Re: [U-Boot] [PATCH v4 06/10] ARM: HYP/non-sec: allow relocation to secure RAM
On Wed, May 7, 2014 at 2:05 AM, Marc Zyngier marc.zyng...@arm.com wrote: On Fri, May 02 2014 at 10:03:37 pm BST, Jon Loeliger loeli...@gmail.com wrote: Mark, In your nonsec_init code, you suggest this change: + mrc p15, 0, r0, c1, c1, 2 movwr1, #0x3fff - movtr1, #0x0006 - mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec + movtr1, #0x0004 + orr r0, r0, r1 + mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec Leaving: mrc p15, 0, r0, c1, c1, 2 movwr1, #0x3fff movtr1, #0x0004 orr r0, r0, r1 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec That sets all the co-processor bits, but the man page suggests that only Just to be clear: which document are you referring to? Hmm... Lessee.. Uh, this one: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388i/CIHEAIAJ.html So, Cortex-A9 TRM 4.3.13 That one happens to be r4p1, but the description is the same for my part rev (r2p9, IIRC). Anyway, those low bits are marked as UNK/SBZP, hence my concern for the apparent extra ON bits. copros with bits 10 and 11 should be modified. It also seems that if the The ARM ARM says that NSACR[13:0] is either RAZ/WI or writable from secure for unimplemented coprocessors. The ARM ARM uber alles. :-) So I believe the above is safe. If you wanted to be really picky, you'd start by reading CPACR, write either 1 or 3 to all the CPn fields, read it back again, see what sticks, and populate NSACR accordingly. Did I hear someone saying Boring? ;-) I'm sorry, did you say something? Sounded like you said Waw-waw waw-wah CPn waw ... PLE is enabled, we should mark it NS-enabled at bit 16 also:. Perhaps: mrcp15, 0, r0, c1, c1, 2 movwr1, #0x0c00 movtr1, #0x0005 orrr0, r0, r1 mcrp15, 0, r0, c1, c1, 2@ NSACR = all copros to non-sec We're getting into IMPDEF territory pretty quickly here. PLE only exists on A9, and is optionnal there (and probably doesn't exist on all versions, if memory serves well...). Ah. Gotcha. Blah blah Osprey ah-chew! Gesundheit! This could be implemented as a per-platform optional feature, though. What do you think? I think we should all convert to A57 on a Dickens ring and be done. In the meantime, it's likely not worth it to be this picky about the darn PLE bits, nor the rest of the NSACR bits. Especially if the ARM ARM says we can let it slide. M. -- Without deviation from the norm, progress is not possible. Yes, yes, Everybody got to deviate from the norm. jdl On Wed, May 7, 2014 at 2:05 AM, Marc Zyngier marc.zyng...@arm.com wrote: On Fri, May 02 2014 at 10:03:37 pm BST, Jon Loeliger loeli...@gmail.com wrote: Mark, In your nonsec_init code, you suggest this change: + mrc p15, 0, r0, c1, c1, 2 movwr1, #0x3fff - movtr1, #0x0006 - mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec + movtr1, #0x0004 + orr r0, r0, r1 + mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec Leaving: mrc p15, 0, r0, c1, c1, 2 movwr1, #0x3fff movtr1, #0x0004 orr r0, r0, r1 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec That sets all the co-processor bits, but the man page suggests that only Just to be clear: which document are you referring to? copros with bits 10 and 11 should be modified. It also seems that if the The ARM ARM says that NSACR[13:0] is either RAZ/WI or writable from secure for unimplemented coprocessors. So I believe the above is safe. If you wanted to be really picky, you'd start by reading CPACR, write either 1 or 3 to all the CPn fields, read it back again, see what sticks, and populate NSACR accordingly. Did I hear someone saying Boring? ;-) PLE is enabled, we should mark it NS-enabled at bit 16 also:. Perhaps: mrcp15, 0, r0, c1, c1, 2 movwr1, #0x0c00 movtr1, #0x0005 orrr0, r0, r1 mcrp15, 0, r0, c1, c1, 2@ NSACR = all copros to non-sec We're getting into IMPDEF territory pretty quickly here. PLE only exists on A9, and is optionnal there (and probably doesn't exist on all versions, if memory serves well...). This could be implemented as a per-platform optional feature, though. What do you think? M. -- Without deviation from the norm, progress is not possible. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 06/10] ARM: HYP/non-sec: allow relocation to secure RAM
/* * With the Secure Monitor at 0x0, its reset vector must also * then point off to the correct out-of-reset entry function. */ #define CONFIG_SECURE_MONITOR_RESET_FUNCTION_myplatform_cpu_entry #define CONFIG_ARMV7_SECURE_BASE0x0 That _myplatform_cpu_entry corresponds to your sunxi_cpu_entry code. Yup, makes sense. Nit-pick: make the _secure_reset a weak symbol that your platform code will overload, just like the rest of the PSCI stuff. Saves the #ifdef horror; ;-) Oh, good idea. I'll add that bit in. Thanks! So, yeah, I know that isn't a proper patch and all. :-) I'm just sending you more information to ponder for this patch series! If you would like to generalize your patch this way, please feel free to do so. If not, I can send a proper patch after this hits mainline or so. My prefered way would be indeed to have a proper patch on top of this to handle the coming out of reset case. You'll get proper credit for the idea! :-) Will do. Thanks, jdl ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] am335x: pepper: Add Gumstix Pepper AM335x-based machine
This adds the Gumstix Pepper[1] single-board computer based on the
TI AM335x processor. Schematics are available [2].
[1] https://store.gumstix.com/index.php/products/344/
[2] https://pubs.gumstix.com/boards/PEPPER/
Signed-off-by: Ash Charles a...@gumstix.com
Cc: Tom Rini tr...@ti.com
---
board/gumstix/pepper/Makefile | 13 +++
board/gumstix/pepper/board.c | 226 ++
board/gumstix/pepper/board.h | 19
board/gumstix/pepper/mux.c| 78 +++
boards.cfg| 1 +
include/configs/pepper.h | 99 ++
6 files changed, 436 insertions(+)
create mode 100644 board/gumstix/pepper/Makefile
create mode 100644 board/gumstix/pepper/board.c
create mode 100644 board/gumstix/pepper/board.h
create mode 100644 board/gumstix/pepper/mux.c
create mode 100644 include/configs/pepper.h
diff --git a/board/gumstix/pepper/Makefile b/board/gumstix/pepper/Makefile
new file mode 100644
index 000..ecb1d61
--- /dev/null
+++ b/board/gumstix/pepper/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += mux.o
+endif
+
+obj-y += board.o
diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c
new file mode 100644
index 000..0faf315
--- /dev/null
+++ b/board/gumstix/pepper/board.c
@@ -0,0 +1,226 @@
+/*
+ * Board functions for Gumstix Pepper and AM335x-based boards
+ *
+ * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
+ * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include spl.h
+#include asm/arch/cpu.h
+#include asm/arch/hardware.h
+#include asm/arch/omap.h
+#include asm/arch/ddr_defs.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+#include asm/arch/mmc_host_def.h
+#include asm/arch/sys_proto.h
+#include asm/arch/mem.h
+#include asm/io.h
+#include asm/emif.h
+#include asm/gpio.h
+#include i2c.h
+#include miiphy.h
+#include cpsw.h
+#include power/tps65217.h
+#include environment.h
+#include watchdog.h
+#include board.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifdef CONFIG_SPL_BUILD
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = ((MT47H128M16RT25E_RD_DQS30) |
+ (MT47H128M16RT25E_RD_DQS20) |
+ (MT47H128M16RT25E_RD_DQS10) |
+ (MT47H128M16RT25E_RD_DQS0)),
+ .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS30) |
+ (MT47H128M16RT25E_WR_DQS20) |
+ (MT47H128M16RT25E_WR_DQS10) |
+ (MT47H128M16RT25E_WR_DQS0)),
+ .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL30) |
+(MT47H128M16RT25E_PHY_WRLVL20) |
+(MT47H128M16RT25E_PHY_WRLVL10) |
+(MT47H128M16RT25E_PHY_WRLVL0)),
+ .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL30) |
+(MT47H128M16RT25E_PHY_GATELVL20) |
+(MT47H128M16RT25E_PHY_GATELVL10) |
+(MT47H128M16RT25E_PHY_GATELVL0)),
+ .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE30) |
+ (MT47H128M16RT25E_PHY_FIFO_WE20) |
+ (MT47H128M16RT25E_PHY_FIFO_WE10) |
+ (MT47H128M16RT25E_PHY_FIFO_WE0)),
+ .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA30) |
+ (MT47H128M16RT25E_PHY_WR_DATA20) |
+ (MT47H128M16RT25E_PHY_WR_DATA10) |
+ (MT47H128M16RT25E_PHY_WR_DATA0)),
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = MT47H128M16RT25E_RATIO,
+ .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT47H128M16RT25E_RATIO,
+ .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT47H128M16RT25E_RATIO,
+ .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ return serial_tstc() serial_getc() == 'c';
+}
+#endif
+
+#define OSC(V_OSCK/100)
+const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void
Re: [U-Boot] Latest u-boot release on BeagleBone Black for FreeBSD
On May 6, 2014, at 7:09 PM, Xuebing Wang xbi...@gmail.com wrote: 2) Would you please point to me which revision that reserves both r8 and r9? r258527 | andrew | 2013-11-24 12:33:38 -0800 (Sun, 24 Nov 2013) | 3 lines Recent versions of U-Boot require us to also backup and restore r9 for API calls to work. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Latest u-boot release on BeagleBone Black for FreeBSD
On May 7, 2014, at 8:02 AM, Tim Kientzle t...@kientzle.com wrote: On May 6, 2014, at 7:09 PM, Xuebing Wang xbi...@gmail.com wrote: 2) Would you please point to me which revision that reserves both r8 and r9? r258527 | andrew | 2013-11-24 12:33:38 -0800 (Sun, 24 Nov 2013) | 3 lines Recent versions of U-Boot require us to also backup and restore r9 for API calls to work. And MFCed to Stable-10: r265064 | ian | 2014-04-28 16:46:04 -0700 (Mon, 28 Apr 2014) | 2 lines MFC r257210, r258527: No hardfloat in ubldr, save/restore r9 for api calls. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Mainline u-boot on socfpga (SocKit) board
Hi! I know that mainline U-Boot SPL is quite far from working on socfpga... but would like to ask, what is the status of U-Boot proper. That should work on socfpga, right? Or are there some pieces missing? I tried commit 173d294b94cfec10063a5be40934d6d8fb7981ce Merge: 33b0f7b 870e0bd Author: Tom Rini tr...@ti.com Date: Tue May 6 14:55:45 2014 -0400 Merge branch 'serial' of git://www.denx.de/git/u-boot-microblaze and it just dies with no output. I'd really like to get something close to mainline working, so that I can generate patches etc. Thanks, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] omap4: duovero: Add Gumstix DuoVero machine.
On Tue, May 6, 2014 at 11:06 AM, Tom Rini tr...@ti.com wrote: You really are using uImage and not zImage for this board, but not for pepper? As with Pepper, the default kernel for this DuoVero board is currently a uImage. We're moving to a device tree kernel but having the fall-back to uImage, particularly for customers required to use an old kernel for the hw acceleration, is useful. I'm sending an updated patch on this thread but I understand if the changes to ti_omap4_common can't be included. --Ash ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] omap4: duovero: Add Gumstix DuoVero machine.
This adds the Gumstix DuoVero machine [1]. This is a OMAP4430-based
computer-on-module (COM aka SOM) that can be mounted on various
expansion boards with different peripherals.
[1] https://store.gumstix.com/index.php/category/43/
Signed-off-by: Ash Charles a...@gumstix.com
Cc: Tom Rini tr...@ti.com
---
board/gumstix/duovero/Makefile | 8 +
board/gumstix/duovero/duovero.c | 264 +++
board/gumstix/duovero/duovero_mux_data.h | 199 +++
boards.cfg | 1 +
include/configs/duovero.h| 62
include/configs/ti_omap4_common.h| 9 ++
6 files changed, 543 insertions(+)
create mode 100644 board/gumstix/duovero/Makefile
create mode 100644 board/gumstix/duovero/duovero.c
create mode 100644 board/gumstix/duovero/duovero_mux_data.h
create mode 100644 include/configs/duovero.h
diff --git a/board/gumstix/duovero/Makefile b/board/gumstix/duovero/Makefile
new file mode 100644
index 000..f738c58
--- /dev/null
+++ b/board/gumstix/duovero/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := duovero.o
diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c
new file mode 100644
index 000..5c5f035
--- /dev/null
+++ b/board/gumstix/duovero/duovero.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2013
+ * Gumstix Inc. www.gumstix.com
+ * Maintainer: Ash Charles a...@gumstix.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include common.h
+#include netdev.h
+#include asm/arch/sys_proto.h
+#include asm/arch/mmc_host_def.h
+#include twl6030.h
+#include asm/emif.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+#include asm/gpio.h
+
+#include duovero_mux_data.h
+
+#define WIFI_EN43
+
+#if defined(CONFIG_CMD_NET)
+#define SMSC_NRESET45
+static void setup_net_chip(void);
+#endif
+
+#ifdef CONFIG_USB_EHCI
+#include usb.h
+#include asm/arch/ehci.h
+#include asm/ehci-omap.h
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ Board: duovero\n
+};
+
+struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+
+ gd-bd-bi_arch_number = MACH_TYPE_OMAP4_DUOVERO;
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ int ret = 0;
+ u8 val;
+
+ /* wifi setup: first enable 32Khz clock from 6030 pmic */
+ val = 0xe1;
+ ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, val, 1);
+ if (ret)
+ printf(Failed to enable 32Khz clock to wifi module\n);
+
+ /* then setup WIFI_EN as an output pin and send reset pulse */
+ if (!gpio_request(WIFI_EN, )) {
+ gpio_direction_output(WIFI_EN, 0);
+ gpio_set_value(WIFI_EN, 1);
+ udelay(1);
+ gpio_set_value(WIFI_EN, 0);
+ udelay(1);
+ gpio_set_value(WIFI_EN, 1);
+ }
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+ return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux((*ctrl)-control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)-control_padconf_wkup_base,
+ wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)-control_padconf_core_base,
+ core_padconf_array_non_essential,
+ sizeof(core_padconf_array_non_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)-control_padconf_wkup_base,
+ wkup_padconf_array_non_essential,
+ sizeof(wkup_padconf_array_non_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+
+#if defined(CONFIG_CMD_NET)
+
+#define GPMC_SIZE_16M 0xF
+#define GPMC_BASEADDR_MASK 0x3F
+#define GPMC_CS_ENABLE 0x1
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32
base,
+ u32 size)
+{
+ writel(0, cs-config7);
+ sdelay(1000);
+ /* Delay for settling */
+ writel(gpmc_config[0], cs-config1);
+ writel(gpmc_config[1], cs-config2);
+ writel(gpmc_config[2], cs-config3);
+
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On 05/06/2014 04:35 PM, Tim Harvey wrote: On Tue, May 6, 2014 at 12:11 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote: Hello Tim, snip Since Crt0.S already created gd on the stack before calling board_init_f, can't the assignment of gd not simply be removed? Is there anything special about gdata? Regards, Jeroen Jeroen, That does make sense, but what I find is that York's ocmmit dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked and its not. This causes bus_i2c_init to skip its initialization because p-base is not zero. York, does this make sense? Your patch creates a dependence on gd-srdata being blank which isn't the case with the SRAM when booting from the IMX6 boot rom. GD should be cleared (zeroed). Then we don't have this problem. Whoever sets up gd (board_int_f, cpu_init_f, or others) should make sure gd is cleared. Why isn't it the case for IMX6 boot rom? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/12] IMX: add additional function for pinmux using an array
On 06/05/14 07:35, Tim Harvey wrote:
On Tue, Apr 29, 2014 at 8:22 AM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
snip
The function name ..._array() also doesn't really capture what's
going on here. Naming is hard though, and I'm not coming up
with something else.
Perhaps 'sparse', 'skip', or alternate?
ya, I'm not sure anything else is more explanatory when we are doing
something like this. Its bad enough that its likely difficult for
someone to understand their first time through that we are doing this
to eliminate multiple structs.
Come to think of it, I don't think we need an _array() function at all.
The list selection and
stride size are IOMUX_PADS implementation details. It's not something we
should expose to
the function user. is_cpu_type() and ifdef(CONFIG_MX6QDL) can be used to
decide the
list and stride values inside imx_iomux_v3_setup_multiple_pads(), and
then this function
could be used for both single and multi cpu type situations.
snip
+/* macros for declaring and using pinmux array */
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
In a similar vein to my comment about Patch 8, I do wonder if a
minor extension of this will allow use with a single-variant
board though.
for a single-variant one would just use the original
IOMUX_PAD/imx_iomux_v3_setup_pad/imx_iomux_v3_setup_pad right?
They can, but then we don't get to use the same code for both
situations.
If we define two versions of IOMUX_PADS: one for multi cpu type,
and one for single cpu type, then the pinmux arrays for both
situations will be syntactically similar.
When combined with my other suggestion, it will be very easy to
take a U-Boot configured for one CPU type, and reconfigure it to
support both CPU types.
We have some custom designs that really only function with
one variant (usually i.MX6DQ) and it seems wrong to have
the other variant included.
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def);\
+}
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads_array(x, \
+ ARRAY_SIZE(x)/2, is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1, 2)
+
#endif/* __MACH_IOMUX_V3_H__*/
Please don't mis-interpret my comments as any form of Nack.
This patch moves the ball forward, and the approach of building
two lists into one prevents duplication of tables quite nicely.
Regards,
Eric
Thanks for the review!
Tim
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Regards,
Nikita Kiryanov
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Re: [U-Boot] [PATCH 03/12] MX6: add common SPL configuration
On 28/04/14 23:17, Tim Harvey wrote: Add a common header which can hopefully be shared amon imx6 SPL users Signed-off-by: Tim Harvey thar...@gateworks.com --- v2: - adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD Aside from the typos, Acked-by: Nikita Kiryanov nik...@compulab.co.il -- Regards, Nikita Kiryanov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 8/8] [omap3][overo] Allow overo to boot with device tree
On Wed, May 7, 2014 at 5:40 AM, Tom Rini tr...@ti.com wrote: I'd like to start by seeing if we can adopt the files (ti_omap3_common.h which grabs ti_armv7_common.h). The intention is to have the really common parts there and the board specific elsewhere. It's indeed not quite perfect and we probably need to push a few things back up to the board, even if they're repeated frequently. Thanks Tom. As this is a rather distinct change, I'm sending an additional patch that switches Overo to ti_omap3_common and DEFAULT_LINUX_BOOT_ENV rather than amending the previous patch series. I hope this is appropriate and acceptable as I wasn't sure the policy on such patches after the close date for the merge window. Another newbie question: should I be basing submitted patches off u-boot-ti/master (as I'm using TI chips) or u-boot/master? --Ash ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] omap3: overo: Use common configurations for Overo
Clean-up the board configuration file for the Gumstix Overo board by
including common omap3 definitions from ti_omap3_common.h as suggested
here [1].
[1] http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/185960
Signed-off-by: Ash Charles ashchar...@gmail.com
---
include/configs/omap3_overo.h | 222 ++
1 file changed, 28 insertions(+), 194 deletions(-)
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 71ec437..6798cf4 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -7,80 +7,35 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP/* in a TI OMAP core */
-#define CONFIG_OMAP34XX/* which is a 34XX */
-#define CONFIG_OMAP3_OVERO /* working with overo */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_SDRC/* The chip has SDRC controller
*/
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define CONFIG_NAND
-#include asm/arch/cpu.h /* get chip and board defs */
-#include asm/arch/omap3.h
+#include configs/ti_omap3_common.h
-/*
- * Display CPU and Board information
- */
+/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-/* Clock Defines */
-#define V_OSCK 2600/* Clock output from T2 */
-#define V_SCLK (V_OSCK 1)
-
+/* call misc_init_r */
#define CONFIG_MISC_INIT_R
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
+/* pass the revision tag */
#define CONFIG_REVISION_TAG
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-/*
- * Size of malloc() pool
- */
+/* override size of malloc() pool */
+#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_ENV_SIZE(128 10) /* 128 KiB sector */
-
/* Shift 128 15 provides 4 MiB heap to support UBI commands.
* Shift 128 10 provides 128 KiB heap for limited-memory devices. */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 15))
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 4800/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE(-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3OMAP34XX_UART3
-#define CONFIG_SERIAL3 3
+/* I2C Support */
+#define CONFIG_SYS_I2C_OMAP34XX
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
- 115200}
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_DOS_PARTITION
+/* TWL4030 LED */
+#define CONFIG_TWL4030_LED
+/* Initialize GPIOs by default */
#define CONFIG_OMAP3_GPIO_2/* GPIO32..63 is in GPIO Bank 2 */
#define CONFIG_OMAP3_GPIO_3/* GPIO64..95 is in GPIO Bank 3 */
#define CONFIG_OMAP3_GPIO_4/* GPIO96..127 is in GPIO Bank 4 */
@@ -88,34 +43,18 @@
#define CONFIG_OMAP3_GPIO_6/* GPIO160..191 is in GPIO Bank 6 */
/* commands to include */
-#include config_cmd_default.h
-
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2/* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_FS_GENERIC
-
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NAND/* NAND support */
-
-#undef CONFIG_CMD_FLASH/* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images*/
#undef CONFIG_CMD_NFS /* NFS support */
-#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot*/
-
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS/* MTD partition support */
+#ifdef CONFIG_NAND
#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
-#define CONFIG_MTD_DEVICE /* required by CONFIG_CMD_MTDPARTS */
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* NAND block
Re: [U-Boot] [PATCH] drivers/usb : Introduce APIs for fsl usb registers
Dear Nikhil Badola, In message 1399468595-953-1-git-send-email-nikhil.bad...@freescale.com you wrote: Introduce new APIs to write fsl usb registers that have w1c bits. Existing API framework do not take care of w1c bits Why exactly do we need a new API for that? All you'r doing is adding just more bits to the mask, right? - setbits_be32(ehci-control, PHY_CLK_SEL_UTMI); - setbits_be32(ehci-control, UTMI_PHY_EN); + fsl_usb_setbits(ehci-control, PHY_CLK_SEL_UTMI, + CONTROL_REGISTER_W1C_MASK); + fsl_usb_setbits(ehci-control, UTMI_PHY_EN, + CONTROL_REGISTER_W1C_MASK); ... +#define CONTROL_REGISTER_W1C_MASK 0x0002 /* W1C: PHY_CLK_VALID */ +#define fsl_usb_setbits(_addr, _v, _mask) out_be32((_addr), \ + ((in_be32(_addr) ~_mask) | _v)) +#define fsl_usb_clrbits(_addr, _v, _mask) out_be32((_addr), \ + ((in_be32(_addr) ~_mask) ~_v)) + I cannot understand in which way fsl_usb_setbits(ehci-control, PHY_CLK_SEL_UTMI, CONTROL_REGISTER_W1C_MASK); would be different from setbits_be32(ehci-control, PHY_CLK_SEL_UTMI | CONTROL_REGISTER_W1C_MASK); ? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I am not now, nor have I ever been, a member of the demigodic party. -- Dennis Ritchie ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] mmc: provide a select_hwpart implementation for get_device()
From: Stephen Warren swar...@nvidia.com
This enables specifying which eMMC HW partition to target for any U-Boot
command that uses the generic get_partition() function to parse its
command-line arguments.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
disk/part.c | 6 +-
drivers/mmc/mmc.c | 26 ++
include/part.h| 2 ++
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/disk/part.c b/disk/part.c
index 5e10cae015e5..2827089d8d5f 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -39,7 +39,11 @@ static const struct block_drvr block_drvr[] = {
{ .name = usb, .get_dev = usb_stor_get_dev, },
#endif
#if defined(CONFIG_MMC)
- { .name = mmc, .get_dev = mmc_get_dev, },
+ {
+ .name = mmc,
+ .get_dev = mmc_get_dev,
+ .select_hwpart = mmc_select_hwpart,
+ },
#endif
#if defined(CONFIG_SYSTEMACE)
{ .name = ace, .get_dev = systemace_get_dev, },
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 16051e52ff16..3089d8d807a8 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -550,6 +550,32 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num)
return 0;
}
+int mmc_select_hwpart(int dev_num, int hwpart)
+{
+ struct mmc *mmc = find_mmc_device(dev_num);
+ int ret;
+
+ if (!mmc)
+ return -1;
+
+ if (mmc-part_num == hwpart)
+ return 0;
+
+ if (mmc-part_config == MMCPART_NOAVAILABLE) {
+ printf(Card doesn't support part_switch\n);
+ return -1;
+ }
+
+ ret = mmc_switch_part(dev_num, hwpart);
+ if (ret)
+ return -1;
+
+ mmc-part_num = hwpart;
+
+ return 0;
+}
+
+
int mmc_switch_part(int dev_num, unsigned int part_num)
{
struct mmc *mmc = find_mmc_device(dev_num);
diff --git a/include/part.h b/include/part.h
index 53532dcd6120..f2c8c641faa8 100644
--- a/include/part.h
+++ b/include/part.h
@@ -103,6 +103,7 @@ block_dev_desc_t* sata_get_dev(int dev);
block_dev_desc_t* scsi_get_dev(int dev);
block_dev_desc_t* usb_stor_get_dev(int dev);
block_dev_desc_t* mmc_get_dev(int dev);
+int mmc_select_hwpart(int dev_num, int hwpart);
block_dev_desc_t* systemace_get_dev(int dev);
block_dev_desc_t* mg_disk_get_dev(int dev);
block_dev_desc_t *host_get_dev(int dev);
@@ -126,6 +127,7 @@ static inline block_dev_desc_t* sata_get_dev(int dev) {
return NULL; }
static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; }
+static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t *host_get_dev(int dev) { return NULL; }
--
1.8.1.5
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[U-Boot] [PATCH 4/4] cmd_mmc: use new mmc_select_hwpart() function
From: Stephen Warren swar...@nvidia.com
The implementation of mmc_select_hwpart() was cribbed from do_mmcops().
Update do_mmcops() to call mmc_select_hwpart() to avoid duplication.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
common/cmd_mmc.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index c1916c9b56a6..572aa895fa1c 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -193,7 +193,7 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
print_mmc_devices('\n');
return 0;
} else if (strcmp(argv[1], dev) == 0) {
- int dev, part = -1;
+ int dev, part = -1, ret;
struct mmc *mmc;
if (argc == 2)
@@ -219,20 +219,11 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[])
mmc_init(mmc);
if (part != -1) {
- int ret;
- if (mmc-part_config == MMCPART_NOAVAILABLE) {
- printf(Card doesn't support part_switch\n);
+ ret = mmc_select_hwpart(dev, part);
+ printf(switch to partitions #%d, %s\n,
+ part, (!ret) ? OK : ERROR);
+ if (ret)
return 1;
- }
-
- if (part != mmc-part_num) {
- ret = mmc_switch_part(dev, part);
- if (!ret)
- mmc-part_num = part;
-
- printf(switch to partitions #%d, %s\n,
- part, (!ret) ? OK : ERROR);
- }
}
curr_device = dev;
if (mmc-part_config == MMCPART_NOAVAILABLE)
--
1.8.1.5
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[U-Boot] [PATCH 2/4] disk: support devices with HW partitions
From: Stephen Warren swar...@nvidia.com
Some device types (e.g. eMMC) have hardware-level partitions (for eMMC,
separate boot and user data partitions). This change allows the user to
specify the HW partition they wish to access when passing a device ID to
U-Boot Commands such as part, ls, load, ums, etc.
The syntax allows an optional .$hwpartid to be appended to the device
name string for those commands.
Existing syntax, for MMC device 0, default HW partition ID, SW partition
ID 1:
ls mmc 0:1 /
New syntax, for MMC device 0, HW partition ID 1 (boot0), SW partition
ID 2:
ls mmc 0.1:2 /
For my purposes, this is most useful for the ums (USB mass storage
gadget) command, but there's no reason not to allow the new syntax
globally.
This patch adds the core support infra-structure. The next patch will
provide the implementation for MMC.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
disk/part.c | 74 -
1 file changed, 64 insertions(+), 10 deletions(-)
diff --git a/disk/part.c b/disk/part.c
index b8c6aac80162..5e10cae015e5 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -22,6 +22,7 @@
struct block_drvr {
char *name;
block_dev_desc_t* (*get_dev)(int dev);
+ int (*select_hwpart)(int dev_num, int hwpart);
};
static const struct block_drvr block_drvr[] = {
@@ -52,11 +53,13 @@ static const struct block_drvr block_drvr[] = {
DECLARE_GLOBAL_DATA_PTR;
#ifdef HAVE_BLOCK_DEVICE
-block_dev_desc_t *get_dev(const char *ifname, int dev)
+block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
const struct block_drvr *drvr = block_drvr;
block_dev_desc_t* (*reloc_get_dev)(int dev);
+ int (*select_hwpart)(int dev_num, int hwpart);
char *name;
+ int ret;
if (!ifname)
return NULL;
@@ -68,17 +71,41 @@ block_dev_desc_t *get_dev(const char *ifname, int dev)
while (drvr-name) {
name = drvr-name;
reloc_get_dev = drvr-get_dev;
+ select_hwpart = drvr-select_hwpart;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
name += gd-reloc_off;
reloc_get_dev += gd-reloc_off;
-#endif
- if (strncmp(ifname, name, strlen(name)) == 0)
- return reloc_get_dev(dev);
+ if (select_hwpart)
+ select_hwpart += gd-reloc_off;
+#endif
+ if (strncmp(ifname, name, strlen(name)) == 0) {
+ block_dev_desc_t *dev_desc = reloc_get_dev(dev);
+ if (!dev_desc)
+ return NULL;
+ if (hwpart == -1)
+ return dev_desc;
+ if (!select_hwpart)
+ return NULL;
+ ret = select_hwpart(dev_desc-dev, hwpart);
+ if (ret 0)
+ return NULL;
+ return dev_desc;
+ }
drvr++;
}
return NULL;
}
+
+block_dev_desc_t *get_dev(const char *ifname, int dev)
+{
+ return get_dev_hwpart(ifname, dev, -1);
+}
#else
+block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
+{
+ return NULL;
+}
+
block_dev_desc_t *get_dev(const char *ifname, int dev)
{
return NULL;
@@ -413,25 +440,52 @@ int get_partition_info(block_dev_desc_t *dev_desc, int
part
return -1;
}
-int get_device(const char *ifname, const char *dev_str,
+int get_device(const char *ifname, const char *dev_hwpart_str,
block_dev_desc_t **dev_desc)
{
char *ep;
- int dev;
+ char *dup_str = NULL;
+ const char *dev_str, *hwpart_str;
+ int dev, hwpart;
+
+ hwpart_str = strchr(dev_hwpart_str, '.');
+ if (hwpart_str) {
+ dup_str = strdup(dev_hwpart_str);
+ dup_str[hwpart_str - dev_hwpart_str] = 0;
+ dev_str = dup_str;
+ hwpart_str++;
+ } else {
+ dev_str = dev_hwpart_str;
+ hwpart = -1;
+ }
dev = simple_strtoul(dev_str, ep, 16);
if (*ep) {
printf(** Bad device specification %s %s **\n,
ifname, dev_str);
- return -1;
+ dev = -1;
+ goto cleanup;
+ }
+
+ if (hwpart_str) {
+ hwpart = simple_strtoul(hwpart_str, ep, 16);
+ if (*ep) {
+ printf(** Bad HW partition specification %s %s **\n,
+ ifname, hwpart_str);
+ dev = -1;
+ goto cleanup;
+ }
}
- *dev_desc = get_dev(ifname, dev);
+ *dev_desc = get_dev_hwpart(ifname, dev, hwpart);
if (!(*dev_desc) || ((*dev_desc)-type == DEV_TYPE_UNKNOWN)) {
- printf(** Bad device %s %s **\n,
[U-Boot] [PATCH 1/4] cmd_part: fix type in part command help text
From: Stephen Warren swar...@nvidia.com All the sub-commands start with the main command anme, but it was missing from one of the help texts. Signed-off-by: Stephen Warren swar...@nvidia.com --- common/cmd_part.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_part.c b/common/cmd_part.c index 14248548d9fe..c84bc27b4042 100644 --- a/common/cmd_part.c +++ b/common/cmd_part.c @@ -82,7 +82,7 @@ int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( part, 5, 1, do_part, disk partition related commands, - uuid interface dev:part\n + part uuid interface dev:part\n - print partition UUID\n part uuid interface dev:part varname\n - set environment variable to partition UUID\n -- 1.8.1.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] mmc: provide a select_hwpart implementation for get_device()
On Wed, May 7, 2014 at 3:19 PM, Stephen Warren swar...@wwwdotorg.org wrote:
+int mmc_select_hwpart(int dev_num, int hwpart)
+{
+ struct mmc *mmc = find_mmc_device(dev_num);
+ int ret;
+
+ if (!mmc)
+ return -1;
+
+ if (mmc-part_num == hwpart)
+ return 0;
+
+ if (mmc-part_config == MMCPART_NOAVAILABLE) {
+ printf(Card doesn't support part_switch\n);
+ return -1;
+ }
+
+ ret = mmc_switch_part(dev_num, hwpart);
+ if (ret)
+ return -1;
Can't you return more appropriate return values rather than -1?
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Re: [U-Boot] [PATCH 3/4] mmc: provide a select_hwpart implementation for get_device()
On 05/07/2014 12:22 PM, Fabio Estevam wrote: On Wed, May 7, 2014 at 3:19 PM, Stephen Warren swar...@wwwdotorg.org wrote: +int mmc_select_hwpart(int dev_num, int hwpart) ... + ret = mmc_switch_part(dev_num, hwpart); + if (ret) + return -1; Can't you return more appropriate return values rather than -1? Oh yes, I should return ret there. I'll hold off for a while before posting V2 though. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
Hi, On wo, 2014-05-07 at 09:14 -0700, York Sun wrote: snip Since Crt0.S already created gd on the stack before calling board_init_f, can't the assignment of gd not simply be removed? Is there anything special about gdata? That does make sense, but what I find is that York's ocmmit dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked and its not. This causes bus_i2c_init to skip its initialization because p-base is not zero. York, does this make sense? Your patch creates a dependence on gd-srdata being blank which isn't the case with the SRAM when booting from the IMX6 boot rom. GD should be cleared (zeroed). Then we don't have this problem. Whoever sets up gd (board_int_f, cpu_init_f, or others) should make sure gd is cleared. Why isn't it the case for IMX6 boot rom? Seems fine to me. Albert, any objection against zeroing gd out in crt0.S? And if not, shouldn't the same be done for arm64. Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 10/13] ARM: HYP/non-sec/PSCI: emit DT nodes
On Sat, 2014-02-15 at 13:36 +, Marc Zyngier wrote: @@ -32,5 +33,11 @@ int arch_fixup_fdt(void *blob) size[bank] = bd-bi_dram[bank].size; } - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + if (ret) + return ret; + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) + return armv7_update_dt(blob); +#endif For platforms where neither of these CONFIG_* are set this results in: arch/arm/lib/bootm-fdt.c: In function ‘arch_fixup_fdt’: arch/arm/lib/bootm-fdt.c:43:1: warning: control reaches end of non-void function [-Wreturn-type] } Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: tegra: use a CPU freq that all SKUs can support
Hi Stephen, I was just porting this change to barebox and stumbled upon a few errors here. Am Donnerstag, den 24.04.2014, 13:30 -0600 schrieb Stephen Warren: From: Stephen Warren swar...@nvidia.com [...] diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index 85a945bc7918..0f52e54239e1 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config) writel(config, reg-cnfg); } +#define TPS62366A_I2C_ADDR 0x60 The I2C address for this chip on Beaver is 0xc0, not 0x60. I don't know about Cardhu. +#define TPS62366A_SET1_REG 0x01 +#define TPS62366A_SET1_DATA (0x46 | TPS62366A_SET1_REG) This should be (0x4600 | TPS62366A_SET1_REG). + +#define TPS62361B_I2C_ADDR 0x60 +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x46 | TPS62361B_SET3_REG) Same here. Only with those fixed I can verify vdd_core to ramp up to 1,2V on Beaver. Without the changes vdd_core stays at the default 1,16V. Regards, Lucas ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: tegra: use a CPU freq that all SKUs can support
On 05/07/2014 01:57 PM, Lucas Stach wrote: Hi Stephen, I was just porting this change to barebox and stumbled upon a few errors here. Wow, I suck. Thanks for the heads up. I'll repost a fixed up version soon. Am Donnerstag, den 24.04.2014, 13:30 -0600 schrieb Stephen Warren: diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c +#define TPS62366A_I2C_ADDR 0x60 The I2C address for this chip on Beaver is 0xc0, not 0x60. I don't know about Cardhu. That's a confusion about 7-bit vs 8-bit I2C addresses. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Wed, May 7, 2014 at 9:14 AM, York Sun york...@freescale.com wrote: On 05/06/2014 04:35 PM, Tim Harvey wrote: On Tue, May 6, 2014 at 12:11 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote: Hello Tim, snip Since Crt0.S already created gd on the stack before calling board_init_f, can't the assignment of gd not simply be removed? Is there anything special about gdata? Regards, Jeroen Jeroen, That does make sense, but what I find is that York's ocmmit dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked and its not. This causes bus_i2c_init to skip its initialization because p-base is not zero. York, does this make sense? Your patch creates a dependence on gd-srdata being blank which isn't the case with the SRAM when booting from the IMX6 boot rom. GD should be cleared (zeroed). Then we don't have this problem. Whoever sets up gd (board_int_f, cpu_init_f, or others) should make sure gd is cleared. Why isn't it the case for IMX6 boot rom? York York, crt0.S is mapping gd to where the SPL stack pointer is defined, which is where Freescale says its stack pointer is for its firmware BOOT ROM, so its initial data will be dependent on what the BOOT ROM did. I think the right solution is to have crt0.S zero it out. Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On 05/07/2014 01:27 PM, Tim Harvey wrote: On Wed, May 7, 2014 at 9:14 AM, York Sun york...@freescale.com wrote: On 05/06/2014 04:35 PM, Tim Harvey wrote: On Tue, May 6, 2014 at 12:11 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote: Hello Tim, snip Since Crt0.S already created gd on the stack before calling board_init_f, can't the assignment of gd not simply be removed? Is there anything special about gdata? Regards, Jeroen Jeroen, That does make sense, but what I find is that York's ocmmit dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked and its not. This causes bus_i2c_init to skip its initialization because p-base is not zero. York, does this make sense? Your patch creates a dependence on gd-srdata being blank which isn't the case with the SRAM when booting from the IMX6 boot rom. GD should be cleared (zeroed). Then we don't have this problem. Whoever sets up gd (board_int_f, cpu_init_f, or others) should make sure gd is cleared. Why isn't it the case for IMX6 boot rom? York York, crt0.S is mapping gd to where the SPL stack pointer is defined, which is where Freescale says its stack pointer is for its firmware BOOT ROM, so its initial data will be dependent on what the BOOT ROM did. I think the right solution is to have crt0.S zero it out. Either crt0.S, or somewhere before gd is used for the first time. Can it be done in board_init_f()? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On Wed, May 7, 2014 at 1:29 PM, York Sun york...@freescale.com wrote: On 05/07/2014 01:27 PM, Tim Harvey wrote: On Wed, May 7, 2014 at 9:14 AM, York Sun york...@freescale.com wrote: On 05/06/2014 04:35 PM, Tim Harvey wrote: On Tue, May 6, 2014 at 12:11 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote: Hello Tim, snip Since Crt0.S already created gd on the stack before calling board_init_f, can't the assignment of gd not simply be removed? Is there anything special about gdata? Regards, Jeroen Jeroen, That does make sense, but what I find is that York's ocmmit dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked and its not. This causes bus_i2c_init to skip its initialization because p-base is not zero. York, does this make sense? Your patch creates a dependence on gd-srdata being blank which isn't the case with the SRAM when booting from the IMX6 boot rom. GD should be cleared (zeroed). Then we don't have this problem. Whoever sets up gd (board_int_f, cpu_init_f, or others) should make sure gd is cleared. Why isn't it the case for IMX6 boot rom? York York, crt0.S is mapping gd to where the SPL stack pointer is defined, which is where Freescale says its stack pointer is for its firmware BOOT ROM, so its initial data will be dependent on what the BOOT ROM did. I think the right solution is to have crt0.S zero it out. Either crt0.S, or somewhere before gd is used for the first time. Can it be done in board_init_f()? York It makes more sense to do it in crt0.S so that all boards don't have to do it and can make the assumption that it is cleared. Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/12] imx: ventana: switch to SPL
On 05/07/2014 01:35 PM, Tim Harvey wrote: On Wed, May 7, 2014 at 1:29 PM, York Sun york...@freescale.com wrote: On 05/07/2014 01:27 PM, Tim Harvey wrote: On Wed, May 7, 2014 at 9:14 AM, York Sun york...@freescale.com wrote: On 05/06/2014 04:35 PM, Tim Harvey wrote: On Tue, May 6, 2014 at 12:11 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote: Hello Tim, snip Since Crt0.S already created gd on the stack before calling board_init_f, can't the assignment of gd not simply be removed? Is there anything special about gdata? Regards, Jeroen Jeroen, That does make sense, but what I find is that York's ocmmit dec1861be90c948ea9fb771927d3d26a994d2e20 requires that gd be blanked and its not. This causes bus_i2c_init to skip its initialization because p-base is not zero. York, does this make sense? Your patch creates a dependence on gd-srdata being blank which isn't the case with the SRAM when booting from the IMX6 boot rom. GD should be cleared (zeroed). Then we don't have this problem. Whoever sets up gd (board_int_f, cpu_init_f, or others) should make sure gd is cleared. Why isn't it the case for IMX6 boot rom? York York, crt0.S is mapping gd to where the SPL stack pointer is defined, which is where Freescale says its stack pointer is for its firmware BOOT ROM, so its initial data will be dependent on what the BOOT ROM did. I think the right solution is to have crt0.S zero it out. Either crt0.S, or somewhere before gd is used for the first time. Can it be done in board_init_f()? York It makes more sense to do it in crt0.S so that all boards don't have to do it and can make the assumption that it is cleared. No objection as far as it is cleared. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] usb: ci_udc: allow multiple buffer allocs per ep
On Tuesday, May 06, 2014 at 01:48:11 AM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com Modify ci_ep_alloc_request() to return a dynamically allocated request object, rather than a singleton that's part of the endpoint. This requires moving various state from the endpoint structure to the request structure, since we need one copy per request. The fast bounce buffer b_fast is removed by this change rather than moved to the request object. Instead, we enhance the bounce buffer logic in ci_bounce()/ci_debounce() to keep the bounce buffer around between request submissions. This avoids the need to allocate an arbitrarily- sized bounce buffer up-front, yet avoids incurring the allocation overhead each time a request is submitted. A future enhancement would be to actually submit multiple requests to HW at once. The Linux driver shows that this is possible. That might improve throughput (depending on the USB protocol in use), since USB could be performing a transfer to one HW buffer in parallel with whatever SW actions U-Boot performs on another buffer. However, I have not made this change as part of this patch, in order to keep SW changes related to buffer management separate from any change in the way the HW is programmed. Applied, thanks Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-dfu
On Tuesday, May 06, 2014 at 11:29:32 AM, Lukasz Majewski wrote:
Hi Marek,
The following changes since commit
af41d6b4cb1602abebaaa9c8774a9b0ece564796:
common: fixed linker-list example (2014-05-05 10:24:13 +0200)
are available in the git repository at:
ssh://gu-...@git.denx.de/u-boot-dfu master
for you to fetch changes up to c805776ce7079c7b7dd54c644b499e1b8f6296b1:
ums: allow the user to specify the device type (2014-05-06 11:13:23
+0200)
Stephen Warren (9):
usb: ums: add error handling for failed registration
ums: support block devices not MMC devices
ums: remove UMS_{NUM,START}_SECTORS + UMS_START_SECTOR
ums: remove error-checking of MMC device size
ums: remove ums_disk_init()
ums: move IO support code to common location
ums: use get_device() not find_mmc_device();
ums: move all variable declarations to the start of the block
ums: allow the user to specify the device type
This doesn't match what's in U-Boot-dfu.git/master [1] it seems. Or does it ...
?
[1] http://git.denx.de/?p=u-boot/u-boot-dfu.git;a=summary
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 2/2] usb: ums: remove ci_udc special case
On Tuesday, May 06, 2014 at 01:48:12 AM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com Now that the ci_udc driver supports allocating multiple requests per endpoint, we can revert the special-case added by a022c1e13c01 usb: ums: use only 1 buffer for CI_UDC. Signed-off-by: Stephen Warren swar...@nvidia.com Applied, thanks Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v2 04/13] Makefile: Support include files for .dts files
Hi Stephen and Masahiro On 6 May 2014 20:15, Masahiro Yamada yamad...@jp.panasonic.com wrote: Hi Simon, Stephen, On Mon, 05 May 2014 10:54:52 -0600 Stephen Warren swar...@wwwdotorg.org wrote: On 05/05/2014 10:09 AM, Simon Glass wrote: Linux supports this, and if we are to have compatible device tree files, U-Boot should also. diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib # Modified for U-Boot dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \ -I$(srctree)/arch/$(ARCH)/dts \ +-I$(srctree)/include\ -undef -D__DTS__ I don't think we should add the top-level include/ directory to the DT include path. That is something I very specifically avoided in the kernel Makefiles. If we did allow this, then DTs could start including arbitrary U-Boot header files, rather than just header files intended to be used in DT bindings, and that would then make the DT files used in U-Boot not portable to the Linux kernel, or any standalone DT file repository which may appear. Instead, let's create a standalone root directory for the DT include files, and add that to the DT header path. We can add this DT-specific include path to the include patch for U-Boot C code if needed. Perhaps we can create a top-level dt/include/ or device-tree/include directory for this? I agree with Stephen. I hesitate to add the top-level include/ to the path. If we try to follow the Linux style, we can add the include path -I$(srctree)/arch/$(ARCH)/dts/include and create symbolic links to include/dt-bindings. Yes that's fine. So long as we can use include files it is OK with me. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] booting signed Images
Hi Heiko, On 7 May 2014 01:06, Heiko Schocher h...@denx.de wrote: Hello Simon, Am 05.05.2014 20:31, schrieb Simon Glass: Hi Wolfgang, On 5 May 2014 11:55, Wolfgang Denkw...@denx.de wrote: Dear Simon, In messageCAPnjgZ2-qC8YK8t2DvmzXWKy3Wd+=7VY1Ti=Jm 98lf96plf...@mail.gmail.com you wrote: Should we not prevent booting uImages or not signed FIT Images when CONFIG_FIT_SIGNATURE is defined? Or at least prevent booting such unsigned images through an U-Boot env variable. What Do you think? There is a 'required' property in the public keys which is intended to support this. If you mark a key as 'required then it will need to be verified by any image that is loaded. There is a test for this case, but it may not be comprehensive. But what about legacy uImage files? It appears nothing would stop booting one of those? That's right, there is nothing to stop that at present. The verification happens either on each image (for per-image signing) or on the selected configuration as a whole (in fit_image_load() when it sees the kernel being loaded). One simple solution might be to check a CONFIG option in boot_get_kernel() and disable support for IMAGE_FORMAT_LEGACY. The question is here, do we introduce a new config option for this, or do we use for example CONFIG_FIT_SIGNATURE to disable it? I prefer to check CONFIG_FIT_SIGNATURE, and disable IMAGE_FORMAT_LEGACY complete. I suggest a new CONFIG option, like CONFIG_DISABLE_IMAGE_FORMAT_LEGACY or possible a device tree option, since if you force disable of the legacy format you are actually removing functionality. At present CONFIG_FIT_SIGNATURE is a capability, and one capability should not normally preclude another. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] lib:crc32:hash: Allow setting of the initial crc32 value
Hi Lukasz, On 7 May 2014 06:57, Lukasz Majewski l.majew...@samsung.com wrote: The current approach set the initial value of crc32 calculation to zero, which is correct for calculating checksum of the whole chunk of data. It however, lacks the flexibility, when one wants to calculate CRC32 of a file comprised of many smaller parts received separately. In the proposed approach the output value is used as a starting condition for the proper crc32 calculation at crc32_wd function. This behavior is identical to the one provided by crc32() method implementation. Additionally comments were appropriately updated. Maybe I am missing something, but this doesn't seem necessary. In hash.h we have hash_init() hash_update() hash_finish() which permits you to pass more data through a hash function. Doesn't this already do what you want? What is missing is probably command-line access to this API. Something like: hash init envvar, algo hash update envvar, data, size hash finish envvar, [*]result or similar. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v2 05/13] tegra: dts: Bring in GPIO bindings from linux
Hi Stephen, On 5 May 2014 10:57, Stephen Warren swar...@wwwdotorg.org wrote: On 05/05/2014 10:09 AM, Simon Glass wrote: These files are taken from Linux 3.14. diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi This looks good. Can the patch be extended to all tegra*.dtsi too, so they are all consistent? Will do. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 4/5] samsung: misc: menu: increase delay in menu main loop
On 30/04/14 20:28, Przemyslaw Marczak wrote: Increase menu loop delay to 200 ms helps choose the right menu option by user. Before this, each time key was pressed the current menu option was changed few times. Now it changes only once and also changes few times if key is pressed for a longer time. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- Changes v2: - new commit Changes v3: - correct commit message Changes v4: - none Changes v5: - move mdelay() from check_keys() to menu loop - update commit msg --- board/samsung/common/misc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/5] samsung: misc: add gpt restore option to lcd menu
On 30/04/14 20:28, Przemyslaw Marczak wrote: This menu option allows restore gpt. This is usefull and no needs access to the u-boot console. For proper operation: - each partition uuid should be set in environment or - CONFIG_RANDOM_UUID should be defined for automatically uuid setting After operation success device is going to be reset. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- Changes v2: - commit separation Changes v3: - none Changes v4: - none Changes v5: - none --- board/samsung/common/misc.c | 3 +++ include/samsung/misc.h | 1 + 2 files changed, 4 insertions(+) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/5] samsung: misc: allows using environmental macros as args in menu commands
On 30/04/14 20:28, Przemyslaw Marczak wrote: Function cmd_process() runs commands with directly given list of arguments but it doesn't expand given environmental variables names as macros. Command gpt as one of arguments expects expanded macro e.g. $partitions so it needs to be called by function run_command(). Changes: - extend array mode_name by lower case commands names - used by find_cmd() - put each command arguments into one string - used by run_command() - use run_command() instead of cmd_process() Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- Changes v2: - new commit after separate previous commit Changes v3: - none Changes v4: - none Changes v5: - none --- board/samsung/common/misc.c | 49 - 1 file changed, 22 insertions(+), 27 deletions(-) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 5/5] samsung: misc: remove download mode info screen
On 30/04/14 20:28, Przemyslaw Marczak wrote: This change removes LCD menu download mode info screen. Now key press timeout is checked in function download_menu() and menu options are displayed directly after PWR + VOLUP keys. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- Changes v4: - new commit Changes v5: - none --- board/samsung/common/misc.c | 73 +++-- 1 file changed, 31 insertions(+), 42 deletions(-) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 3/5] samsung: misc: add env default option to lcd menu
On 30/04/14 20:28, Przemyslaw Marczak wrote: From: Inha Song ideal.s...@samsung.com This change allows reset device environment to default without using u-boot console, which is useful for system developers. Signed-off-by: Inha Song ideal.s...@samsung.com Acked-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- Changes v2: - extend commit message Changes v3: - none Changes v4: - none Changes v5: - none --- board/samsung/common/misc.c | 3 +++ include/samsung/misc.h | 1 + 2 files changed, 4 insertions(+) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/12] IMX: add additional function for pinmux using an array
On Wed, May 7, 2014 at 9:59 AM, Nikita Kiryanov nik...@compulab.co.il wrote: On 06/05/14 07:35, Tim Harvey wrote: On Tue, Apr 29, 2014 at 8:22 AM, Eric Nelson eric.nel...@boundarydevices.com wrote: snip The function name ..._array() also doesn't really capture what's going on here. Naming is hard though, and I'm not coming up with something else. Perhaps 'sparse', 'skip', or alternate? ya, I'm not sure anything else is more explanatory when we are doing something like this. Its bad enough that its likely difficult for someone to understand their first time through that we are doing this to eliminate multiple structs. Come to think of it, I don't think we need an _array() function at all. The list selection and stride size are IOMUX_PADS implementation details. It's not something we should expose to the function user. is_cpu_type() and ifdef(CONFIG_MX6QDL) can be used to decide the list and stride values inside imx_iomux_v3_setup_multiple_pads(), and then this function could be used for both single and multi cpu type situations. snip +/* macros for declaring and using pinmux array */ +#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) In a similar vein to my comment about Patch 8, I do wonder if a minor extension of this will allow use with a single-variant board though. for a single-variant one would just use the original IOMUX_PAD/imx_iomux_v3_setup_pad/imx_iomux_v3_setup_pad right? They can, but then we don't get to use the same code for both situations. If we define two versions of IOMUX_PADS: one for multi cpu type, and one for single cpu type, then the pinmux arrays for both situations will be syntactically similar. When combined with my other suggestion, it will be very easy to take a U-Boot configured for one CPU type, and reconfigure it to support both CPU types. Nikita, Excellent idea - I've merged that idea into my new patchset that I will post shortly. Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please fill the maintainer field of chromebook-x86
Hi Simon, The maintainer field of chromebook-x86 is blank. Active x86 x86corebootchromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x0111 - To make the maintainership clearer, could you add your name and email address to that field, please? Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [i2c] Pull request
Hello Tom, please pull from u-boot-i2c.git, thanks! The following changes since commit 173d294b94cfec10063a5be40934d6d8fb7981ce: Merge branch 'serial' of git://www.denx.de/git/u-boot-microblaze (2014-05-06 14:55:45 -0400) are available in the git repository at: git://git.denx.de/u-boot-i2c.git master for you to fetch changes up to 5146fc2b37a3098f0973b2f2339e069adfc7d272: i2c: zynq: Fixed compilation errors when using DEBUG (2014-05-08 07:03:37 +0200) Jesper B. Christensen (1): i2c: zynq: Fixed compilation errors when using DEBUG drivers/i2c/zynq_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 01/11] nand: remove CONFIG_SYS_NAND_PAGE_SIZE
We only need to read in the size of struct image_header and thus don't need to know the page size of the nand device. Cc: Scott Wood scottw...@freescale.com Signed-off-by: Tim Harvey thar...@gateworks.com Acked-by: Stefano Babic sba...@denx.de Acked-by: Scott Wood scottw...@freescale.com --- v3: - no changes v2: - cc Scott Wood scottw...@freescale.com on this - Acked-by: Stefano Babic sba...@denx.de - Acked-by: Scott Wood scottw...@freescale.com --- common/spl/spl_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9da0218..062461b 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -76,7 +76,7 @@ void spl_nand_load_image(void) #endif /* Load u-boot */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + sizeof(*header), (void *)header); spl_parse_image_header(header); nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, spl_image.size, (void *)spl_image.load_addr); -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 00/11] mx6: SPL NAND support
This series adds some necessary framework for IMX6 SPL support. The series includes support for NAND SPL and has been tested with MMC as well. I have tested this on five differing Ventana baseboards with a variety of memory (32bit 512MB, 32bit 1024MB, 64bit 1024MB) and CPU configurations (IMX6Q, IMX6DL, IMX6S). This is based on top of Mashahiro Yamada's patch that consolidates arch/arm/include/asm/arch-*/spl.h [1] v3: - re-ordered calls in board_init_f - replace imx_iomux_v3_setup_multiple_pads_array with additional intelligence in imx_iomux_v3_setup_multiple_pads - added ifdef's around cpu specific mmdc iocfg functions for code-reduction with single-variant board configs - added checks for IMX6D - added Freescale copyright to boot device support function - fixed typo s/IMX6SLD/IMX6SDL - encorporated cleanups in mxs_nand_spl.c per feedback v2: - use compatible linker script instead of creating new one - remove structure passing data from SPL to u-boot - remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base and nand_bbt to bring SPL down in size. This reduced codesize by about 32k where now mxs_spl_nand is about 12k total - adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD - move boot dev detection into imx-common/spl.c - move macros for using pinmux array into iomux-v3.h - remove missing/unnecessary include - revert mtdparts change - use get_ram_size() to detect memory - add support for MX6SOLO and MX6DUAL - set CS0_END for 4GB so get_ram_size() works - updated DDR3 calibration values for ventana boards - fixed build issue - only compile spl if doing spl build - fixed line length issue in README - remove CONFIG_SPL* conditions and conditionally compile instead - removed prints for CPU type and DRAM size/width - uboot will print these l - removed unused gw_ventana_spl.cfg - use common read_eeprom function - added MMC support to SPL - added Masahiro Yamada's boot mode consolidation patch http://patchwork.ozlabs.org/patch/341817 and rebase on top of it [1] http://patchwork.ozlabs.org/patch/341817/ Tim Harvey (11): SPL: NAND: remove CONFIG_SYS_NAND_PAGE_SIZE SPL: NAND: add support for mxs nand MX6: add common SPL configuration MX6: add boot device support for SPL IMX: add comments and remove unused struct fields MX6: add structs for mmdc and ddr iomux registers MX6: add mmdc configuration for MX6Q/MX6DL IMX: iomux: add macros to setup iomux for multiple SoC types IMX: ventana: split read_eeprom into standalone file IMX: ventana: auto-configure for IMX6Q vs IMX6DL IMX: ventana: switch to SPL arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/ddr.c| 473 ++ arch/arm/imx-common/Makefile| 1 + arch/arm/imx-common/cpu.c | 16 +- arch/arm/imx-common/iomux-v3.c | 16 +- arch/arm/imx-common/spl.c | 81 arch/arm/include/asm/arch-mx6/mx6-ddr.h | 231 +++ arch/arm/include/asm/imx-common/iomux-v3.h | 25 ++ board/gateworks/gw_ventana/Makefile | 3 +- board/gateworks/gw_ventana/README | 92 +++-- board/gateworks/gw_ventana/eeprom.c | 89 + board/gateworks/gw_ventana/gw_ventana.c | 591 +++- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 board/gateworks/gw_ventana/ventana_eeprom.h | 11 + boards.cfg | 6 +- common/spl/spl_nand.c | 2 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 231 +++ include/configs/gw_ventana.h| 11 + include/configs/imx6_spl.h | 71 21 files changed, 2047 insertions(+), 339 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c create mode 100644 arch/arm/imx-common/spl.c create mode 100644 board/gateworks/gw_ventana/eeprom.c create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c create mode 100644 drivers/mtd/nand/mxs_nand_spl.c create mode 100644 include/configs/imx6_spl.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 05/11] imx: add comments and remove unused struct fields
Add comment block for the imx_ddr_size function and remove the extra unused
fields from struct esd_mmdc_regs which are also not common between IMX53 and
IMX6.
Signed-off-by: Tim Harvey thar...@gateworks.com
Acked-by: Stefano Babic sba...@denx.de
---
v3:
- fixed doxygen-style comment block
- added Stefano's Ack
v2:
- new patch in series
---
arch/arm/imx-common/cpu.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index a77c4de..5a09107 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -58,6 +58,7 @@ char *get_reset_cause(void)
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};
+/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
uint32_tctl;
uint32_tpdc;
@@ -66,15 +67,6 @@ struct esd_mmdc_regs {
uint32_tcfg1;
uint32_tcfg2;
uint32_tmisc;
- uint32_tscr;
- uint32_tref;
- uint32_trsvd1;
- uint32_trsvd2;
- uint32_trwd;
- uint32_tor;
- uint32_tmrr;
- uint32_tcfg3lp;
- uint32_tmr4;
};
#define ESD_MMDC_CTL_GET_ROW(mdctl)((ctl 24) 7)
@@ -83,6 +75,12 @@ struct esd_mmdc_regs {
#define ESD_MMDC_CTL_GET_CS1(mdctl)((ctl 30) 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc 5) 1)
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
unsigned imx_ddr_size(void)
{
struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
--
1.8.3.2
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[U-Boot] [PATCH v3 04/11] mx6: add boot device support for SPL
Add a common spl.c file to support boot device functions needed for SPL
such as detecting the boot device.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- added Freescale copyright
v2:
- re-base on top of Masahiro Yamada's consolidation patch:
http://patchwork.ozlabs.org/patch/341817/
- moved spl_boot_device() and get_boot_mode() into own common imx spl.c file
- use mem-mapped structure for smbr reg access
---
arch/arm/imx-common/Makefile | 1 +
arch/arm/imx-common/spl.c| 81
2 files changed, 82 insertions(+)
create mode 100644 arch/arm/imx-common/spl.c
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index b04dfbb..c97ea48 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
+obj-$(CONFIG_SPL_BUILD)+= spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
new file mode 100644
index 000..9a02a64
--- /dev/null
+++ b/arch/arm/imx-common/spl.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/spl.h
+#include spl.h
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+u32 spl_boot_device(void)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(psrc-sbmr1);
+
+ /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+ switch ((reg 0x00FF) 4) {
+/* EIM: See 8.5.1, Table 8-9 */
+ case 0x0:
+ /* BOOT_CFG1[3]: NOR/OneNAND Selection */
+ if ((reg 0x0008) 3)
+ return BOOT_DEVICE_ONENAND;
+ else
+ return BOOT_DEVICE_NOR;
+ break;
+ /* SATA: See 8.5.4, Table 8-20 */
+ case 0x2:
+ return BOOT_DEVICE_SATA;
+ /* Serial ROM: See 8.5.5.1, Table 8-22 */
+ case 0x3:
+ /* BOOT_CFG4[2:0] */
+ switch ((reg 0x0700) 24) {
+ case 0x0 ... 0x4:
+ return BOOT_DEVICE_SPI;
+ case 0x5 ... 0x7:
+ return BOOT_DEVICE_I2C;
+ }
+ break;
+ /* SD/eSD: 8.5.3, Table 8-15 */
+ case 0x4:
+ case 0x5:
+ return BOOT_DEVICE_MMC1;
+ /* MMC/eMMC: 8.5.3 */
+ case 0x6:
+ case 0x7:
+ return BOOT_DEVICE_MMC1;
+ /* NAND Flash: 8.5.2 */
+ case 0x8 ... 0xf:
+ return BOOT_DEVICE_NAND;
+ }
+ return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ /* for MMC return either RAW or FAT mode */
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ break;
+ default:
+ puts(spl: ERROR: unsupported device\n);
+ hang();
+ }
+}
+#endif
--
1.8.3.2
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[U-Boot] [PATCH v3 02/11] spl: nand: add support for mxs nand
This utilizes existing mxs_nand support layer to provide a method to load an
image off nand for SPL. The flash device will be detected in order to support
multiple flash devices instead of having layout hard coded at build time.
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- removed NAND_NCE and NAND_CTRL_CHANGE unused by mxc_nand.c
- return specific error types on errors
- remove register keyword - let compiler do optimizations
v2:
- remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base
and nand_bbt to bring SPL down in size. This reduced codesize by about 32k
where now mxs_spl_nand is about 12k total.
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/mxs_nand_spl.c | 231
2 files changed, 232 insertions(+)
create mode 100644 drivers/mtd/nand/mxs_nand_spl.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 02b149c..de5b461 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -65,5 +65,6 @@ else # minimal SPL drivers
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
+obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
endif # drivers
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
new file mode 100644
index 000..78ca32c
--- /dev/null
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include nand.h
+#include malloc.h
+
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
+int column, int page_addr)
+{
+ register struct nand_chip *chip = mtd-priv;
+ u32 timeo, time_start;
+
+ /* write out the command to the device */
+ chip-cmd_ctrl(mtd, command, NAND_CLE);
+
+ /* Serially input address */
+ if (column != -1) {
+ chip-cmd_ctrl(mtd, column, NAND_ALE);
+ chip-cmd_ctrl(mtd, column 8, NAND_ALE);
+ }
+ if (page_addr != -1) {
+ chip-cmd_ctrl(mtd, page_addr, NAND_ALE);
+ chip-cmd_ctrl(mtd, page_addr 8, NAND_ALE);
+ /* One more address cycle for devices 128MiB */
+ if (chip-chipsize (128 20))
+ chip-cmd_ctrl(mtd, page_addr 16, NAND_ALE);
+ }
+ chip-cmd_ctrl(mtd, NAND_CMD_NONE, 0);
+
+ if (command == NAND_CMD_READ0) {
+ chip-cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE);
+ chip-cmd_ctrl(mtd, NAND_CMD_NONE, 0);
+ }
+
+ /* wait for nand ready */
+ ndelay(100);
+ timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ time_start = get_timer(0);
+ while (get_timer(time_start) timeo) {
+ if (chip-dev_ready(mtd))
+ break;
+ }
+}
+
+static int mxs_flash_ident(struct mtd_info *mtd)
+{
+ register struct nand_chip *chip = mtd-priv;
+ int i;
+ u8 mfg_id, dev_id;
+ u8 id_data[8];
+ struct nand_onfi_params *p = chip-onfi_params;
+
+ /* Reset the chip */
+ chip-cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+ /* Send the command for reading device ID */
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+ /* Read manufacturer and device IDs */
+ mfg_id = chip-read_byte(mtd);
+ dev_id = chip-read_byte(mtd);
+
+ /* Try again to make sure */
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+ for (i = 0; i 8; i++)
+ id_data[i] = chip-read_byte(mtd);
+ if (id_data[0] != mfg_id || id_data[1] != dev_id) {
+ printf(second ID read did not match);
+ return -1;
+ }
+ debug(0x%02x:0x%02x , mfg_id, dev_id);
+
+ /* read ONFI */
+ chip-onfi_version = 0;
+ chip-cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+ if (chip-read_byte(mtd) != 'O' || chip-read_byte(mtd) != 'N' ||
+ chip-read_byte(mtd) != 'F' || chip-read_byte(mtd) != 'I') {
+ return -2;
+ }
+
+ /* we have ONFI, probe it */
+ chip-cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+ chip-read_buf(mtd, (uint8_t *)p, sizeof(*p));
+ mtd-name = p-model;
+ mtd-writesize = le32_to_cpu(p-byte_per_page);
+ mtd-erasesize = le32_to_cpu(p-pages_per_block) * mtd-writesize;
+ mtd-oobsize = le16_to_cpu(p-spare_bytes_per_page);
+ chip-chipsize = le32_to_cpu(p-blocks_per_lun);
+ chip-chipsize *= (uint64_t)mtd-erasesize * p-lun_count;
+ /* Calculate the address shift from the page size */
+ chip-page_shift = ffs(mtd-writesize) - 1;
+ chip-phys_erase_shift = ffs(mtd-erasesize) - 1;
+ /* Convert chipsize to number of pages
[U-Boot] [PATCH v3 03/11] mx6: add common SPL configuration
Add a common header which can hopefully be shared amon imx6 SPL users Signed-off-by: Tim Harvey thar...@gateworks.com Acked-by: Stefano Babic sba...@denx.de Acked-by: Nikita Kiryanov nik...@compulab.co.il --- v3: - fixed typo s/IMX6SLD/IMX6SDL - add acks from Stefano and Nikita v2: - adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD --- include/configs/imx6_spl.h | 71 ++ 1 file changed, 71 insertions(+) create mode 100644 include/configs/imx6_spl.h diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h new file mode 100644 index 000..6fdc438 --- /dev/null +++ b/include/configs/imx6_spl.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey thar...@gateworks.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __IMX6_SPL_CONFIG_H +#define __IMX6_SPL_CONFIG_H + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_FRAMEWORK + +/* + * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: + * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091 + * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well + * - BOOT ROM stack is at 0x0091FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + *IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to + *fit between 0x00907000 and 0x00918000. + * - Additionally the BOOT ROM loads what they consider the firmware image + *which consists of a 4K header in front of us that contains the IVT, DCD + *and some padding thus 'our' max size is really 0x00908000 - 0x00918000 + *or 64KB + */ +#define CONFIG_SPL_LDSCRIPTarch/arm/cpu/armv7/omap-common/u-boot-spl.lds +#define CONFIG_SPL_TEXT_BASE 0x00908000 +#define CONFIG_SPL_MAX_SIZE(64 * 1024) +#define CONFIG_SPL_START_S_PATHarch/arm/cpu/armv7 +#define CONFIG_SPL_STACK 0x0091FFB8 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* NAND support */ +#if defined(CONFIG_SPL_NAND_SUPPORT) +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_DMA_SUPPORT +#endif + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR138 /* offset 69KB */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) +#endif + +/* SATA support */ +#if defined(CONFIG_SPL_SATA_SUPPORT) +#define CONFIG_SPL_SATA_BOOT_DEVICE0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME u-boot.img +#define CONFIG_SPL_LIBDISK_SUPPORT +#endif + +#define CONFIG_SPL_BSS_START_ADDR 0x1820 +#define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START0x1830 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB */ +#define CONFIG_SYS_TEXT_BASE 0x1780 +#endif + +#endif -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 06/11] mx6: add structs for mmdc and ddr iomux registers
Add memory-mapped structures for MMDC iomux and configuration. Note that
the MMDC configuration registers are common between the IMX6DQ
(IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) the iomux
register addresses differ. This requires two sets of structures.
Add structures to describe DDR3 device information, system information
(memory layout, etc), and MMDC calibration regitsers that can be used to
configure the MMDC dynamically.
We define these structures for SPL builds instead of including mx6q-ddr.h an
mx6dl-ddr.h which use the same namespace and are only useful for imximage cf
files.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- moved portions into following patch
v2:
- split out from original mmdc configuration patch
- only define for SPL build
- do not include mx6q-ddr.h and mx6dl-ddr.h for SPL build - these use the
same namespace and are only useful for imximage cfg files
---
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 159
1 file changed, 159 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 43d377a..c2a31d2 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_MX6Q
#include mx6q-ddr.h
#else
@@ -15,6 +16,164 @@
#error Please select cpu
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
+#else
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdscr;
+ u32 mdref;
+ u32 res1[2];
+ u32 mdrwd;
+ u32 mdor;
+ u32 res2[3];
+ u32 mdasp;
+ u32 res3[240];
+ u32 mapsr;
+ u32 res4[254];
+ u32 mpzqhwctrl;
+ u32 res5[2];
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+ u32 res6;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+ u32 res7[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+ u32 res8;
+ u32 mprddlctl;
+ u32 res9;
+ u32 mpwrdlctl;
+ u32 res10[25];
+ u32 mpmur0;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE 0x020e0500
+struct mx6dq_iomux_ddr_regs {
+ u32 res1[3];
+ u32 dram_sdqs5;
+ u32 dram_dqm5;
+ u32 dram_dqm4;
+ u32 dram_sdqs4;
+ u32 dram_sdqs3;
+ u32 dram_dqm3;
+ u32 dram_sdqs2;
+ u32 dram_dqm2;
+ u32 res2[16];
+ u32 dram_cas;
+ u32 res3[2];
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res4[2];
+ u32 dram_sdclk_0;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdclk_1;
+ u32 dram_sdcke1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 res5;
+ u32 dram_sdqs0;
+ u32 dram_dqm0;
+ u32 dram_sdqs1;
+ u32 dram_dqm1;
+ u32 dram_sdqs6;
+ u32 dram_dqm6;
+ u32 dram_sdqs7;
+ u32 dram_dqm7;
+};
+
+#define MX6DQ_IOM_GRP_BASE 0x020e0700
+struct mx6dq_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 res2;
+ u32 grp_ddrpke;
+ u32 res3[6];
+ u32 grp_ddrmode;
+ u32 res4[3];
+ u32 grp_b0ds;
+ u32 grp_b1ds;
+ u32 grp_ctlds;
+ u32 res5;
+ u32 grp_b2ds;
+ u32 grp_ddr_type;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 grp_b6ds;
+};
+
+#define MX6SDL_IOM_DDR_BASE 0x020e0400
+struct mx6sdl_iomux_ddr_regs {
+ u32 res1[25];
+ u32 dram_cas;
+ u32 res2[2];
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_dqm2;
+ u32 dram_dqm3;
+ u32 dram_dqm4;
+ u32 dram_dqm5;
+ u32 dram_dqm6;
+ u32 dram_dqm7;
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res3[2];
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_sdclk_1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_sdqs2;
+ u32 dram_sdqs3;
+ u32 dram_sdqs4;
+ u32 dram_sdqs5;
+ u32 dram_sdqs6;
+ u32 dram_sdqs7;
+};
+
+#define MX6SDL_IOM_GRP_BASE 0x020e0700
+struct mx6sdl_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 grp_ddrpke;
+ u32 res2[2];
+ u32 grp_ddrmode;
+ u32 grp_b0ds;
+ u32 res3;
+ u32 grp_ctlds;
+ u32 grp_b1ds;
+ u32 grp_ddr_type;
+ u32 grp_b2ds;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 res4;
+ u32
[U-Boot] [PATCH v3 07/11] mx6: add mmdc configuration for MX6Q/MX6DL
Add functions for configuring iomux based on board-specific regs and
for configuring mmdc based on board-specific and chip-specific data.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- added ifdef's around cpu specific iocfg functions for code-reduction with
single-variant board configs
- moved portions from previous patch here
- added check for IMX6D
v2:
- split out mmdc and iomux structs into separate patch
---
arch/arm/cpu/armv7/mx6/Makefile | 1 +
arch/arm/cpu/armv7/mx6/ddr.c| 473
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 72 +
3 files changed, 546 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index d7285fc..6dc9f8e 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -8,4 +8,5 @@
#
obj-y := soc.o clock.o
+obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT)+= hab.o
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
new file mode 100644
index 000..e64fa91
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -0,0 +1,473 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/types.h
+#include asm/arch/mx6-ddr.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+#include asm/types.h
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+/* Configure MX6DQ mmdc iomux */
+void mx6dq_dram_iocfg(unsigned width,
+ const struct mx6dq_iomux_ddr_regs *ddr,
+ const struct mx6dq_iomux_grp_regs *grp)
+{
+ volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
+
+ /* DDR IO Type */
+ mx6_grp_iomux-grp_ddr_type = grp-grp_ddr_type;
+ mx6_grp_iomux-grp_ddrpke = grp-grp_ddrpke;
+
+ /* Clock */
+ mx6_ddr_iomux-dram_sdclk_0 = ddr-dram_sdclk_0;
+ mx6_ddr_iomux-dram_sdclk_1 = ddr-dram_sdclk_1;
+
+ /* Address */
+ mx6_ddr_iomux-dram_cas = ddr-dram_cas;
+ mx6_ddr_iomux-dram_ras = ddr-dram_ras;
+ mx6_grp_iomux-grp_addds = grp-grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux-dram_reset = ddr-dram_reset;
+ mx6_ddr_iomux-dram_sdcke0 = ddr-dram_sdcke0;
+ mx6_ddr_iomux-dram_sdcke1 = ddr-dram_sdcke1;
+ mx6_ddr_iomux-dram_sdba2 = ddr-dram_sdba2;
+ mx6_ddr_iomux-dram_sdodt0 = ddr-dram_sdodt0;
+ mx6_ddr_iomux-dram_sdodt1 = ddr-dram_sdodt1;
+ mx6_grp_iomux-grp_ctlds = grp-grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux-grp_ddrmode_ctl = grp-grp_ddrmode_ctl;
+ mx6_ddr_iomux-dram_sdqs0 = ddr-dram_sdqs0;
+ mx6_ddr_iomux-dram_sdqs1 = ddr-dram_sdqs1;
+ if (width = 32) {
+ mx6_ddr_iomux-dram_sdqs2 = ddr-dram_sdqs2;
+ mx6_ddr_iomux-dram_sdqs3 = ddr-dram_sdqs3;
+ }
+ if (width = 64) {
+ mx6_ddr_iomux-dram_sdqs4 = ddr-dram_sdqs4;
+ mx6_ddr_iomux-dram_sdqs5 = ddr-dram_sdqs5;
+ mx6_ddr_iomux-dram_sdqs6 = ddr-dram_sdqs6;
+ mx6_ddr_iomux-dram_sdqs7 = ddr-dram_sdqs7;
+ }
+
+ /* Data */
+ mx6_grp_iomux-grp_ddrmode = grp-grp_ddrmode;
+ mx6_grp_iomux-grp_b0ds = grp-grp_b0ds;
+ mx6_grp_iomux-grp_b1ds = grp-grp_b1ds;
+ if (width = 32) {
+ mx6_grp_iomux-grp_b2ds = grp-grp_b2ds;
+ mx6_grp_iomux-grp_b3ds = grp-grp_b3ds;
+ }
+ if (width = 64) {
+ mx6_grp_iomux-grp_b4ds = grp-grp_b4ds;
+ mx6_grp_iomux-grp_b5ds = grp-grp_b5ds;
+ mx6_grp_iomux-grp_b6ds = grp-grp_b6ds;
+ mx6_grp_iomux-grp_b7ds = grp-grp_b7ds;
+ }
+ mx6_ddr_iomux-dram_dqm0 = ddr-dram_dqm0;
+ mx6_ddr_iomux-dram_dqm1 = ddr-dram_dqm1;
+ if (width = 32) {
+ mx6_ddr_iomux-dram_dqm2 = ddr-dram_dqm2;
+ mx6_ddr_iomux-dram_dqm3 = ddr-dram_dqm3;
+ }
+ if (width = 64) {
+ mx6_ddr_iomux-dram_dqm4 = ddr-dram_dqm4;
+ mx6_ddr_iomux-dram_dqm5 = ddr-dram_dqm5;
+ mx6_ddr_iomux-dram_dqm6 = ddr-dram_dqm6;
+ mx6_ddr_iomux-dram_dqm7 = ddr-dram_dqm7;
+ }
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+/* Configure MX6SDL mmdc iomux */
+void mx6sdl_dram_iocfg(unsigned width,
+ const struct mx6sdl_iomux_ddr_regs *ddr,
+ const struct mx6sdl_iomux_grp_regs *grp)
+{
+ volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
+
+
[U-Boot] [PATCH v3 11/11] imx: ventana: switch to SPL
Switch to an SPL image. The SPL for Ventana does the following: - setup i2c and read the factory programmed EEPROM to obtain DRAM config and model for board-specific calibration data - configure DRAM per CPU/size/layout/devices/calibration - load u-boot.img from NAND and jump to it This allows for a single SPL+u-boot.img to replace the previous multiple boa configurations. Signed-off-by: Tim Harvey thar...@gateworks.com --- v3: - re-ordered calls in board_init_f v2: - remove missing/unnecessary include - revert mtdparts change - use imx_ddr_size() which uses MMDC configuration to determine mem size explicitly - add support for MX6SOLO and MX6DUAL - set CS0_END for 4GB so get_ram_size() works - updated DDR3 calibration values for ventana boards - fixed build issue - only compile spl if doing spl build - fixed line length issue in README - remove CONFIG_SPL* conditions and conditionally compile instead - removed prints for CPU type and DRAM size/width - uboot will print these later - removed unused gw_ventana_spl.cfg - use common read_eeprom function - added MMC support to SPL --- board/gateworks/gw_ventana/Makefile | 1 + board/gateworks/gw_ventana/README | 92 +++--- board/gateworks/gw_ventana/gw_ventana.c | 10 +- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 boards.cfg | 6 +- include/configs/gw_ventana.h| 11 + 7 files changed, 498 insertions(+), 56 deletions(-) create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index 03bd1fd..33a1788 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -7,4 +7,5 @@ # obj-y := gw_ventana.o gsc.o eeprom.o +obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README index 9e697d6..888657c 100644 --- a/board/gateworks/gw_ventana/README +++ b/board/gateworks/gw_ventana/README @@ -3,53 +3,81 @@ U-Boot for the Gateworks Ventana Product Family boards This file contains information for the port of U-Boot to the Gateworks Ventana Product family boards. -1. Boot source, boot from NAND +1. Secondary Program Loader (SPL) +- + +The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading +an executable image from various boot devices. + +The Gateworks Ventana board config uses an SPL build configuration. This +will build the following artifacts from u-boot source: + - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program + Loader) boots. This detects CPU/DRAM configuration, configures + The DRAM controller, loads u-boot.img from the detected boot device, + and jumps to it. As this is booted from the PPL, it has an IVT/DCD + table. + - u-boot.img - The main u-boot core which is u-boot.bin with a image header. + + +2. Build + + +To build U-Boot for the Gateworks Ventana product family: + + make gwventana_config + make + + +3. Boot source, boot from NAND -- The i.MX6 BOOT ROM expects some structures that provide details of NAND layout and bad block information (referred to as 'bootstreams') which are replicated -multiple times in NAND. The number of replications is configurable through -board strapping options and eFUSE settings. The Freescale 'kobs-ng' -application from the Freescale LTIB BSP, which runs under Linux, must be used -to program the bootstream in order to setup the replicated headers correctly. +multiple times in NAND. The number of replications and their spacing (referred +to as search stride) is configurable through board strapping options and/or +eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In +addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two +copies of a bootloader in flash in the case that a bad block has corrupted one. +The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs +under Linux and operates on an MTD partition, must be used to program the +bootstream in order to setup this flash structure correctly. The Gateworks Ventana boards with NAND flash have been factory programmed such that their eFUSE settings expect 2 copies of the boostream (this is specified by providing kobs-ng with the --search_exponent=1 argument). Once in -Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream +Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL with: -kobs-ng init -v -x --search_exponent=1 u-boot.imx +kobs-ng init -v -x --search_exponent=1 SPL -The kobs-ng application uses an imximage (u-boot.imx) which contains the -Image Vector Table (IVT) and Device Configuration Data (DCD) structures that -the i.MX6
[U-Boot] [PATCH v3 09/11] imx: ventana: split read_eeprom into standalone file
Split the read_eeprom function out so that it can be shared (ie with SPL)
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- no changes
v2:
- new patch in series
---
board/gateworks/gw_ventana/Makefile | 2 +-
board/gateworks/gw_ventana/eeprom.c | 89 +
board/gateworks/gw_ventana/gw_ventana.c | 89 +
board/gateworks/gw_ventana/ventana_eeprom.h | 11
4 files changed, 102 insertions(+), 89 deletions(-)
create mode 100644 board/gateworks/gw_ventana/eeprom.c
diff --git a/board/gateworks/gw_ventana/Makefile
b/board/gateworks/gw_ventana/Makefile
index e8dab89..03bd1fd 100644
--- a/board/gateworks/gw_ventana/Makefile
+++ b/board/gateworks/gw_ventana/Makefile
@@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := gw_ventana.o gsc.o
+obj-y := gw_ventana.o gsc.o eeprom.o
diff --git a/board/gateworks/gw_ventana/eeprom.c
b/board/gateworks/gw_ventana/eeprom.c
new file mode 100644
index 000..e90186e
--- /dev/null
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey thar...@gateworks.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+
+#include gsc.h
+#include ventana_eeprom.h
+
+/* read ventana EEPROM, check for validity, and return baseboard type */
+int
+read_eeprom(int bus, struct ventana_board_info *info)
+{
+ int i;
+ int chksum;
+ char baseboard;
+ int type;
+ unsigned char *buf = (unsigned char *)info;
+
+ memset(info, 0, sizeof(*info));
+
+ /*
+* On a board with a missing/depleted backup battery for GSC, the
+* board may be ready to probe the GSC before its firmware is
+* running. We will wait here indefinately for the GSC/EEPROM.
+*/
+ while (1) {
+ if (0 == i2c_set_bus_num(bus)
+ 0 == i2c_probe(GSC_EEPROM_ADDR))
+ break;
+ mdelay(1);
+ }
+
+ /* read eeprom config section */
+ if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
+ puts(EEPROM: Failed to read EEPROM\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* sanity checks */
+ if (info-model[0] != 'G' || info-model[1] != 'W') {
+ puts(EEPROM: Invalid Model in EEPROM\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* validate checksum */
+ for (chksum = 0, i = 0; i sizeof(*info)-2; i++)
+ chksum += buf[i];
+ if ((info-chksum[0] != chksum8) ||
+ (info-chksum[1] != (chksum0xff))) {
+ puts(EEPROM: Failed EEPROM checksum\n);
+ info-model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* original GW5400-A prototype */
+ baseboard = info-model[3];
+ if (strncasecmp((const char *)info-model, GW5400-A, 8) == 0)
+ baseboard = '0';
+
+ switch (baseboard) {
+ case '0': /* original GW5400-A prototype */
+ type = GW54proto;
+ break;
+ case '1':
+ type = GW51xx;
+ break;
+ case '2':
+ type = GW52xx;
+ break;
+ case '3':
+ type = GW53xx;
+ break;
+ case '4':
+ type = GW54xx;
+ break;
+ default:
+ printf(EEPROM: Unknown model in EEPROM: %s\n, info-model);
+ type = GW_UNKNOWN;
+ break;
+ }
+ return type;
+}
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 2113740..3b6bc01 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -81,15 +81,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static struct ventana_board_info ventana_info;
-enum {
- GW54proto, /* original GW5400-A prototype */
- GW51xx,
- GW52xx,
- GW53xx,
- GW54xx,
- GW_UNKNOWN,
-};
-
int board_type;
/* UART1: Function varies per baseboard */
@@ -368,84 +359,6 @@ int board_eth_init(bd_t *bis)
return 0;
}
-/* read ventana EEPROM, check for validity, and return baseboard type */
-static int
-read_eeprom(void)
-{
- int i;
- int chksum;
- char baseboard;
- int type;
- struct ventana_board_info *info = ventana_info;
- unsigned char *buf = (unsigned char *)ventana_info;
-
- memset(info, 0, sizeof(ventana_info));
-
- /*
-* On a board with a missing/depleted backup battery for GSC, the
-* board may be ready to probe the GSC before its firmware is
-* running. We will wait here indefinately for the GSC/EEPROM.
-*/
- while (1) {
- if (0 == i2c_set_bus_num(I2C_GSC)
- 0 == i2c_probe(GSC_EEPROM_ADDR))
[U-Boot] [PATCH v3 08/11] imx: iomux: add macros to setup iomux for multiple SoC types
Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list
and add macros for declaring the pad_list that take into account the
SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL
iomux).
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- remove commit msg 2nd paragrap about prior approaches
- re-work to avoid needing to add a new function by making
imx_iomux_v3_setup_multiple_pads more intelligent and adding macros
that depend on SoC type support
v2:
- moved macros for declaring and using structs for array variant
- removed non-related whitespace cleanup
---
arch/arm/imx-common/iomux-v3.c | 16 ++--
arch/arm/include/asm/imx-common/iomux-v3.h | 25 +
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b59b802..9bd8dfb 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -11,6 +11,7 @@
#include common.h
#include asm/io.h
#include asm/arch/imx-regs.h
+#include asm/arch/sys_proto.h
#include asm/imx-common/iomux-v3.h
static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -46,12 +47,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
#endif
}
+/* configures a list of pads within declared with IOMUX_PADS macro */
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count)
{
iomux_v3_cfg_t const *p = pad_list;
+ int stride;
int i;
- for (i = 0; i count; i++)
- imx_iomux_v3_setup_pad(*p++);
+#if defined(CONFIG_MX6QDL)
+ stride = 2;
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ p += 1;
+#else
+ stride = 1;
+#endif
+ for (i = 0; i count; i++) {
+ imx_iomux_v3_setup_pad(*p);
+ p += stride;
+ }
}
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
b/arch/arm/include/asm/imx-common/iomux-v3.h
index dec11a1..3b0759a 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -170,4 +170,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def);\
+}
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x)\
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
#endif /* __MACH_IOMUX_V3_H__*/
--
1.8.3.2
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[U-Boot] [PATCH v3 10/11] imx: ventana: auto-configure for IMX6Q vs IMX6DL
use the new iomux function and a macros to create a multi-dimensional array
of iomux values without duplicating the defintions.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v3:
- replace use of imx_iomux_v3_setup_multiple_pads_array with
imx_iomux_v3_setup_multiple_pads
v2:
- use macros that have been moved to iomux-v3.h
---
board/gateworks/gw_ventana/gw_ventana.c | 492
1 file changed, 310 insertions(+), 182 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 3b6bc01..4ae458f 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -85,109 +85,149 @@ int board_type;
/* UART1: Function varies per baseboard */
iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
/* UART2: Serial Console */
iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1: GSC */
-struct i2c_pads_info i2c_pad_info0 = {
+struct i2c_pads_info mx6q_i2c_pad_info0 = {
.scl = {
- .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
- .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
-struct i2c_pads_info i2c_pad_info1 = {
+struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
/* I2C3: Misc/Expansion */
-struct i2c_pads_info i2c_pad_info2 = {
+struct i2c_pads_info mx6q_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info2 = {
.scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
[U-Boot] [PATCH v2] dwc_ahsata: return failure for MX6 if not IMX6Q/IMX6D
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure
instead of attempting a memory access that results in a data abort and reset.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v2:
- remove print as this condition isn't really an error just something not
possible
---
drivers/block/dwc_ahsata.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 3569214..15d65d7 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -17,6 +17,7 @@
#include asm/io.h
#include linux/bitops.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
#include dwc_ahsata.h
struct sata_port_regs {
@@ -558,6 +559,10 @@ int init_sata(int dev)
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
+#if defined(CONFIG_MX6)
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+#endif
if (dev 0 || dev (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf(The sata index %d is out of ranges\n\r, dev);
return -1;
--
1.8.3.2
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[U-Boot] [PATCH] imx: sata: return failure if not IMX6Q/IMX6D
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return
instead of configuring the SATA clock and GPR13 registers.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
arch/arm/imx-common/sata.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index 2e69486..c10dd28 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -8,13 +8,18 @@
#include asm/arch/iomux.h
#include asm/io.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ int ret;
- int ret = enable_sata_clock();
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+
+ ret = enable_sata_clock();
if (ret)
return ret;
--
1.8.3.2
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