Re: [U-Boot] [RFC PATCH 1/7] Allow checking in multiple partitions for scan_dev_for_boot.

[Vagrant Cascadian]

Thanks for the review!

On 2014-10-06, Stephen Warren swar...@nvidia.com wrote:
 On 10/03/2014 03:08 PM, Vagrant Cascadian wrote:

 Some standalone description of this change, and justification for it,
 should really be present in the commit message. Patch 0/7 doesn't get
 applied anywhere.

Of course; that was a consequence of learning how patman/git-send-email
work... trial by fire... I'll use more verbose commit messages in the
future.


 diff --git a/include/config_distro_bootcmd.h 
 b/include/config_distro_bootcmd.h

 -bootpart=1\0 \
 +boot_partitions=1\0 \

 Instead of searching a hard-coded list of partitions, I think it'd be
 better to have the script automatically determine which partition to
 boot from based on the partition tables' bootable flag or partition
 type. I had always intended these scripts to do that, but never got
 around to doing it. I think the $dev:$part syntax already chooses the
 first partition marked bootable if you don't specify a partition. Would
 that work?

I suspect that might work. I merely went with the simplest approach to
extend what was already there, by supporting an arbitrary number of
partitions to search, and leaving the defaults as is.

The BeagleBone Black board ships with various boot files on the first
FAT partition, but newer images available for it moved boot files
(kernel/initrd/dtb/uEnv.txt) onto the second (ext4?) partition, as the
FAT partition is exported as a multifunction device over USB... So
ideally u-boot could support multiple partitions to search, to support
multiple generations of images without having to manually configure
u-boot.


live well,
  vagrant


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Re: [U-Boot] [RFC PATCH 6/7] Add support for loading environment from uEnv.txt in config_distro_bootcmd.

[Vagrant Cascadian]

On 2014-10-06, Stephen Warren wrote:
 On 10/03/2014 03:08 PM, Vagrant Cascadian wrote:

 diff --git a/include/config_distro_bootcmd.h 
 b/include/config_distro_bootcmd.h

  for prefix in ${boot_prefixes}; do  \
  run scan_dev_for_extlinux;  \
  run scan_dev_for_scripts;   \
 +run scan_dev_for_uenv_files;\
  done;   \

 I've always thought of uEnv.txt being stored in a single hard-coded
 location, and used to set e.g. $boot_targets to influence which
 locations get searched for boot files. However, this patch appears to
 use it to house actual boot command sequences.

I took the behavior of the am335x_evm.h based boards and tryed to
generalize it. If that's not desired, then allowing for some hook to
maintain backwards compatibility for those boards would be nice to make
it feasible for boards to migrate to config_distro_bootcmd without
breaking backwards compatibility.


 In other words, I intended:

 * (Optionally, and preferably via CONFIG_PREBOOT) load uEnv.txt from a
 hard-coded location.
 * Search a list of locations for boot files, of type extlinux.conf (or
 for legacy reasons, boot .scr)

 However, this patch now allows:

 * Search a list of locations for boot files, of type extlinux.conf, or
 for legacy reasons, boot .scr, or uEnv.txt

 I don't think that's something we should encourage in
 config_distro_bootcmd.h; the entire point of this header file is to
 define a single way (extlinux.conf) for distros to define the available
 boot options. Yes unfortunately we have boot.scr too as a legacy option,
 but perhaps someday we can drop that. If we grow more options (allowing
 boot scripts in uEnv.txt) that removes the standardization.

Sure.


 If we absolutely have to support uEnv.txt for legacy reasons on some
 platforms, we should at least make it optional so that we don't add
 support for it to all the other platforms that don't want to pick up
 legacy stuff. Perhaps we should run scan_dev_hook and allow boards to
 define arbitrary stuff there, so there's no mention at all of uEnv.txt
 in config_distro_bootcmd.h.

Sounds reasonable. It might be desireable to have multiple hook
locations, to be able to run before or after various points. Some of the
other patches in this series implement generic hooks to be run as part
of bootcmd. Obviously, there's a balance to be struck not putting too
many hooks in.

Thanks for the review and comments!


live well,
  vagrant


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[U-Boot] [PATCH 4/9] mmc: sunxi: Add support for sun8i (A23)

[Chen-Yu Tsai]

The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.

Re-use code added for sun6i.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 arch/arm/include/asm/arch-sunxi/mmc.h | 2 +-
 drivers/mmc/sunxi_mmc.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h 
b/arch/arm/include/asm/arch-sunxi/mmc.h
index 6a31184..5836ae9 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,7 @@ struct sunxi_mmc {
u32 chda;   /* 0x90 */
u32 cbda;   /* 0x94 */
u32 res1[26];
-#if defined(CONFIG_SUN6I)
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
u32 res2[64];
 #endif
u32 fifo;   /* 0x100 (0x200 on sun6i) FIFO access address */
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 8f4b50b..23a2ec0 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -73,7 +73,7 @@ static int mmc_clk_io_on(int sdc_no)
/* config ahb clock */
setbits_le32(ccm-ahb_gate0, 1  AHB_GATE_OFFSET_MMC(sdc_no));
 
-#if defined(CONFIG_SUN6I)
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
/* unassert reset */
setbits_le32(ccm-ahb_reset0_cfg, 1  AHB_RESET_OFFSET_MMC(sdc_no));
 #endif
-- 
2.1.1

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[U-Boot] [PATCH 0/9] ARM: sunxi: Add Allwinner A23 (sun8i) support

[Chen-Yu Tsai]

Hi everyone,

This series adds support for Allwinner's A23 SoC. All the patches
are either direct cherry-picks or changes manually merged from
u-boot-sunxi.

Patch 1 fixes build breaks when CONFIG_MMC is not set. This happens
when we use port F for uart0.

Patch 2 adds uart0 pinmux values for A23.

Patch 3 adds support for using uart0 on port F, either using a breakout
board or soldering wires to exposed pads. At least one version of A23
tablets requires this, as no other uarts are exposed.

Patch 4 adds support for sun8i in the mmc driver. This is the same as
sun6i.

Patch 5 adds machine support for sun8i.

Patch 6 adds support for gpio banks L and beyond, which is used by
r_uart, p2wi (on sun6i) and rsb (on sun8i).

Patch 7 makes the prcm apb0 clock enabling function to take an argument
for which modules should be enabled.

Patch 8 adds support for using r_uart as a console (with CONS_INDEX=5).

Patch 9 adds a defconfig for the Ippo Q8H A23 tablet board.


Cheers
ChenYu

Chen-Yu Tsai (8):
  ARM: sunxi: Fix build break when CONFIG_MMC is not defined
  ARM: sunxi: Add sun8i (A23) UART0 pin mux support
  ARM: sunxi: Add support for uart0 on port F (mmc0)
  mmc: sunxi: Add support for sun8i (A23)
  ARM: sunxi: Add basic A23 support
  ARM: sunxi: Allow specifying module in prcm apb0 init function
  ARM: sunxi: Add support for using R_UART as console
  ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfig

Hans de Goede (1):
  ARM: sunxi: Add support for R_PIO gpio banks

 arch/arm/Kconfig|  3 +++
 arch/arm/cpu/armv7/sunxi/Makefile   |  2 ++
 arch/arm/cpu/armv7/sunxi/board.c| 18 +++--
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c  |  6 ++
 arch/arm/cpu/armv7/sunxi/cpu_info.c |  2 ++
 arch/arm/cpu/armv7/sunxi/prcm.c | 12 +++-
 arch/arm/include/asm/arch-sunxi/clock.h |  2 +-
 arch/arm/include/asm/arch-sunxi/cpu.h   |  1 +
 arch/arm/include/asm/arch-sunxi/gpio.h  | 34 +++--
 arch/arm/include/asm/arch-sunxi/mmc.h   |  2 +-
 arch/arm/include/asm/arch-sunxi/prcm.h  |  2 +-
 board/sunxi/Kconfig |  9 -
 board/sunxi/MAINTAINERS |  5 +
 configs/Ippo_q8h_defconfig  |  4 
 drivers/mmc/sunxi_mmc.c |  2 +-
 include/configs/sun8i.h | 23 ++
 include/configs/sunxi-common.h  | 11 ++-
 17 files changed, 123 insertions(+), 15 deletions(-)
 create mode 100644 configs/Ippo_q8h_defconfig
 create mode 100644 include/configs/sun8i.h

-- 
2.1.1

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[U-Boot] [PATCH 6/9] ARM: sunxi: Add support for R_PIO gpio banks

[Chen-Yu Tsai]

From: Hans de Goede hdego...@redhat.com

The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.

Signed-off-by: Hans de Goede hdego...@redhat.com
[w...@csie.org: expanded commit message]
[w...@csie.org: add pin bank M and expand comments]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 arch/arm/include/asm/arch-sunxi/gpio.h | 25 +++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index b94ec4d..bbe815a 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -10,6 +10,7 @@
 #define _SUNXI_GPIO_H
 
 #include linux/types.h
+#include asm/arch/cpu.h
 
 /*
  * sunxi has 9 banks of gpio, they are:
@@ -29,6 +30,19 @@
 #define SUNXI_GPIO_I   8
 #define SUNXI_GPIO_BANKS 9
 
+/*
+ * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
+ * at a different register offset.
+ *
+ * sun6i has 2 banks:
+ * PL0 - PL8  | PM0 - PM7
+ *
+ * sun8i has 1 bank:
+ * PL0 - PL11
+ */
+#define SUNXI_GPIO_L   9
+#define SUNXI_GPIO_M   10
+
 struct sunxi_gpio {
u32 cfg[4];
u32 dat;
@@ -50,8 +64,9 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
 };
 
-#define BANK_TO_GPIO(bank) \
-   ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[bank]
+#define BANK_TO_GPIO(bank) (((bank)  SUNXI_GPIO_BANKS) ? \
+   ((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)-gpio_bank[bank] : \
+   ((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)-gpio_bank[(bank) - 
SUNXI_GPIO_BANKS])
 
 #define GPIO_BANK(pin) ((pin)  5)
 #define GPIO_NUM(pin)  ((pin)  0x1f)
@@ -75,6 +90,8 @@ struct sunxi_gpio_reg {
 #define SUNXI_GPIO_G_NR32
 #define SUNXI_GPIO_H_NR32
 #define SUNXI_GPIO_I_NR32
+#define SUNXI_GPIO_L_NR32
+#define SUNXI_GPIO_M_NR32
 
 #define SUNXI_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + 0)
@@ -89,6 +106,8 @@ enum sunxi_gpio_number {
SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+   SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I),
+   SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
 };
 
 /* SUNXI GPIO number definitions */
@@ -101,6 +120,8 @@ enum sunxi_gpio_number {
 #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
 #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
 #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
+#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
+#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
 
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT   0
-- 
2.1.1

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[U-Boot] [PATCH 2/9] ARM: sunxi: Add sun8i (A23) UART0 pin mux support

[Chen-Yu Tsai]

UART0 pin muxes on the A23 have a different function value.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 arch/arm/include/asm/arch-sunxi/gpio.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index ba7e69b..b94ec4d 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -125,8 +125,14 @@ enum sunxi_gpio_number {
 #define SUNXI_GPF0_SDC02
 
 #define SUNXI_GPF2_SDC02
+
+#ifdef CONFIG_SUN8I
+#define SUNXI_GPF2_UART0_TX3
+#define SUNXI_GPF4_UART0_RX3
+#else
 #define SUNXI_GPF2_UART0_TX4
 #define SUNXI_GPF4_UART0_RX4
+#endif
 
 #define SUN4I_GPG0_SDC14
 
-- 
2.1.1

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[U-Boot] [PATCH 3/9] ARM: sunxi: Add support for uart0 on port F (mmc0)

[Chen-Yu Tsai]

Allwinner SoCs provide uart0 muxed with mmc0, which can then be used
with a micro SD breakout board. On the A23, this is the only way to
use uart0.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 arch/arm/cpu/armv7/sunxi/board.c | 11 ++-
 include/configs/sunxi-common.h   |  2 ++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index b6d63db..29d45b6 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -50,7 +50,16 @@ u32 spl_boot_mode(void)
 
 int gpio_init(void)
 {
-#if CONFIG_CONS_INDEX == 1  (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#if CONFIG_CONS_INDEX == 1  defined(CONFIG_UART0_PORT_F)
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+   /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
+   sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
+   sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
+   sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
+   sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+   sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1  (defined(CONFIG_SUN4I) || 
defined(CONFIG_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 7571e0e..7857a56 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -77,6 +77,7 @@
 #define CONFIG_INITRD_TAG
 
 /* mmc config */
+#if !defined(CONFIG_UART0_PORT_F)
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
@@ -84,6 +85,7 @@
 #define CONFIG_MMC_SUNXI_SLOT  0
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0   /* first detected MMC 
controller */
+#endif
 
 /* 4MB of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (4  20))
-- 
2.1.1

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[U-Boot] [PATCH 1/9] ARM: sunxi: Fix build break when CONFIG_MMC is not defined

[Chen-Yu Tsai]

BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when
CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally
include it when CONFIG_MMC is enabled, as we do for CONFIG_AHCI.

This is used when we want to use uart0 from port F, which conflicts
with mmc0.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 include/configs/sunxi-common.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index a31656e..7571e0e 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -227,6 +227,12 @@
pxefile_addr_r=0x4320\0 \
ramdisk_addr_r=0x4330\0
 
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
 #ifdef CONFIG_AHCI
 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
 #else
@@ -240,7 +246,7 @@
 #endif
 
 #define BOOT_TARGET_DEVICES(func) \
-   func(MMC, mmc, 0) \
+   BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
-- 
2.1.1

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[U-Boot] [PATCH 8/9] ARM: sunxi: Add support for using R_UART as console

[Chen-Yu Tsai]

The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.

Add support for R_UART so we can have a console while using mmc.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 arch/arm/cpu/armv7/sunxi/board.c   | 4 
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 ++
 arch/arm/include/asm/arch-sunxi/cpu.h  | 1 +
 arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
 include/configs/sunxi-common.h | 1 +
 5 files changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 61c1ba9..aeb2c2f 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -75,6 +75,10 @@ int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 5  defined(CONFIG_SUN8I)
+   sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
+   sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+   sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c 
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 8387b93..1eae976 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -13,6 +13,7 @@
 #include common.h
 #include asm/io.h
 #include asm/arch/clock.h
+#include asm/arch/prcm.h
 #include asm/arch/sys_proto.h
 
 void clock_init_uart(void)
@@ -20,6 +21,7 @@ void clock_init_uart(void)
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
+#if CONFIG_CONS_INDEX  5
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
   APB2_CLK_RATE_N_1|
@@ -35,6 +37,10 @@ void clock_init_uart(void)
setbits_le32(ccm-apb2_reset_cfg,
 1  (APB2_RESET_UART_SHIFT +
   CONFIG_CONS_INDEX - 1));
+#else
+   /* enable R_PIO and R_UART clocks, and de-assert resets */
+   prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
 
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
writel(PLL6_CFG_DEFAULT, ccm-pll6_cfg);
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h 
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 313e6c8..0de79a0 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -111,6 +111,7 @@
 #define SUNXI_AVG_BASE 0x01ea
 
 #define SUNXI_PRCM_BASE0x01f01400
+#define SUNXI_R_UART_BASE  0x01f02800
 #define SUNXI_R_PIO_BASE   0x01f02c00
 #define SUNXI_P2WI_BASE0x01f03400
 
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index bbe815a..c216960 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -164,6 +164,9 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPI4_SDC32
 
+#define SUN8I_GPL2_R_UART_TX   2
+#define SUN8I_GPL3_R_UART_RX   2
+
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE0
 #define SUNXI_GPIO_PULL_UP 1
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 7857a56..7e54296 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -42,6 +42,7 @@
 #define CONFIG_SYS_NS16550_COM2SUNXI_UART1_BASE
 #define CONFIG_SYS_NS16550_COM3SUNXI_UART2_BASE
 #define CONFIG_SYS_NS16550_COM4SUNXI_UART3_BASE
+#define CONFIG_SYS_NS16550_COM5SUNXI_R_UART_BASE
 
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE  0x4000
-- 
2.1.1

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[U-Boot] [PATCH 9/9] ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfig

[Chen-Yu Tsai]

Ippo q8h is a series of A23 tablet boards. This defconfig
is for v5 of these boards, though for u-boot purposes they
are mostly the same.

See: http://linux-sunxi.org/Ippo_q8h

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 board/sunxi/MAINTAINERS| 5 +
 configs/Ippo_q8h_defconfig | 4 
 2 files changed, 9 insertions(+)
 create mode 100644 configs/Ippo_q8h_defconfig

diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 7afe45e..febd126 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -50,3 +50,8 @@ COLOMBUS BOARD
 M: Maxime Ripard maxime.rip...@free-electrons.com
 S: Maintained
 F: configs/Colombus_defconfig
+
+IPPO-Q8H-V5 BOARD
+M: CHen-Yu Tsai w...@csie.org
+S: Maintained
+F: configs/Ippo_q8h_v5_defconfig
diff --git a/configs/Ippo_q8h_defconfig b/configs/Ippo_q8h_defconfig
new file mode 100644
index 000..781f137
--- /dev/null
+++ b/configs/Ippo_q8h_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS=IPPO_Q8H_V5,CONS_INDEX=5
+CONFIG_ARM=y
+CONFIG_TARGET_SUN8I=y
+CONFIG_DEFAULT_DEVICE_TREE=sun8i-a23-ippo-q8h-v5.dtb
-- 
2.1.1

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[U-Boot] [PATCH 7/9] ARM: sunxi: Allow specifying module in prcm apb0 init function

[Chen-Yu Tsai]

The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 arch/arm/cpu/armv7/sunxi/prcm.c| 12 +++-
 arch/arm/include/asm/arch-sunxi/prcm.h |  2 +-
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
index 7b3ee89..19b4938 100644
--- a/arch/arm/cpu/armv7/sunxi/prcm.c
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -21,13 +21,15 @@
 #include asm/arch/prcm.h
 #include asm/arch/sys_proto.h
 
-void prcm_init_apb0(void)
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
 {
struct sunxi_prcm_reg *prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
-   setbits_le32(prcm-apb0_gate, PRCM_APB0_GATE_P2WI |
-  PRCM_APB0_GATE_PIO);
-   setbits_le32(prcm-apb0_reset, PRCM_APB0_RESET_P2WI |
-   PRCM_APB0_RESET_PIO);
+   /* open the clock for module */
+   setbits_le32(prcm-apb0_gate, flags);
+
+   /* deassert reset for module */
+   setbits_le32(prcm-apb0_reset, flags);
 }
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h 
b/arch/arm/include/asm/arch-sunxi/prcm.h
index 1b40f09..3d3bfa6 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -233,6 +233,6 @@ struct sunxi_prcm_reg {
u32 dram_tst;   /* 0x190 */
 };
 
-void prcm_init_apb0(void);
+void prcm_apb0_enable(u32 flags);
 #endif /* __ASSEMBLY__ */
 #endif /* _PRCM_H */
-- 
2.1.1

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[U-Boot] [PATCH 5/9] ARM: sunxi: Add basic A23 support

[Chen-Yu Tsai]

The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 arch/arm/Kconfig|  3 +++
 arch/arm/cpu/armv7/sunxi/Makefile   |  2 ++
 arch/arm/cpu/armv7/sunxi/board.c|  3 ++-
 arch/arm/cpu/armv7/sunxi/cpu_info.c |  2 ++
 arch/arm/include/asm/arch-sunxi/clock.h |  2 +-
 board/sunxi/Kconfig |  9 -
 include/configs/sun8i.h | 23 +++
 7 files changed, 41 insertions(+), 3 deletions(-)
 create mode 100644 include/configs/sun8i.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e3e7e78..cb691b2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -450,6 +450,9 @@ config TARGET_SUN6I
 config TARGET_SUN7I
bool Support sun7i
 
+config TARGET_SUN8I
+   bool Support sun8i
+
 config TARGET_SNOWBALL
bool Support snowball
 
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 2a42dca..24f1dae 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -12,10 +12,12 @@ obj-y   += board.o
 obj-y  += clock.o
 obj-y  += pinmux.o
 obj-$(CONFIG_SUN6I)+= prcm.o
+obj-$(CONFIG_SUN8I)+= prcm.o
 obj-$(CONFIG_SUN4I)+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)+= clock_sun4i.o
 obj-$(CONFIG_SUN6I)+= clock_sun6i.o
 obj-$(CONFIG_SUN7I)+= clock_sun4i.o
+obj-$(CONFIG_SUN8I)+= clock_sun6i.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y  += cpu_info.o
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 29d45b6..61c1ba9 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -100,7 +100,8 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD  (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
+#if !defined CONFIG_SPL_BUILD  (defined CONFIG_SUN7I || \
+   defined CONFIG_SUN6I || defined CONFIG_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
mrc p15, 0, r0, c1, c0, 1\n
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c 
b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 40c4e13..4f2a09c 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -27,6 +27,8 @@ int print_cpuinfo(void)
puts(CPU:   Allwinner A31 (SUN6I)\n);
 #elif defined CONFIG_SUN7I
puts(CPU:   Allwinner A20 (SUN7I)\n);
+#elif defined CONFIG_SUN8I
+   puts(CPU:   Allwinner A23 (SUN8I)\n);
 #else
 #warning Please update cpu_info.c with correct CPU information
puts(CPU:   SUNXI Family\n);
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h 
b/arch/arm/include/asm/arch-sunxi/clock.h
index 8f5d860..012c2af 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -15,7 +15,7 @@
 #define CLK_GATE_CLOSE 0x0
 
 /* clock control module regs definition */
-#ifdef CONFIG_SUN6I
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
 #include asm/arch/clock_sun6i.h
 #else
 #include asm/arch/clock_sun4i.h
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 05defac..16f6db4 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -27,7 +27,14 @@ config SYS_CONFIG_NAME
 
 endif
 
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
+if TARGET_SUN8I
+
+config SYS_CONFIG_NAME
+   default sun8i
+
+endif
+
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I
 
 config SYS_CPU
default armv7
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
new file mode 100644
index 000..1c1a7cd
--- /dev/null
+++ b/include/configs/sun8i.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014 Chen-Yu Tsai w...@csie.org
+ *
+ * Configuration settings for the Allwinner A23 (sun8i) CPU
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A23 specific configuration
+ */
+#define CONFIG_SUN8I   /* sun8i SoC generation */
+#define CONFIG_SYS_PROMPT  sun8i# 
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include configs/sunxi-common.h
+
+#endif /* __CONFIG_H */
-- 
2.1.1

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Re: [U-Boot] [PATCH 0/5] ARM: sheevaplug: refresh for 201410

[DrEagle]

Thank you Prafulla,

Is there a pull request planned to master 2014-10 release from 
git-marvell ?


Regards

Le 2014-10-01 13:21, Prafulla Wadaskar a écrit :

-Original Message-
From: drEagle [mailto:drea...@doukki.net]
Sent: 26 September 2014 14:47
To: Prafulla Wadaskar; Albert ARIBAUD
Cc: Nobuhiro Iwamatsu; U-Boot; Pantelis Antoniou; Tom
Rini
Subject: Re: [PATCH 0/5] ARM: sheevaplug: refresh for
201410

Hi,

Is there any actions to take theses patches mainlined ?



This patch series is applies to u-boot-marvell.git master branch

Thanks and regards...
Prafulla . . .


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Re: [U-Boot] [PATCH 0/5] ARM: sheevaplug: refresh for 201410

[Prafulla Wadaskar]

 -Original Message-
 From: DrEagle [mailto:drea...@doukki.net]
 Sent: 07 October 2014 12:59
 To: Prafulla Wadaskar
 Cc: drEagle; Albert ARIBAUD; Nobuhiro Iwamatsu; U-Boot;
 Pantelis Antoniou; Tom Rini
 Subject: RE: [PATCH 0/5] ARM: sheevaplug: refresh for
 201410
 
 Thank you Prafulla,
 
 Is there a pull request planned to master 2014-10
 release from
 git-marvell ?

Yes, it has been already requested to Albert.

Regards...
Prafulla . . .
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Re: [U-Boot] am335x: using GPIO1 pins as input

[Yegor Yefremov]

On Mon, Oct 6, 2014 at 5:39 PM, Yegor Yefremov
yegorsli...@googlemail.com wrote:
 U-Boot 2014.07

 I'm trying to use ping 44..47 as input. I've configured PINMUX and
 invoked request, direction etc. I always get 0 from gpio_get_value()

 int val;

 gpio_request(44, dip_s1):
 gpio_request(45, dip_s2);
 gpio_request(46, dip_s3);
 gpio_request(47, dip_s4);

 gpio_direction_input(44);
 gpio_direction_input(45);
 gpio_direction_input(46);
 gpio_direction_input(47);

 val = gpio_get_value(44);
 printf(DIP value: %d\n, val);
 val = gpio_get_value(45);
 printf(DIP value: %d\n, val);
 val = gpio_get_value(46);
 printf(DIP value: %d\n, val);
 val = gpio_get_value(47);
 printf(DIP value: %d\n, val);

 After reading http://e2e.ti.com/support/arm/sitara_arm/f/791/t/248181.aspx
 I've checked clock registers CM_PER_L4LS_CLKSTCTRL (bit 8 L4LS_GCLK
 is set) and also CM_PER_GPIO1_CLKCTRL has value 2 - enabled. I can
 also see, that arch/arm/cpu/armv7/am33xx/clock_am33xx.c-enable_basic_clocks()
 enables clocks for GPIO1.

 Then I checked GPIO1 specific registers and found out, that
 GPIO_SYSSTATUS (0x4804C114) shows 0x i.e. GPIO is still in
 reset. Any idea, what should be activated/setup in order to get the
 second GPIO bank working?

Some more details. These pins are working in Linux. In U-boot I can
use them as output via gpio toggle 44 (I can measure the signal via
oscilloscope). So the requirements, that were mentioned in the thread
on TI forum are met. I still cannot understand from TRM, if debounce
clock is necessary or optional in order to get input working?

Yegor
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[U-Boot] Uboot send pull request

[uboot]

Hi Tom,

Please pull the following patch from u-boot-nds32 into your tree.
Thanks!

The following changes since commit d05bfd0586ccebe96e31976459c8ef45ec65e109:

  Merge branch 'master' of git://git.denx.de/u-boot-i2c (2013-08-06 09:49:06 
-0400)

are available in the git repository at:

  git://git.denx.de/u-boot-nds32.git master

Andes (1):
  nds32: Change of NDS32 Custodian

ken kuo (2):
  nds32: introduce DMA allocation API
  nds32: fix the missing COBJS-y change

 MAINTAINERS  |2 +-
 arch/nds32/include/asm/dma-mapping.h |   33 +
 board/AndesTech/adp-ag102/Makefile   |2 +-
 3 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 arch/nds32/include/asm/dma-mapping.h
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[U-Boot] Debugging u-boot

[Kantanu Kumar Mohapatra]

Hi

In reply to this, can anyone please suggest me, how to debug the
fw_printenv code in u-boot?
I am using buildroot-2014.02, which used uboot-tools-2014.01. But I am
having few custom changes in uboot-2010.03, those I want to use, in
tools-2014.01 I can see as of now, the code fails on fw_printenv().

Thanks,
Kantanu

Dear Kantanu,

In message 
20141002235515.0f6337076cc849064921372b9de1c389.ce86d191f7.mail...@email10.secureserver.net
you wrote:

 I am Kantanu, working for U-Boot related stuff as a freelancer. Can
 you please suggest how to see the u-boot logs. I am using syslog to
 see the logs, but how to get these u-boot stderr logs to syslog?

It is always best to ask such questions on the U-Boot mailing list.

U-Boot does not support a file concept, and thus no file redirection
either. So there is no easy way to redirect console output to a log
buffer. You would have to implement such a redirecting driver.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
What if is a trademark of Hewlett Packard, so stop using it in your
sentences without permission, or risk being sued.
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[U-Boot] Sorry for the mistake of sending Uboot send pull request

[uboot]

 Hi Tom,
 
 Sorry for the mistake of sending mail of Uboot send pull request.
 
 Please forget and ignore this mail.
 
 Following is the content of previous Uboot send pull request mail:
=


 Hi Tom,

 Please pull the following patch from u-boot-nds32 into your tree.
 Thanks!

 The following changes since commit d05bfd0586ccebe96e31976459c8ef45ec65e109:
 
 Merge branch 'master' of git://git.denx.de/u-boot-i2c (2013-08-06 09:49:06 
-0400)
 
 are available in the git repository at:
 
   git://git.denx.de/u-boot-nds32.git master
 
 Andes (1):
nds32: Change of NDS32 Custodian
 
 ken kuo (2):
  nds32: introduce DMA allocation API
  nds32: fix the missing COBJS-y change

 MAINTAINERS  |2 +-
 arch/nds32/include/asm/dma-mapping.h |   33 +
 board/AndesTech/adp-ag102/Makefile   |2 +-
 3 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 arch/nds32/include/asm/dma-mapping.h
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[U-Boot] [PATCH] ot1200: remove superfluous string tag

[Christian Gmeiner]

Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
 board/bachmann/ot1200/Kconfig | 5 -
 1 file changed, 5 deletions(-)

diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
index 55a825d..6cf2573 100644
--- a/board/bachmann/ot1200/Kconfig
+++ b/board/bachmann/ot1200/Kconfig
@@ -1,23 +1,18 @@
 if TARGET_OT1200
 
 config SYS_CPU
-   string
default armv7
 
 config SYS_BOARD
-   string
default ot1200
 
 config SYS_VENDOR
-   string
default bachmann
 
 config SYS_SOC
-   string
default mx6
 
 config SYS_CONFIG_NAME
-   string
default ot1200
 
 endif
-- 
1.9.3

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Re: [U-Boot] [PATCH] ot1200: remove superfluous string tag

[Masahiro Yamada]

On Tue,  7 Oct 2014 10:58:51 +0200
Christian Gmeiner christian.gmei...@gmail.com wrote:

 Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
 ---
  board/bachmann/ot1200/Kconfig | 5 -
  1 file changed, 5 deletions(-)
 
 diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
 index 55a825d..6cf2573 100644
 --- a/board/bachmann/ot1200/Kconfig
 +++ b/board/bachmann/ot1200/Kconfig
 @@ -1,23 +1,18 @@
  if TARGET_OT1200
  
  config SYS_CPU
 - string
   default armv7
  
  config SYS_BOARD
 - string
   default ot1200
  
  config SYS_VENDOR
 - string
   default bachmann
  
  config SYS_SOC
 - string
   default mx6
  
  config SYS_CONFIG_NAME
 - string
   default ot1200
  
  endif
 -- 
 1.9.3

Reviewed-by: Masahiro Yamada yamad...@jp.panasonic.com

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Re: [U-Boot] [PATCH 2/3] fdt: add fdt_add_display_timings(..) and friends

[Christian Gmeiner]

Hi Simon

 On 15 September 2014 07:06, Christian Gmeiner christian.gmei...@gmail.com
 wrote:

 This new function is used to set all display-timings
 properties based on fb_videomode.

 display-timings {
 timing0 {
 clock-frequency = 2500;
 hactive = 640;
 vactive = 480;
 hback-porch = 48;
 hfront-porch = 16;
 vback-porch = 31;
 vfront-porch = 12;
 hsync-len = 96;
 vsync-len = 2;
 };
 };

 Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com


The ot1200 base patch has landed in u-boot-imx and I will work to get this EDID
stuff mainline too.


 Thanks for the patch. There are a few style violations and I have a few
 minor comments below.

 $ ./tools/patman/patman -c1 -n
 Cleaned 1 patches
 0 errors, 4 warnings, 0 checks for
 0001-fdt-add-fdt_add_display_timings-.-and-friends.patch:
 warning: common/fdt_support.c,1400: line over 80 characters
 warning: common/fdt_support.c,1406: braces {} are not necessary for single
 statement blocks
 warning: common/fdt_support.c,1412: braces {} are not necessary for single
 statement blocks
 warning: include/fdt_support.h,96: line over 80 characters

 checkpatch.pl found 0 error(s), 4 warning(s), 0 checks(s)


Will fix them in the next patch series about this topic.



 ---
  common/fdt_support.c  | 56
 +++
  include/fdt_support.h |  5 +
  2 files changed, 61 insertions(+)

 diff --git a/common/fdt_support.c b/common/fdt_support.c
 index 784a570..72004a3 100644
 --- a/common/fdt_support.c
 +++ b/common/fdt_support.c
 @@ -11,6 +11,7 @@
  #include stdio_dev.h
  #include linux/ctype.h
  #include linux/types.h
 +#include linux/fb.h
  #include asm/global_data.h
  #include libfdt.h
  #include fdt_support.h
 @@ -1373,6 +1374,61 @@ err_size:
  #endif

  /*
 +* fdt_find_display_timings: finde node containing display-timings
 +*
 +* @fdt: fdt to device tree
 +* @compat: compatiable string to match
 +* @parent: parent node containing display-timings


 or -ve error code FDT_ERROR_...


ok


 +*/
 +int fdt_find_display_timings(void *fdt, const char *compat, const char
 *parent)
 +{
 +   int coff = fdt_node_offset_by_compatible(fdt, -1, compat);
 +   int poff = fdt_subnode_offset(fdt, coff, parent);
 +   int noff = fdt_subnode_offset(fdt, poff, display-timings);
 +


 Can we return an error when we see one? Here it will return a somewhat
 meaningless error if (say) the first call finds no node.


I can return the return code of the three functions. Something like:

int coff, poff, noff;

coff = fdt_node_offset_by_compatible(..);
if (coff  0)
return coff;

poff = fdt_subnode_offset(..);
if (poff  0)


Would that be better?


 +   return noff;
 +}
 +
 +/*
 +* fdt_update_display_timings: update display-timings properties
 +*
 +* @fdt: fdt to device tree
 +* @compat: compatiable string to match


 compatible


ok


 +* @parent: parent node containing display-timings


 @parent: parent node containing display-timings subnode


yes... thats better.


 +* @mode: ptr to fb_videomode


 Well we know that from the code. Perhaps display timings to add to the
 device tree


sounds good to me.


 +*/


 This function is exported so the comment should go in the header file.


okay.


 +int fdt_update_display_timings(void *fdt, const char *compat, const char
 *parent,
 +   struct fb_videomode *mode)
 +{
 +   int noff = fdt_find_display_timings(fdt, compat, parent);
 +
 +   /* check if display-timings subnode does exist */
 +   if (noff == -FDT_ERR_NOTFOUND) {


 if (noff  0)

 would be better

ok



 +   return noff;
 +   }
 +
 +   /* check if timing0 subnode exists */
 +   noff = fdt_subnode_offset(fdt, noff, timing0);
 +   if (noff == -FDT_ERR_NOTFOUND) {


 same here

ok



 +   return noff;
 +   }
 +
 +   /* set all needed properties */
 +   fdt_setprop_u32(fdt, noff, clock-frequency,
 +   PICOS2KHZ(mode-pixclock) * 1000);
 +   fdt_setprop_u32(fdt, noff, hactive, mode-xres);
 +   fdt_setprop_u32(fdt, noff, vactive, mode-yres);
 +   fdt_setprop_u32(fdt, noff, hback-porch, mode-left_margin);
 +   fdt_setprop_u32(fdt, noff, hfront-porch, mode-right_margin);
 +   fdt_setprop_u32(fdt, noff, vback-porch, mode-upper_margin);
 +   fdt_setprop_u32(fdt, noff, vfront-porch, mode-lower_margin);
 +   fdt_setprop_u32(fdt, noff, hsync-len, mode-hsync_len);
 +   fdt_setprop_u32(fdt, noff, vsync-len, mode-vsync_len);


 Should you have error checking here? We might run out of space.

Sounds like a good idea - will change the current code.



 +
 +   return 0;
 +}
 +
 +/*
   * Verify the physical address of device tree node for a given alias
   *
   * This function locates the device tree node of a given alias, 

[U-Boot] [PATCH 1/2] net: Add a command to access the EEPROM from ethernet devices

[Alban Bedel]

Many ethernet devices use an EEPROM to store various settings, most
commonly the device MAC address. But on some devices it can contains
a lot more, for example USB device might also have many USB related
parameters.

This commit add a set of commands to read/write this EEPROM, write a
default configuration and read/write the device MAC address. The
defaults command allow priming the EEPROM for devices that need more
than just a MAC address in the EEPROM.

Change-Id: I9f2d15f84b772dc680349c65c89e772780823745
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
 common/cmd_net.c | 134 +++
 include/net.h|  28 
 net/eth.c|  46 +++
 3 files changed, 208 insertions(+)

diff --git a/common/cmd_net.c b/common/cmd_net.c
index 09489d4..f4952d5 100644
--- a/common/cmd_net.c
+++ b/common/cmd_net.c
@@ -445,3 +445,137 @@ U_BOOT_CMD(
 );
 
 #endif  /* CONFIG_CMD_LINK_LOCAL */
+
+#if defined(CONFIG_CMD_ETH_EEPROM)
+static int do_eth_eeprom_rw(struct eth_device *dev,
+   int argc, char * const argv[])
+{
+   ulong addr, offset, length = 1;
+
+   if (argc  4)
+   return CMD_RET_USAGE;
+
+   addr = simple_strtoul(argv[2], NULL, 16);
+   offset = simple_strtoul(argv[3], NULL, 16);
+   if (argc  4)
+   length = simple_strtoul(argv[4], NULL, 16);
+
+   if (!strcmp(argv[0], write)) {
+   if (eth_eeprom_write(dev, offset, length, (void *)addr)) {
+   printf(EEPROM write failed\n);
+   return CMD_RET_FAILURE;
+   }
+   return CMD_RET_SUCCESS;
+   } else if (!strcmp(argv[0], read)) {
+   if (eth_eeprom_read(dev, offset, length, (void *)addr)) {
+   printf(EEPROM read failed\n);
+   return CMD_RET_FAILURE;
+   }
+   return CMD_RET_SUCCESS;
+   }
+
+   return CMD_RET_USAGE;
+}
+
+static int do_eth_eeprom_defaults(struct eth_device *dev,
+   int argc, char * const argv[])
+{
+   if (eth_eeprom_defaults(dev)) {
+   printf(EEPROM write failed\n);
+   return CMD_RET_FAILURE;
+   }
+
+   return CMD_RET_SUCCESS;
+}
+
+static int do_eth_eeprom_set_mac(struct eth_device *dev,
+   int argc, char * const argv[])
+{
+   u8 mac[6];
+
+   if (argc  3)
+   return CMD_RET_USAGE;
+
+   eth_parse_enetaddr(argv[2], mac);
+   if (!is_valid_ether_addr(mac)) {
+   printf(Invalid mac address given\n);
+   return CMD_RET_FAILURE;
+   }
+
+   printf(Writing MAC to EEPROM \n);
+   if (eth_eeprom_write_mac(dev, mac)) {
+   printf(EEPROM write failed\n);
+   return CMD_RET_FAILURE;
+   }
+
+   return CMD_RET_SUCCESS;
+}
+
+static int do_eth_eeprom_show_mac(struct eth_device *dev,
+   int argc, char * const argv[])
+{
+   u8 data[6];
+
+   if (eth_eeprom_read_mac(dev, data)) {
+   printf(EEPROM read failed\n);
+   return CMD_RET_FAILURE;
+   }
+
+   printf(%pM\n, data);
+   if (!is_valid_ether_addr(data))
+   printf(Warning: MAC address is not valid!\n);
+
+   return CMD_RET_SUCCESS;
+}
+
+static int do_eth_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
+   char * const argv[])
+{
+   struct eth_device *dev;
+   char *endp = NULL;
+   int index;
+
+   if (argc  3)
+   return CMD_RET_USAGE;
+
+   /* Get the ethernet device, by ID or by name */
+   index = (int) simple_strtoul(argv[2], endp, 16);
+   if (endp  argv[2])
+   dev = eth_get_dev_by_index(index);
+   else
+   dev = eth_get_dev_by_name(argv[2]);
+
+   if (!dev) {
+   printf(Ethernet device not found\n);
+   return CMD_RET_FAILURE;
+   }
+
+   if (!strcmp(argv[1], read) || !strcmp(argv[1], write))
+   return do_eth_eeprom_rw(dev, argc - 1, argv + 1);
+   if (!strcmp(argv[1], defaults))
+   return do_eth_eeprom_defaults(dev, argc - 1, argv + 1);
+   if (!strcmp(argv[1], set_mac))
+   return do_eth_eeprom_set_mac(dev, argc - 1, argv + 1);
+   if (!strcmp(argv[1], show_mac))
+   return do_eth_eeprom_show_mac(dev, argc - 1, argv + 1);
+
+   printf(Unknown sub command: %s\n, argv[1]);
+
+   return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+   eth_eeprom, 6,  0,  do_eth_eeprom,
+   access the EEPROM of ethernet devices,
+   read dev addr off [size]\n
+   - read 'size' bytes starting at offset 'off' to memory address 
'addr'.\n
+   eth_eeprom write dev addr off [size]\n
+   - write 'size' bytes starting at offset 'off' from memory address 
'addr'.\n
+   eth_eeprom defaults dev\n
+ 

[U-Boot] [PATCH 2/2] usb: eth: smsc95xx: Add EEPROM access support

[Alban Bedel]

Use the new ethernet eeprom API to allow the user to read/write the
EEPROM.

Change-Id: I21233b6ee805a75bd8a03ca12e22c41421b7629c
Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
 drivers/usb/eth/smsc95xx.c | 199 +++--
 1 file changed, 192 insertions(+), 7 deletions(-)

diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index 6bca34d..eb29565 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -59,6 +59,8 @@
 
 #define E2P_CMD0x30
 #define E2P_CMD_BUSY_  0x8000
+#define E2P_CMD_EWEN_  0x2000
+#define E2P_CMD_WRITE_ 0x3000
 #define E2P_CMD_READ_  0x
 #define E2P_CMD_TIMEOUT_   0x0400
 #define E2P_CMD_LOADED_0x0200
@@ -146,6 +148,131 @@ struct smsc95xx_private {
int have_hwaddr;  /* 1 if we have a hardware MAC address */
 };
 
+#ifdef CONFIG_CMD_ETH_EEPROM
+static u8 eeprom_defaults[] = {
+   /* 0x00 */
+   0xA5,   /* Signature */
+   0xFF, 0xFF, /* MAC bytes 0-1 */
+   0xFF, 0xFF, /* MAC bytes 2-3 */
+   0xFF, 0xFF, /* MAC bytes 4-5 */
+   0x01,   /* FS Polling Interval for Interrupt Endpoint */
+   0x01,   /* HS Polling Interval for Interrupt Endpoint */
+   0x01,   /* Configuration Flags */
+   0x09, 0x04, /* Language ID */
+   0x0a,   /* Manufacturer ID String Descriptor Length (bytes) */
+   0x2f,   /* Manufacturer ID String Descriptor EEPROM Word Offset 
*/
+   0x10,   /* Product Name String Descriptor Length (bytes) */
+   0x34,   /* Product Name String Descriptor EEPROM Word Offset */
+   /* 0x10 */
+   0x12,   /* Serial Number String Descriptor Length (bytes) */
+   0x3c,   /* Serial Number String Descriptor EEPROM Word Offset */
+   0x08,   /* Configuration String Descriptor Length (bytes) */
+   0x45,   /* Configuration String Descriptor Word Offset */
+   0x08,   /* Interface String Descriptor Length (bytes) */
+   0x49,   /* Interface String Descriptor Word Offset */
+   0x12,   /* Hi-Speed Device Descriptor Length (bytes) */
+   0x1d,   /* Hi-Speed Device Descriptor Word Offset */
+   0x12,   /* Hi-Speed Configuration and Interface Descriptor 
Length (bytes) */
+   0x26,   /* Hi-Speed Configuration and Interface Descriptor Word 
Offset */
+   0x12,   /* Full-Speed Device Descriptor Length (bytes) */
+   0x1d,   /* Full-Speed Device Descriptor Word Offset */
+   0x12,   /* Full-Speed Configuration and Interface Descriptor 
Length (bytes) */
+   0x26,   /* Full-Speed Configuration and Interface Descriptor 
Word Offset */
+   0x00, 0x00, /* RESERVED */
+   /* 0x20 */
+   0x24, 0x04, /* Vendor ID */
+   0x14, 0x95, /* Product ID */
+   0x00, 0x01, /* Device ID */
+   0x9b,   /* Config Data Byte 1 Register (CFG1) */
+   0x18,   /* Config Data Byte 2 Register (CFG2) */
+   0x00,   /* Config Data Byte 3 Register (CFG3) */
+   0x32,   /* Non-Removable Devices Register (NRD) */
+   0x00,   /* Port Disable (Self) Register (PDS) */
+   0x00,   /* Port Disable (Bus) Register (PDB) */
+   0x01,   /* Max Power (Self) Register (MAXPS) */
+   0x00,   /* Max Power (Bus) Register (MAXPB) */
+   0x01,   /* Hub Controller Max Current (Self) Register (HCMCS) */
+   0x00,   /* Hub Controller Max Current (Bus) Register (HCMCB) */
+   /* 0x30 */
+   0x32,   /* Power-on Time Register (PWRT) */
+   0x00,   /* Boost_Up Register (BOOSTUP) */
+   0x00,   /* Boost_5 Register (BOOST5) */
+   0x00,   /* Boost_4:2 Register (BOOST42) */
+   0x00,   /* RESERVED */
+   0x00,   /* Port Swap Register (PRTSP) */
+   0x21,   /* Port Remap 12 Register (PRTR12) */
+   0x43,   /* Port Remap 34 Register (PRTR34) */
+   0x05,   /* Port Remap 5 Register (PRTR5) */
+   0x01,   /* Status/Command Register (STCD) */
+   /* 0x3A  - Device Descriptor */
+   0x12, 0x01,
+   0x00, 0x02,
+   0xff, 0x00,
+   /* 0x40 */
+   0xff, 0x40,
+   0x24, 0x04,
+   0x00, 0xec,
+   0x00, 0x01,
+   0x01, 0x02,
+   0x03, 0x01,
+   /* 0x4C  - Configuration and Interface Descriptor */
+   0x09, 0x02,
+   0x27, 0x00,
+   /* 0x50 */
+   0x01, 0x01,
+   0x04, 0xc0,
+   0x00, 0x09,
+   0x04, 0x00,
+   0x00, 0x03,
+   0xff, 0x00,
+   0xff, 0x05,
+   /* 0x5E  - Manufacturer ID String Descriptor */
+   0x0a, 0x03,
+   

Re: [U-Boot] U-Boot Mini Summit

[Detlev Zundel]

Hi Albert,

[...]

 I would have liked to attend, but for personal reasons could not free
 myself up.

That's of course unfortunate.

 Is there any possibility of a Google Hangout or anything similar?

To be honest - I have no idea how to do this or if this is feasible.
Last year Marek volunteered to try it, but it did not work out.  IIRC
the conference WiFi wasn't stable enough to do that.

Is anyone (who also attends) willing to try setting up such a Google
Hangout this year again?

Best wishes
  Detlev
  
-- 
Be careful in casting out your devil 'lest you cast out the best thing
about you.
   -- Friedrich Nietzsche
--
DENX Software Engineering GmbH,  MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de
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Re: [U-Boot] U-Boot Mini Summit

[Detlev Zundel]

Hello Masahiro-san,

[...]

 Perhaps, is it better to insert 5-minute break between talks?
 Speakers might need to get something prepared. (connecting their
 laptop to the beamer, etc.)

Of course.  I did not explicitely include this in the agenda, but such a
5 minute break is what I'll strive to maintain.

Bets wishes
  Detlev
  
-- 
A change in language can transform our appreciation of the cosmos
   -- Benjamin Lee Whorf
--
DENX Software Engineering GmbH,  MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de
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Re: [U-Boot] [PATCH V5] ARM: mx6: Add support for Kosagi Novena

[Sean Cross]

On 07/10/2014 00:02, Marek Vasut wrote:
 Add support for the Kosagi Novena board. Currently supported are:
 - I2C busses
 - FEC Ethernet
 - MMC0, MMC1, Booting from MMC
 - SATA
 - USB ports
 - USB Ethernet

This patch looks good.  It resets the FPGA, muxes the correct UART
lines, and detects USB devices.  It doesn't have the newer FEC reset
sequence, but is the idea for Nikolay to submit that separately in order
to get credit for it?


Sean

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[U-Boot] [PATCH] checkpatch: Add a check for forbidden tags in the git log

[Alban Bedel]

After doing this error too many times myself add a check for left
over tags from gerrit and co.

Signed-off-by: Alban Bedel alban.be...@avionic-design.de
---
 scripts/checkpatch.pl | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 74db2e2..3f1dedf 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -351,6 +351,15 @@ our $signature_tags = qr{(?xi:
Cc:
 )};
 
+our $forbidden_tags = qr{(?xi:
+   Bug[=:]|
+   Test[=:]|
+   Issue:|
+   Change-Id:|
+   Review URL:|
+   Reviewed-On:
+)};
+
 our @typeList = (
qr{void},
qr{(?:unsigned\s+)?char},
@@ -1894,6 +1903,12 @@ sub process {
}
}
 
+# Check for left over tags
+   if ($line =~ /^\s*$forbidden_tags/i) {
+   WARN(FORBIDDEN_TAGS,
+Do not leave extra tags (internal review marker, 
etc)\n . $herecurr)
+   }
+
 # Check for wrappage within a valid hunk of the file
if ($realcnt != 0  $line !~ m{^(?:\+|-| |\\ No newline|$)}) {
ERROR(CORRUPTED_PATCH,
-- 
2.1.1

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[U-Boot] [PATCH][v2] ls102x: configs - Add hash command in freescale LS1 platforms

[Ruchika Gupta]

Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
---
Changes in v2
Warning fixed for ls1021atwr build

 arch/arm/include/asm/arch-ls102xa/config.h |  8 
 arch/arm/include/asm/arch-ls102xa/config.h.rej | 19 +++
 board/freescale/ls1021aqds/ls1021aqds.c| 10 ++
 board/freescale/ls1021atwr/ls1021atwr.c| 10 ++
 include/configs/ls1021aqds.h   |  6 ++
 include/configs/ls1021atwr.h   |  6 ++
 6 files changed, 59 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h.rej

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index a500b5b..588f37b 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -20,6 +20,8 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0056)
 #define CONFIG_SYS_FSL_SCFG_ADDR   (CONFIG_SYS_IMMR + 0x0057)
 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea)
+#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 
0x70)
+#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 
0x71)
 #define CONFIG_SYS_FSL_GUTS_ADDR   (CONFIG_SYS_IMMR + 0x00ee)
 #define CONFIG_SYS_FSL_LS1_CLK_ADDR(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR + 
0x011c0500)
@@ -66,6 +68,7 @@
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
 #define CONFIG_SYS_FSL_DCU_BE
+#define CONFIG_SYS_FSL_SEC_LE
 
 #define DCU_LAYER_MAX_NUM  16
 
@@ -76,8 +79,13 @@
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_NUM_DDR_CONTROLLERS 1
 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_SEC_COMPAT  5
 #else
 #error SoC not defined
 #endif
 
+#if CONFIG_SYS_FSL_SEC_COMPAT = 4
+#define CONFIG_FSL_CAAM
+#endif
+
 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h.rej 
b/arch/arm/include/asm/arch-ls102xa/config.h.rej
new file mode 100644
index 000..00e587e
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/config.h.rej
@@ -0,0 +1,19 @@
+--- arch/arm/include/asm/arch-ls102xa/config.h
 arch/arm/include/asm/arch-ls102xa/config.h
+@@ -73,8 +75,16 @@
+ #define CONFIG_MAX_CPUS   2
+ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+ #define CONFIG_NUM_DDR_CONTROLLERS1
++#define CONFIG_SYS_FSL_SEC_OFFSET 0x0070
++#define CONFIG_SYS_FSL_SEC_COMPAT 5
+ #else
+ #error SoC not defined
+ #endif
+
++#define CONFIG_SYS_FSL_SEC_LE
++
++#if CONFIG_SYS_FSL_SEC_COMPAT = 4
++#define CONFIG_FSL_CAAM
++#endif
++
+ #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f7..d6278b9 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -13,6 +13,7 @@
 #include mmc.h
 #include fsl_esdhc.h
 #include fsl_ifc.h
+#include fsl_sec.h
 
 #include ../common/qixis.h
 #include ls1021aqds_qixis.h
@@ -213,6 +214,15 @@ int config_serdes_mux(void)
return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+   if (sec_init()  0)
+   return -1;
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c 
b/board/freescale/ls1021atwr/ls1021atwr.c
index b522ff2..469b502 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -16,6 +16,7 @@
 #include netdev.h
 #include fsl_mdio.h
 #include tsec.h
+#include fsl_sec.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -280,6 +281,15 @@ int board_init(void)
return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+   if (sec_init()  0)
+   return -1;
+   return 0;
+}
+#endif
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
ft_cpu_setup(blob, bd);
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..e1ca78a 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -388,4 +388,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMD_BOOTZ
 
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272..7199c92 100644
--- 

Re: [U-Boot] [PATCH V5] ARM: mx6: Add support for Kosagi Novena

[Marek Vasut]

On Tuesday, October 07, 2014 at 11:52:33 AM, Sean Cross wrote:
 On 07/10/2014 00:02, Marek Vasut wrote:
  Add support for the Kosagi Novena board. Currently supported are:
  - I2C busses
  - FEC Ethernet
  - MMC0, MMC1, Booting from MMC
  - SATA
  - USB ports
  - USB Ethernet
 
 This patch looks good.  It resets the FPGA, muxes the correct UART
 lines, and detects USB devices.  It doesn't have the newer FEC reset
 sequence, but is the idea for Nikolay to submit that separately in order
 to get credit for it?

I would be happy to do it that way, what do you think ?

Best regards,
Marek Vasut
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Re: [U-Boot] Pull request: u-boot-uniphier/master

[Albert ARIBAUD]

Hi Masahiro,

On Sun, 5 Oct 2014 14:32:12 +0900, Masahiro YAMADA
yamad...@jp.panasonic.com wrote:

 Hi Albert,
 
 
 The following changes since commit be9f643ae6aa9044c60fe80e3a2c10be8371c692:
 
   Merge branch 'for-tom' of git://git.denx.de/u-boot-dm (2014-09-26
 20:10:48 -0400)
 
 are available in the git repository at:
 
 
   git://git.denx.de/u-boot-uniphier.git master
 
 for you to fetch changes up to 6dd0e7c00bfa5ce861a72b8e4a3ef9e787306125:
 
   git-mailrc: add me as a maintainer of UniPhier platform (2014-10-05
 14:10:09 +0900)
 
 
 Masahiro Yamada (7):
   mtd: denali: add Denali controller configs to Kconfig
   mtd: denali: add Denali NAND driver for SPL
   serial: add UniPhier serial driver
   ARM: UniPhier: add UniPhier SoC support code
   ARM: UniPhier: add Kconfig and defconfig
   MAINTAINERS: add me as a maintainer of UniPhier platform
   git-mailrc: add me as a maintainer of UniPhier platform
 
  MAINTAINERS   |9 +
  arch/arm/Kconfig  |5 +
  arch/arm/cpu/armv7/uniphier/Kconfig   |   32 ++
  arch/arm/cpu/armv7/uniphier/Makefile  |   23 ++
  arch/arm/cpu/armv7/uniphier/board_common.c|   32 ++
  arch/arm/cpu/armv7/uniphier/board_late_init.c |   91 +
  arch/arm/cpu/armv7/uniphier/cache_uniphier.c  |  154 
  arch/arm/cpu/armv7/uniphier/cmd_pinmon.c  |   33 ++
  arch/arm/cpu/armv7/uniphier/cpu_info.c|   59 +++
  arch/arm/cpu/armv7/uniphier/dram_init.c   |   37 ++
  arch/arm/cpu/armv7/uniphier/init_page_table.c | 1068
 +
  arch/arm/cpu/armv7/uniphier/lowlevel_init.S   |  159 
  arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile  |   10 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c|   33 ++
  arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c  |   16 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c  |   42 +++
  arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c   |1 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c |   29 ++
  arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c |   63 
  arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c|  189 ++
  arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c|1 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c|   44 +++
  arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c |   28 ++
  arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c|  162 
  arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile |   10 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c |   16 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c |   39 ++
  arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c  |   66 
  arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c|   29 ++
  arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c|   45 +++
  arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c   |  168 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c   |   18 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c   |   75 
  arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c|   28 ++
  arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c   |  136 +++
  arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile |   10 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c   |1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c |   16 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c |1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c  |1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c|   29 ++
  arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c|   57 +++
  arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c   |  201 ++
  arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c   |1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c   |   51 +++
  arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c|1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c   |  142 +++
  arch/arm/cpu/armv7/uniphier/reset.c   |   29 ++
  arch/arm/cpu/armv7/uniphier/smp.S |   54 +++
  arch/arm/cpu/armv7/uniphier/spl.c |   17 +
  arch/arm/cpu/armv7/uniphier/support_card.c|  180 +
  arch/arm/cpu/armv7/uniphier/timer.c   |   39 ++
  arch/arm/include/asm/arch-uniphier/arm-mpcore.h   |   46 +++
  arch/arm/include/asm/arch-uniphier/bcu-regs.h |   30 ++
  arch/arm/include/asm/arch-uniphier/board.h|   35 ++
  

[U-Boot] [PATCH][v2] ls102x: configs - Add hash command in freescale LS1 platforms

[Ruchika Gupta]

Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
---
Changes from v1:
Rebased to HEAD of uboot
Compilation warning fixed in ls1021atwr build

 arch/arm/include/asm/arch-ls102xa/config.h |  8 
 board/freescale/ls1021aqds/ls1021aqds.c| 10 ++
 board/freescale/ls1021atwr/ls1021atwr.c| 10 ++
 include/configs/ls1021aqds.h   |  6 ++
 include/configs/ls1021atwr.h   |  6 ++
 5 files changed, 40 insertions(+)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index a500b5b..588f37b 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -20,6 +20,8 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0056)
 #define CONFIG_SYS_FSL_SCFG_ADDR   (CONFIG_SYS_IMMR + 0x0057)
 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea)
+#define CONFIG_SYS_FSL_SEC_ADDR(CONFIG_SYS_IMMR + 
0x70)
+#define CONFIG_SYS_FSL_JR0_ADDR(CONFIG_SYS_IMMR + 
0x71)
 #define CONFIG_SYS_FSL_GUTS_ADDR   (CONFIG_SYS_IMMR + 0x00ee)
 #define CONFIG_SYS_FSL_LS1_CLK_ADDR(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR + 
0x011c0500)
@@ -66,6 +68,7 @@
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
 #define CONFIG_SYS_FSL_DCU_BE
+#define CONFIG_SYS_FSL_SEC_LE
 
 #define DCU_LAYER_MAX_NUM  16
 
@@ -76,8 +79,13 @@
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_NUM_DDR_CONTROLLERS 1
 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_SEC_COMPAT  5
 #else
 #error SoC not defined
 #endif
 
+#if CONFIG_SYS_FSL_SEC_COMPAT = 4
+#define CONFIG_FSL_CAAM
+#endif
+
 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f7..d6278b9 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -13,6 +13,7 @@
 #include mmc.h
 #include fsl_esdhc.h
 #include fsl_ifc.h
+#include fsl_sec.h
 
 #include ../common/qixis.h
 #include ls1021aqds_qixis.h
@@ -213,6 +214,15 @@ int config_serdes_mux(void)
return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+   if (sec_init()  0)
+   return -1;
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c 
b/board/freescale/ls1021atwr/ls1021atwr.c
index b522ff2..469b502 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -16,6 +16,7 @@
 #include netdev.h
 #include fsl_mdio.h
 #include tsec.h
+#include fsl_sec.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -280,6 +281,15 @@ int board_init(void)
return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+   if (sec_init()  0)
+   return -1;
+   return 0;
+}
+#endif
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
ft_cpu_setup(blob, bd);
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..e1ca78a 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -388,4 +388,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMD_BOOTZ
 
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272..7199c92 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -288,4 +288,10 @@
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMD_BOOTZ
 
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
 #endif
-- 
1.8.1.4

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[U-Boot] [PATCH 3/3] ls102x: Add support for secure boot and enable blob command

[Ruchika Gupta]

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
---
Changes from v3
Added new defconfigs in MAINTAINERS

 board/freescale/ls1021aqds/MAINTAINERS   | 1 +
 board/freescale/ls1021atwr/MAINTAINERS   | 1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 3 +++
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 3 +++
 include/configs/ls1021aqds.h | 4 
 include/configs/ls1021atwr.h | 4 
 6 files changed, 16 insertions(+)
 create mode 100644 configs/ls1021aqds_nor_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1021atwr_nor_SECURE_BOOT_defconfig

diff --git a/board/freescale/ls1021aqds/MAINTAINERS 
b/board/freescale/ls1021aqds/MAINTAINERS
index ccf4513..e30e944 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -5,3 +5,4 @@ F:  board/freescale/ls1021aqds/
 F: include/configs/ls1021aqds.h
 F: configs/ls1021aqds_nor_defconfig
 F: configs/ls1021aqds_ddr4_nor_defconfig
+F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1021atwr/MAINTAINERS 
b/board/freescale/ls1021atwr/MAINTAINERS
index 4e5bc15..8def0e5 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -4,3 +4,4 @@ S:  Maintained
 F: board/freescale/ls1021atwr/
 F: include/configs/ls1021atwr.h
 F: configs/ls1021atwr_nor_defconfig
+F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig 
b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
new file mode 100644
index 000..2b47995
--- /dev/null
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS=SECURE_BOOT
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig 
b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
new file mode 100644
index 000..eeeb0d5
--- /dev/null
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS=SECURE_BOOT
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index e1ca78a..f71bbce 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -394,4 +394,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_HASH
 #define CONFIG_SHA_HW_ACCEL
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 7199c92..8a78d22 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -294,4 +294,8 @@
 #define CONFIG_CMD_HASH
 #define CONFIG_SHA_HW_ACCEL
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif
-- 
1.8.1.4

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[U-Boot] [PATCH 2/3] mpc85xx: configs - Enable blob command in freescale platforms

[Ruchika Gupta]

Enable blob commands for platforms having SEC 4.0 or greater
for secure boot scenarios

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
---
Changes from v3
No changes

 include/configs/B4860QDS.h   | 4 
 include/configs/BSC9132QDS.h | 4 
 include/configs/P1010RDB.h   | 4 
 include/configs/P2041RDB.h   | 4 
 include/configs/T1040QDS.h   | 1 +
 include/configs/T104xRDB.h   | 1 +
 include/configs/T208xQDS.h   | 1 +
 include/configs/T208xRDB.h   | 1 +
 include/configs/T4240QDS.h   | 4 
 include/configs/T4240RDB.h   | 1 +
 include/configs/corenet_ds.h | 4 
 11 files changed, 29 insertions(+)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2bf8ca0..c9fd2bb 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -917,4 +917,8 @@ unsigned long get_board_ddr_clk(void);
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 922ac00..32fc099 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -708,4 +708,8 @@ combinations. this should be removed later
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 1fa858e..7039da4 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -960,4 +960,8 @@ extern unsigned long get_sdram_size(void);
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 7ff2dd5..0b12cf5 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -747,4 +747,8 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 5870a49..bbe54bf 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -822,6 +822,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include asm/fsl_secure_boot.h
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index b21eb3a..0c90040 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -869,6 +869,7 @@
 
 #ifdef CONFIG_SECURE_BOOT
 #include asm/fsl_secure_boot.h
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 9a8a3b6..f40ad9a 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -913,6 +913,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include asm/fsl_secure_boot.h
+#define CONFIG_CMD_BLOB
 #undef CONFIG_CMD_USB
 #endif
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 4ff31e6..8d4b02f 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -872,6 +872,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include asm/fsl_secure_boot.h
+#define CONFIG_CMD_BLOB
 #undef CONFIG_CMD_USB
 #endif
 
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index d2faf94..e3bbfeb 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -629,4 +629,8 @@ unsigned long get_board_ddr_clk(void);
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index b3fbbe3..82e5efd 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -755,6 +755,7 @@ unsigned long get_board_ddr_clk(void);
  * which is anyways not used in Secure Environment.
  */
 #undef CONFIG_CMD_USB
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 4fd290e..b0c8277 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -749,4 +749,8 @@
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.8.1.4

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[U-Boot] [PATCH 1/3][v4] crypto/fsl: Add command for encapsulating/decapsulating blobs

[Ruchika Gupta]

Freescale's SEC block has built-in Blob Protocol which provides
a method for protecting user-defined data across system power
cycles. SEC block protects data in a data structure called a Blob,
which provides both confidentiality and integrity protection.

Encapsulating data as a blob
Each time that the Blob Protocol is used to protect data, a
different randomly generated key is used to encrypt the data.
This random key is itself encrypted using a key which is derived
from SoC's non volatile secret key and a 16 bit Key identifier.
The resulting encrypted key along with encrypted data is called a blob.
The non volatile secure key is available for use only during secure boot.

During decapsulation, the reverse process is performed to get back
the original data.

Commands added
--
blob enc - encapsulating data as a cryptgraphic blob
blob dec - decapsulating cryptgraphic blob to get the data

Commands Syntax
---
blob enc src dst len km

Encapsulate and create blob of data $len bytes long
at address $src and store the result at address $dst.
$km is the 16 byte key modifier is also required for
generation/use as key for cryptographic operation. Key
modifier should be 16 byte long.

blob dec src dst len km

Decapsulate the  blob of data at address $src and
store result of $len byte at addr $dst.
$km is the 16 byte key modifier is also required for
generation/use as key for cryptographic operation. Key
modifier should be 16 byte long.

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
---
Changes from v3
No changes

 common/Makefile   |   2 +
 common/cmd_blob.c | 109 
 drivers/crypto/fsl/Makefile   |   1 +
 drivers/crypto/fsl/fsl_blob.c |  61 
 drivers/crypto/fsl/jobdesc.c  |  80 ++
 drivers/crypto/fsl/jobdesc.h  |  11 
 drivers/crypto/fsl/jr.c   | 127 +-
 include/fsl_sec.h |  34 ++-
 8 files changed, 423 insertions(+), 2 deletions(-)
 create mode 100644 common/cmd_blob.c
 create mode 100644 drivers/crypto/fsl/fsl_blob.c

diff --git a/common/Makefile b/common/Makefile
index b19d379..c84b3bc 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -265,4 +265,6 @@ obj-y += aboot.o
 obj-y += fb_mmc.o
 endif
 
+obj-$(CONFIG_CMD_BLOB) += cmd_blob.o
+
 CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 
2/dev/null)
diff --git a/common/cmd_blob.c b/common/cmd_blob.c
new file mode 100644
index 000..82ecaf0
--- /dev/null
+++ b/common/cmd_blob.c
@@ -0,0 +1,109 @@
+/*
+ *
+ * Command for encapsulating/decapsulating blob of memory.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+#include environment.h
+#include malloc.h
+#include asm/byteorder.h
+#include linux/compiler.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * blob_decap() - Decapsulate the data as a blob
+ * @key_mod:   - Pointer to key modifier/key
+ * @src:   - Address of data to be decapsulated
+ * @dst:   - Address of data to be decapsulated
+ * @len:   - Size of data to be decapsulated
+ *
+ * Returns zero on success,and negative on error.
+ */
+__weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+{
+   return 0;
+}
+
+/**
+ * blob_encap() - Encapsulate the data as a blob
+ * @key_mod:   - Pointer to key modifier/key
+ * @src:   - Address of data to be encapsulated
+ * @dst:   - Address of data to be encapsulated
+ * @len:   - Size of data to be encapsulated
+ *
+ * Returns zero on success,and negative on error.
+ */
+__weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+{
+   return 0;
+}
+
+/**
+ * do_blob() - Handle the blob command-line command
+ * @cmdtp: Command data struct pointer
+ * @flag:  Command flag
+ * @argc:  Command-line argument count
+ * @argv:  Array of command-line arguments
+ *
+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
+ * on error.
+ */
+static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+   uint32_t key_addr, src_addr, dst_addr, len;
+   uint8_t *km_ptr, *src_ptr, *dst_ptr;
+   int enc, ret = 0;
+
+   if (argc != 6)
+   return CMD_RET_USAGE;
+
+   if (!strncmp(argv[1], enc, 3))
+   enc = 1;
+   else if (!strncmp(argv[1], dec, 3))
+   enc = 0;
+   else
+   return CMD_RET_USAGE;
+
+   src_addr = simple_strtoul(argv[2], NULL, 16);
+   dst_addr = simple_strtoul(argv[3], NULL, 16);
+   len = simple_strtoul(argv[4], NULL, 16);
+   key_addr = simple_strtoul(argv[5], NULL, 16);
+
+   km_ptr = (uint8_t *)key_addr;
+   src_ptr = (uint8_t *)src_addr;
+   dst_ptr = (uint8_t *)dst_addr;
+
+   if (enc)
+   ret = blob_encap(km_ptr, src_ptr, dst_ptr, 

[U-Boot] [PATCH 3/3][v4] ls102x: Add support for secure boot and enable blob command

[Ruchika Gupta]

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
---
Changes from v3
Added new defconfigs in MAINTAINERS

 board/freescale/ls1021aqds/MAINTAINERS   | 1 +
 board/freescale/ls1021atwr/MAINTAINERS   | 1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 3 +++
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 3 +++
 include/configs/ls1021aqds.h | 4 
 include/configs/ls1021atwr.h | 4 
 6 files changed, 16 insertions(+)
 create mode 100644 configs/ls1021aqds_nor_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1021atwr_nor_SECURE_BOOT_defconfig

diff --git a/board/freescale/ls1021aqds/MAINTAINERS 
b/board/freescale/ls1021aqds/MAINTAINERS
index ccf4513..e30e944 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -5,3 +5,4 @@ F:  board/freescale/ls1021aqds/
 F: include/configs/ls1021aqds.h
 F: configs/ls1021aqds_nor_defconfig
 F: configs/ls1021aqds_ddr4_nor_defconfig
+F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1021atwr/MAINTAINERS 
b/board/freescale/ls1021atwr/MAINTAINERS
index 4e5bc15..8def0e5 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -4,3 +4,4 @@ S:  Maintained
 F: board/freescale/ls1021atwr/
 F: include/configs/ls1021atwr.h
 F: configs/ls1021atwr_nor_defconfig
+F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig 
b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
new file mode 100644
index 000..2b47995
--- /dev/null
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS=SECURE_BOOT
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig 
b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
new file mode 100644
index 000..eeeb0d5
--- /dev/null
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS=SECURE_BOOT
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index e1ca78a..f71bbce 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -394,4 +394,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_HASH
 #define CONFIG_SHA_HW_ACCEL
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 7199c92..8a78d22 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -294,4 +294,8 @@
 #define CONFIG_CMD_HASH
 #define CONFIG_SHA_HW_ACCEL
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif
-- 
1.8.1.4

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[U-Boot] [PATCH 2/3][v4] mpc85xx: configs - Enable blob command in freescale platforms

[Ruchika Gupta]

Enable blob commands for platforms having SEC 4.0 or greater
for secure boot scenarios

Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
---
Changes from v3
No changes

 include/configs/B4860QDS.h   | 4 
 include/configs/BSC9132QDS.h | 4 
 include/configs/P1010RDB.h   | 4 
 include/configs/P2041RDB.h   | 4 
 include/configs/T1040QDS.h   | 1 +
 include/configs/T104xRDB.h   | 1 +
 include/configs/T208xQDS.h   | 1 +
 include/configs/T208xRDB.h   | 1 +
 include/configs/T4240QDS.h   | 4 
 include/configs/T4240RDB.h   | 1 +
 include/configs/corenet_ds.h | 4 
 11 files changed, 29 insertions(+)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2bf8ca0..c9fd2bb 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -917,4 +917,8 @@ unsigned long get_board_ddr_clk(void);
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 922ac00..32fc099 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -708,4 +708,8 @@ combinations. this should be removed later
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 1fa858e..7039da4 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -960,4 +960,8 @@ extern unsigned long get_sdram_size(void);
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 7ff2dd5..0b12cf5 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -747,4 +747,8 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 5870a49..bbe54bf 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -822,6 +822,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include asm/fsl_secure_boot.h
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index b21eb3a..0c90040 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -869,6 +869,7 @@
 
 #ifdef CONFIG_SECURE_BOOT
 #include asm/fsl_secure_boot.h
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 9a8a3b6..f40ad9a 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -913,6 +913,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include asm/fsl_secure_boot.h
+#define CONFIG_CMD_BLOB
 #undef CONFIG_CMD_USB
 #endif
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 4ff31e6..8d4b02f 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -872,6 +872,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include asm/fsl_secure_boot.h
+#define CONFIG_CMD_BLOB
 #undef CONFIG_CMD_USB
 #endif
 
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index d2faf94..e3bbfeb 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -629,4 +629,8 @@ unsigned long get_board_ddr_clk(void);
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index b3fbbe3..82e5efd 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -755,6 +755,7 @@ unsigned long get_board_ddr_clk(void);
  * which is anyways not used in Secure Environment.
  */
 #undef CONFIG_CMD_USB
+#define CONFIG_CMD_BLOB
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 4fd290e..b0c8277 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -749,4 +749,8 @@
 
 #include asm/fsl_secure_boot.h
 
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.8.1.4

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Re: [U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings

[Albert ARIBAUD]

Hi Stefan,

On Sat,  6 Sep 2014 19:47:06 +0200, Stefan Agner ste...@agner.ch
wrote:

 From: Anthony Felice tony.fel...@timesys.com
 
 Removed settings in unsupported register fields. They didn’t
 do anything, and in most cases, were not documented in the
 reference manual.
 
 Changed register settings to comply with JEDEC required values.
 
 Changed timing parameters because they included full clock
 periods that were doing nothing.
 
 Signed-off-by: Anthony Felice tony.fel...@timesys.com
 [rebased on v2014.10-rc2]
 Signed-off-by: Stefan Agner ste...@agner.ch
 ---
 As discuessed in the initial patch set this fixes a lot of wrong/
 undocummented access and it would be nice to have in the next U-Boot
 release. Verified the patchset after rebase again using memtester
 on Vybrid Tower.
 
  arch/arm/include/asm/arch-vf610/imx-regs.h| 49 +++---
  arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++--
  arch/arm/include/asm/imx-common/iomux-v3.h|  2 +
  board/freescale/vf610twr/vf610twr.c   | 94 
 +--
  4 files changed, 127 insertions(+), 62 deletions(-)
 
 diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h 
 b/arch/arm/include/asm/arch-vf610/imx-regs.h
 index bb00217..9d797db 100644
 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h
 +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
 @@ -103,9 +103,11 @@
  /* DDRMC */
  #define DDRMC_PHY_DQ_TIMING  0x2613
  #define DDRMC_PHY_DQS_TIMING 0x2615
 -#define DDRMC_PHY_CTRL   0x01210080
 +#define DDRMC_PHY_CTRL   0x0021
  #define DDRMC_PHY_MASTER_CTRL0x0001012a
 -#define DDRMC_PHY_SLAVE_CTRL 0x00012020
 +#define DDRMC_PHY_SLAVE_CTRL 0x2000
 +#define DDRMC_PHY_OFF0x
 +#define DDRMC_PHY_PROC_PAD_ODT   0x00010101
  
  #define DDRMC_PHY50_DDR3_MODE(1  12)
  #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1  8)
 @@ -138,7 +140,7 @@
  #define DDRMC_CR21_CCMAP_EN  1
  #define DDRMC_CR22_TDAL(v)   (((v)  0x3f)  16)
  #define DDRMC_CR23_BSTLEN(v) (((v)  0x7)  24)
 -#define DDRMC_CR23_TDLL(v)   ((v)  0xff)
 +#define DDRMC_CR23_TDLL(v)   ((v)  0x)
  #define DDRMC_CR24_TRP_AB(v) ((v)  0x1f)
  #define DDRMC_CR25_TREF_EN   (1  16)
  #define DDRMC_CR26_TREF(v)   (((v)  0x)  16)
 @@ -151,7 +153,7 @@
  #define DDRMC_CR33_EN_QK_SREF(1  16)
  #define DDRMC_CR34_CKSRX(v)  (((v)  0xf)  16)
  #define DDRMC_CR34_CKSRE(v)  (((v)  0xf)  8)
 -#define DDRMC_CR38_FREQ_CHG_EN   (1  8)
 +#define DDRMC_CR38_FREQ_CHG_EN(v)(((v)  0x1)  8)
  #define DDRMC_CR39_PHY_INI_COM(v)(((v)  0x)  16)
  #define DDRMC_CR39_PHY_INI_STA(v)(((v)  0xff)  8)
  #define DDRMC_CR39_FRQ_CH_DLLOFF(v)  ((v)  0x3)
 @@ -163,7 +165,7 @@
  #define DDRMC_CR67_ZQCS(v)   ((v)  0xfff)
  #define DDRMC_CR69_ZQ_ON_SREF_EX(v)  (((v)  0xf)  8)
  #define DDRMC_CR70_REF_PER_ZQ(v) (v)
 -#define DDRMC_CR72_ZQCS_ROTATE   (1  24)
 +#define DDRMC_CR72_ZQCS_ROTATE(v)(((v)  0x1)  24)
  #define DDRMC_CR73_APREBIT(v)(((v)  0xf)  
 24)
  #define DDRMC_CR73_COL_DIFF(v)   (((v)  0x7)  
 16)
  #define DDRMC_CR73_ROW_DIFF(v)   (((v)  0x3)  
 8)
 @@ -182,9 +184,10 @@
  #define DDRMC_CR77_CS_MAP(1  24)
  #define DDRMC_CR77_DI_RD_INTLEAVE(1  8)
  #define DDRMC_CR77_SWAP_EN   1
 +#define DDRMC_CR78_Q_FULLNESS(v) (((v)  0x7)  24)
  #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v)  0xf)
 -#define DDRMC_CR79_CTLUPD_AREF   (1  24)
 -#define DDRMC_CR82_INT_MASK  0x1fff
 +#define DDRMC_CR79_CTLUPD_AREF(v)(((v)  0x1)  24)
 +#define DDRMC_CR82_INT_MASK  0x1000
  #define DDRMC_CR87_ODT_WR_MAPCS0 (1  24)
  #define DDRMC_CR87_ODT_RD_MAPCS0 (1  16)
  #define DDRMC_CR88_TODTL_CMD(v)  (((v)  0x1f) 
  16)
 @@ -192,9 +195,17 @@
  #define DDRMC_CR91_R2W_SMCSDL(v) (((v)  0x7)  16)
  #define DDRMC_CR96_WLMRD(v)  (((v)  0x3f)  8)
  #define DDRMC_CR96_WLDQSEN(v)((v)  0x3f)
 

[U-Boot] Pull request: u-boot-arm/master

[Albert ARIBAUD]

Hi Tom,

The following changes since commit
be9f643ae6aa9044c60fe80e3a2c10be8371c692:

  Merge branch 'for-tom' of git://git.denx.de/u-boot-dm (2014-09-26
  20:10:48 -0400)

are available in the git repository at:


  git://git.denx.de/u-boot-arm master

for you to fetch changes up to c19a8bc5711ec63e905ef91f045a1489f0aa3cb0:

  vf610twr: Tune DDR initialization settings (2014-10-07 13:08:31 +0200)


Albert ARIBAUD (1):
  Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master'

Anthony Felice (1):
  vf610twr: Tune DDR initialization settings

DrEagle (5):
  ARM: sheevaplug: change env location
  ARM: sheevaplug: add MVSATA driver
  ARM: sheevaplug: add MTD defaults
  ARM: sheevaplug: redefine MTDPARTS
  ARM: sheevaplug: add HUSH parser

Masahiro Yamada (7):
  mtd: denali: add Denali controller configs to Kconfig
  mtd: denali: add Denali NAND driver for SPL
  serial: add UniPhier serial driver
  ARM: UniPhier: add UniPhier SoC support code
  ARM: UniPhier: add Kconfig and defconfig
  MAINTAINERS: add me as a maintainer of UniPhier platform
  git-mailrc: add me as a maintainer of UniPhier platform

Michael Walle (1):
  lsxl: convert to generic board and fix typo

 MAINTAINERS|9 +
 arch/arm/Kconfig   |5 +
 arch/arm/cpu/armv7/uniphier/Kconfig|   32 +
 arch/arm/cpu/armv7/uniphier/Makefile   |   23 +
 arch/arm/cpu/armv7/uniphier/board_common.c |   32 +
 arch/arm/cpu/armv7/uniphier/board_late_init.c  |   91 ++
 arch/arm/cpu/armv7/uniphier/cache_uniphier.c   |  154 +++
 arch/arm/cpu/armv7/uniphier/cmd_pinmon.c   |   33 +
 arch/arm/cpu/armv7/uniphier/cpu_info.c |   59 ++
 arch/arm/cpu/armv7/uniphier/dram_init.c|   37 +
 arch/arm/cpu/armv7/uniphier/init_page_table.c  | 1068
 
 arch/arm/cpu/armv7/uniphier/lowlevel_init.S|  159 +++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile   |   10 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c |   33 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c   |   16
 + .../armv7/uniphier/ph1-ld4/board_postclk_init.c|   42 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c|1 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c  |   29 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c  |   63 ++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c |  189 
 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c |1 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c |   44 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c  |   28 +
 arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c |  162 +++
 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile  |   10 +
 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c  |   16
 + .../armv7/uniphier/ph1-pro4/board_postclk_init.c   |   39 +
 arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c   |   66 ++
 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c |   29 +
 arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c |   45 +
 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c|  168
 +++ .../arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c |   18 +
 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c|   75 ++
 arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c |   28 +
 arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c|  136 +++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile  |   10 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c|1 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c  |   16
 + .../armv7/uniphier/ph1-sld8/board_postclk_init.c   |1 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c   |1 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c |   29 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c |   57 ++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c|  201
  .../arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c |1 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c|   51 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c |1 +
 arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c|  142 +++
 arch/arm/cpu/armv7/uniphier/reset.c|   29 +
 arch/arm/cpu/armv7/uniphier/smp.S  |   54 +
 arch/arm/cpu/armv7/uniphier/spl.c  |   17 +
 arch/arm/cpu/armv7/uniphier/support_card.c |  180 
 arch/arm/cpu/armv7/uniphier/timer.c|   39 +
 arch/arm/include/asm/arch-uniphier/arm-mpcore.h|   46 +
 arch/arm/include/asm/arch-uniphier/bcu-regs.h  |   30 +
 arch/arm/include/asm/arch-uniphier/board.h |   35 +
 arch/arm/include/asm/arch-uniphier/boot-device.h   |   20 +
 arch/arm/include/asm/arch-uniphier/led.h   |  101 ++
 arch/arm/include/asm/arch-uniphier/sbc-regs.h  |  108 ++
 arch/arm/include/asm/arch-uniphier/sc-regs.h   |   62 ++
 

Re: [U-Boot] [PATCH v5 0/15] samsung: Use common config files with Samsung boards

[Minkyu Kang]

Dear Simon Glass,

On 06/10/14 03:39, Simon Glass wrote:
 Hi Minkyu,
 
 On 1 October 2014 21:44, Simon Glass s...@chromium.org wrote:
 Hi Minkyu,

 On 1 October 2014 21:43, Simon Glass s...@chromium.org wrote:
 This series tries to unify the Samsung board configs into a few header
 files for exynos5 and exynos4.

 The purpose is to make it easier to move to driver model. In that case
 I would like things like the GPIO drivers and serial drivers to work in
 a standard way, and not need to support device tree and platform data at
 the same time. That would be quite painful.

 Another reason is that the Chrome OS EC drivers are currently included in
 boards that don't have a Chrome OS EC. This concern was raised by the
 Samsung maintainer (Minkyu) a while back.

 There are still a few boards that don't use CONFIG_OF_CONTROL so I have
 updated these rudimentary of device tree files based on feedback.

 This series has the side-effect of getting the EC interface working
 properly on Pit, so the keyboard works. It also provides access to the
 TPS65090 PMIC, which means that the backlight is enabled.

 Changes in v5:
 - Rebase on top of samsung/master

 Please check this and see if it works for what you need.

 I suppose the merge will be Albert's problem, but I will do a patch
 once I know the detla.
 
 Actually I see that Albert has pulled this in. So v4 should work for
 you now. I just tried applying it on u-boot-arm/master and it worked
 OK.
 
 Regards,
 Simon
 

Hm, I tried to apply. but failed..

Applying: Exynos: Use 900MHz ARM frequency in SPL for peach_pit
Applying: exynos5: Enable data cache
Applying: cros_ec: power: Add a tunnelled version of the tps65090 driver
Applying: cros_ec: exynos: Use the correct tps65090 driver in each case
Applying: dm: exynos: Split out the cros_ec drivers
Applying: exynos: dts: Add device tree node for cros_ec keyboard
Applying: exynos: Rename -dt config files to -common
Applying: exynos: Move common exynos settings into a common file
Applying: exynos: Move common smdk5420 things to common file
Applying: exynos: config: Move cros_ec and tps65090 out of smdk boards
Applying: config: Move arndale to use common exynos5250 file
Applying: config: Move smdkv310 to use common exynos4 file
Applying: samsung: Enable device tree for s5p_goni
error: patch failed: arch/arm/Kconfig:547
error: arch/arm/Kconfig: patch does not apply
Patch failed at 0013 samsung: Enable device tree for s5p_goni


Thanks,
Minkyu Kang.
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Re: [U-Boot] [PATCH 2/2] usb: eth: smsc95xx: Add EEPROM access support

[Pavel Machek]

On Tue 2014-10-07 11:19:37, Alban Bedel wrote:
 Use the new ethernet eeprom API to allow the user to read/write the
 EEPROM.
 
 Change-Id: I21233b6ee805a75bd8a03ca12e22c41421b7629c
 Signed-off-by: Alban Bedel alban.be...@avionic-design.de
 ---
  drivers/usb/eth/smsc95xx.c | 199 
 +++--
  1 file changed, 192 insertions(+), 7 deletions(-)
 
 diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
 index 6bca34d..eb29565 100644
 --- a/drivers/usb/eth/smsc95xx.c
 +++ b/drivers/usb/eth/smsc95xx.c
 @@ -59,6 +59,8 @@
  
  #define E2P_CMD  0x30
  #define E2P_CMD_BUSY_0x8000
 +#define E2P_CMD_EWEN_0x2000
 +#define E2P_CMD_WRITE_   0x3000
  #define E2P_CMD_READ_0x
  #define E2P_CMD_TIMEOUT_ 0x0400
  #define E2P_CMD_LOADED_  0x0200
 @@ -146,6 +148,131 @@ struct smsc95xx_private {
   int have_hwaddr;  /* 1 if we have a hardware MAC address */
  };
  
 +#ifdef CONFIG_CMD_ETH_EEPROM

Is this layout common for all machines using this driver? If not, is
it worth comment which machine is it?

 +static u8 eeprom_defaults[] = {
 + /* 0x00 */
 + 0xA5,   /* Signature */
 + 0xFF, 0xFF, /* MAC bytes 0-1 */
 + 0xFF, 0xFF, /* MAC bytes 2-3 */
 + 0xFF, 0xFF, /* MAC bytes 4-5 */

Normally, we use all zeros for unset...?

Best regards,
Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) 
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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[U-Boot] [PATCH] powerpc/BSC9131RDB: Enable creation of dynamic partitions for NAND

[Ashish Kumar]

 * fdt_fixup_mtdparts is called from ft_board_setup
 * Run mtdparts default to create NAND partition on uboot
 * Use mtdparts to create partitions dynamically rather
than using static partitions in device tree

Signed-off-by: Ashish Kumar ashish.ku...@freescale.com
---
 board/freescale/bsc9131rdb/bsc9131rdb.c |   11 +++
 include/configs/BSC9131RDB.h|   17 +
 2 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c 
b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 7fe4ae7..9146f49 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -15,6 +15,9 @@
 #include fdt_support.h
 #include fsl_mdio.h
 #include tsec.h
+#include jffs2/load_kernel.h
+#include mtd_node.h
+#include flash.h
 #include netdev.h
 
 
@@ -50,6 +53,11 @@ int checkboard(void)
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+struct node_info nodes[] = {
+   { fsl,ifc-nand,   MTD_DEV_TYPE_NAND, },
+};
+#endif
 void ft_board_setup(void *blob, bd_t *bd)
 {
phys_addr_t base;
@@ -61,6 +69,9 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
 
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+   fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
 
fdt_fixup_dr_usb(blob, bd);
 }
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 56a3e94..9945dfb 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -393,6 +393,23 @@ extern unsigned long get_sdram_size(void);
 #endif
 
 /*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT nand0=ff80.flash,
+#define MTDPARTS_DEFAULT mtdparts=ff80.flash:1m(uboot), \
+   8m(kernel),512k(dtb),-(fs)
+/*
+ * Override partitions in device tree using info
+ * in mtdparts environment variable
+ */
+#ifdef CONFIG_CMD_MTDPARTS
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#endif
+
+/*
  * Environment Configuration
  */
 
-- 
1.7.6.GIT

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[U-Boot] [SoCFPGA] next steps

[Marek Vasut]

Hey,

given that we now have most of the u-boot socfpga stuff in mainline, I decided 
it would be a good idea to list what we're still missing and we should also 
decide how to move on now.

First thing I should probably clarify is the late acceptance of the socfpga 
patches. This is certainly not something we do regularly and is one of the
worst possible practices to do, but this time it felt rather important to get
the platform in shape, so this exception happened. Furthermore, all of the code
in u-boot-socfpga should be based on u-boot-arm and should be submitted through
the u-boot-arm repository, not directly to u-boot .

As you probably noticed, there is a lot of topic branches in the u-boot-socfpga 
[1] repository, each of them with a date tag. This decision came to be so that
rebasing of a branch can be avoided. I will most likely garbage-collect the old
and useless topic branches at some point, when they become irrelevant due to the
code being merged into u-boot-arm/master (and then to u-boot/master).

I think that's about it for the organization part. Now for the remaining part,
we are still missing a few things. Some of them are ready, some of them, not so
much:

 SPL:  This is something we still miss from mainline. We will need to discuss 
   this thoroughly, but one thing is obvious already -- we need to figure
   out how to interoperate with Quartus resp. the bsp-editor generated 
   header files to assemble the SPL properly.
 USB:  This is scheduled for the next merge window. The DWC2 driver is cleaned
   up and seems to be in rather good state. The USB driver currently resides
   in [2]
 EPCQ: This is something I prepared and tested real quick. The EPCS/EPCQ SPI NOR
   can be operated via the Altera SPI driver, which is currently unused at
   all and thus suffering bitrot. The current cleanup is here [3]
 NET:  Does the SoCDK use EMAC0 or EMAC1 ? I believe we still have this issue
   open, I recall Chin was complaining about this.

You can find the latest combined version of all the patches at [4] to ease up 
your testing.

Please feel free to add into this list, it would be really good to keep track of
what's still open and what's missing.

Thank you!

[1] http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=summary
[2] http://git.denx.de/?p=u-boot/u-boot-
usb.git;a=shortlog;h=refs/heads/topic/dwc2-20140930
[3] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/topic/drivers/spi-20141006
[4] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/topic/arm/socfpga-next-20141007
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Re: [U-Boot] [PATCH 2/2] usb: eth: smsc95xx: Add EEPROM access support

[Alban Bedel]

On Tue, 7 Oct 2014 14:22:09 +0200
Pavel Machek pa...@denx.de wrote:

 On Tue 2014-10-07 11:19:37, Alban Bedel wrote:
  Use the new ethernet eeprom API to allow the user to read/write the
  EEPROM.
  
  Change-Id: I21233b6ee805a75bd8a03ca12e22c41421b7629c
  Signed-off-by: Alban Bedel alban.be...@avionic-design.de
  ---
   drivers/usb/eth/smsc95xx.c | 199 
  +++--
   1 file changed, 192 insertions(+), 7 deletions(-)
  
  diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
  index 6bca34d..eb29565 100644
  --- a/drivers/usb/eth/smsc95xx.c
  +++ b/drivers/usb/eth/smsc95xx.c
  @@ -59,6 +59,8 @@
   
   #define E2P_CMD0x30
   #define E2P_CMD_BUSY_  0x8000
  +#define E2P_CMD_EWEN_  0x2000
  +#define E2P_CMD_WRITE_ 0x3000
   #define E2P_CMD_READ_  0x
   #define E2P_CMD_TIMEOUT_   0x0400
   #define E2P_CMD_LOADED_0x0200
  @@ -146,6 +148,131 @@ struct smsc95xx_private {
  int have_hwaddr;  /* 1 if we have a hardware MAC address */
   };
   
  +#ifdef CONFIG_CMD_ETH_EEPROM
 
 Is this layout common for all machines using this driver? If not, is
 it worth comment which machine is it?

These are supposed to be the same values as would be used by the
controller when the eeprom is not programmed. So they are not machine
specific, however it is specific to the LAN9514, looking at the
datasheet for the LAN9500 the eeprom layout is different.

Then I'll submit a new version that use per chip defaults, as well
as allowing the board file to override the default data.

  +static u8 eeprom_defaults[] = {
  +   /* 0x00 */
  +   0xA5,   /* Signature */
  +   0xFF, 0xFF, /* MAC bytes 0-1 */
  +   0xFF, 0xFF, /* MAC bytes 2-3 */
  +   0xFF, 0xFF, /* MAC bytes 4-5 */
 
 Normally, we use all zeros for unset...?

That's what the controller use when the EEPROM hasn't been programmed,
but I'll change it to all 0.

Alban



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Re: [U-Boot] [PATCH 2/2] usb: eth: smsc95xx: Add EEPROM access support

[Marek Vasut]

On Tuesday, October 07, 2014 at 03:35:40 PM, Alban Bedel wrote:
 On Tue, 7 Oct 2014 14:22:09 +0200
 
 Pavel Machek pa...@denx.de wrote:
  On Tue 2014-10-07 11:19:37, Alban Bedel wrote:
   Use the new ethernet eeprom API to allow the user to read/write the
   EEPROM.
   
   Change-Id: I21233b6ee805a75bd8a03ca12e22c41421b7629c
   Signed-off-by: Alban Bedel alban.be...@avionic-design.de
   ---
   
drivers/usb/eth/smsc95xx.c | 199
+++-- 1 file changed, 192
insertions(+), 7 deletions(-)
   
   diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
   index 6bca34d..eb29565 100644
   --- a/drivers/usb/eth/smsc95xx.c
   +++ b/drivers/usb/eth/smsc95xx.c
   @@ -59,6 +59,8 @@
   
#define E2P_CMD  0x30
#define E2P_CMD_BUSY_0x8000
   
   +#define E2P_CMD_EWEN_0x2000
   +#define E2P_CMD_WRITE_   0x3000
   
#define E2P_CMD_READ_0x
#define E2P_CMD_TIMEOUT_ 0x0400
#define E2P_CMD_LOADED_  0x0200
   
   @@ -146,6 +148,131 @@ struct smsc95xx_private {
   
 int have_hwaddr;  /* 1 if we have a hardware MAC address */

};
   
   +#ifdef CONFIG_CMD_ETH_EEPROM
  
  Is this layout common for all machines using this driver? If not, is
  it worth comment which machine is it?
 
 These are supposed to be the same values as would be used by the
 controller when the eeprom is not programmed. So they are not machine
 specific, however it is specific to the LAN9514, looking at the
 datasheet for the LAN9500 the eeprom layout is different.
 
 Then I'll submit a new version that use per chip defaults, as well
 as allowing the board file to override the default data.
 
   +static u8 eeprom_defaults[] = {
   + /* 0x00 */
   + 0xA5,   /* Signature */
   + 0xFF, 0xFF, /* MAC bytes 0-1 */
   + 0xFF, 0xFF, /* MAC bytes 2-3 */
   + 0xFF, 0xFF, /* MAC bytes 4-5 */
  
  Normally, we use all zeros for unset...?
 
 That's what the controller use when the EEPROM hasn't been programmed,
 but I'll change it to all 0.

Well isn't it better to use these settings as defaults then ?

Best regards,
Marek Vasut
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[U-Boot] [PATCH] sunxi: Increase command line buffer size (CONFIG_SYS_CBSIZE)

[Ian Campbell]

From: Ian Campbell ian.campb...@citrix.com

I was running into this limit with a not overly long PXE append line.

Since the PXE code wants to print the resulting command line increase
CONFIG_SYS_PBSIZE too.

Signed-off-by: Ian Campbell ian.campb...@citrix.com
---
 include/configs/sunxi-common.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1d947d7..d4419a2 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -92,8 +92,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_CMD_ECHO
-#define CONFIG_SYS_CBSIZE  256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE  384 /* Print Buffer Size */
+#define CONFIG_SYS_CBSIZE  1024/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE  1024/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS 16  /* max number of command args */
 #define CONFIG_SYS_GENERIC_BOARD
 
-- 
2.1.0

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[U-Boot] [PATCH] HACK: arndale: deinit scsi before launching Linux

[Ian Campbell]

From: Ian Campbell ian.campb...@citrix.com

NOT TO BE APPLIED AS IS

Without this Linux fails to correctly init the phy (or something) and cannot
detect the disk.

Even with this we can fail to detect the disk outselves on some fraction of
boots, so something else is clearly up too.
---
 arch/arm/cpu/armv7/exynos/sata.c | 11 +++
 arch/arm/lib/bootm.c |  4 
 board/samsung/arndale/arndale.c  |  5 +
 drivers/block/ahci.c |  4 
 include/scsi.h   |  1 +
 5 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/exynos/sata.c b/arch/arm/cpu/armv7/exynos/sata.c
index 14d42e7..05f1372 100644
--- a/arch/arm/cpu/armv7/exynos/sata.c
+++ b/arch/arm/cpu/armv7/exynos/sata.c
@@ -310,6 +310,11 @@ static int exynos5_ahci_init(void __iomem *mmio)
printf(%s: already calibrated?\n, __func__);
}
 
+   /* Clear phy control enable. Seems to be necessary to
+* reinitialise on a warm reboot, at least sometimes. */
+   clrbits_le32(EXYNOS5_SATA_PHY_CONTROL, S5P_PMU_SATA_PHY_CONTROL_EN);
+   udelay(1000);
+
setbits_le32(EXYNOS5_SATA_PHY_CONTROL, S5P_PMU_SATA_PHY_CONTROL_EN);
 
__raw_writel(0, phy_ctrl + SATA_RESET);
@@ -368,3 +373,9 @@ int exynos5_sata_init(void)
}
return -ENODEV;
 }
+
+int exynos5_sata_deinit(void)
+{
+   clrbits_le32(EXYNOS5_SATA_PHY_CONTROL, S5P_PMU_SATA_PHY_CONTROL_EN);
+   return 0;
+}
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 39fe7a1..9c8d242 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -15,6 +15,7 @@
 #include common.h
 #include command.h
 #include image.h
+#include scsi.h
 #include u-boot/zlib.h
 #include asm/byteorder.h
 #include libfdt.h
@@ -81,6 +82,9 @@ static void announce_and_cleanup(int fake)
 #ifdef CONFIG_USB_DEVICE
udc_disconnect();
 #endif
+#ifdef CONFIG_SCSI_AHCI_PLAT
+   scsi_deinit();
+#endif
cleanup_before_linux();
 }
 
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 551bfce..43c9694 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -36,6 +36,11 @@ int scsi_init(void)
printf(ARNDALE SCSI INIT\n);
return exynos5_sata_init();
 }
+
+int scsi_deinit(void)
+{
+   return exynos5_sata_deinit();
+}
 #endif
 
 int board_init(void)
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index a93a8e1..a7e57be 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -959,6 +959,10 @@ void __weak scsi_init(void)
 {
 }
 
+void __weak scsi_deinit(void)
+{
+}
+
 #endif
 
 /*
diff --git a/include/scsi.h b/include/scsi.h
index 73de7b7..06ad192 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -172,6 +172,7 @@ void scsi_low_level_init(int busdevfunc);
  * functions residing inside cmd_scsi.c
  */
 void scsi_init(void);
+void scsi_deinit(void);
 void scsi_scan(int mode);
 
 /** @return the number of scsi disks */
-- 
2.1.0

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[U-Boot] [PATCH] arndale: Increase command line buffer size (CONFIG_SYS_CBSIZE)

[Ian Campbell]

From: Ian Campbell ian.campb...@citrix.com

I was running into this limit with a not overly long PXE append line.

Since the PXE code wants to print the resulting command line increase
CONFIG_SYS_PBSIZE too.

Signed-off-by: Ian Campbell ian.campb...@citrix.com
---
 include/configs/arndale.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index f702b6e..adc3eaa 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -116,8 +116,8 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_PROMPT  ARNDALE # 
-#define CONFIG_SYS_CBSIZE  256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE  384 /* Print Buffer Size */
+#define CONFIG_SYS_CBSIZE  1024/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE  1024/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS 16  /* max number of command args */
 #define CONFIG_DEFAULT_CONSOLE console=ttySAC2,115200n8\0
 /* Boot Argument Buffer Size */
-- 
2.1.0

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Re: [U-Boot] [PATCH] HACK: arndale: deinit scsi before launching Linux

[Ian Campbell]

On Tue, 2014-10-07 at 14:36 +0100, Ian Campbell wrote:

Please ignore, I ran git send-email from the wrong branch, this isn't
ready yet...


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[U-Boot] [PATCH RFC 0/2] u-boot: arndale: Support for SATA controller.

[Ian Campbell]

Hello,

The following series ports over Taylor Hutt's patches to enable SATA for
the Chromeos smdk5250 u-boot and enables it for arndale (but not
smdk5250 since I don't have one).

In terms of basic access from u-boot it works for me but there is a
strange issue once booted Linux, which is that it will fail to detect
the disk if the PMU bit for the SATA is not disabled prior to launching
Linux, see the second patch for a hack which helps, but not completely.
Even with that hack it still fails to detect the disk some fraction of
the time, in both failure cases the output is essentially the same:

[2.380814] ahci 122f.sata: SSS flag set, parallel bus scan disabled
[2.386096] ahci 122f.sata: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 
impl platform mode
[2.394583] ahci 122f.sata: flags: ncq sntf stag pm led clo only pmp pio 
slum part ccc apst 
[2.424239] scsi0 : ahci_platform
[2.427650] ata1: SATA max UDMA/133 mmio [mem 0x122f-0x122f01fe] port 
0x100 irq 147
[   12.433897] ata1: softreset failed (1st FIS failed)
[   22.433896] ata1: softreset failed (1st FIS failed)
[   57.433895] ata1: softreset failed (1st FIS failed)
[   57.437299] ata1: limiting SATA link speed to 1.5 Gbps
[   62.629902] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 310)
[   62.634623] ata1.00: link online but device misclassified
[   62.634632] ata1: link online but 1 devices misclassified, device detection 
might fail

Usually a warm reset will succeed, although sometimes it seems a hard
reset is required. When it works I see instead:

[2.337636] ahci 122f.sata: SSS flag set, parallel bus scan disabled
[2.342901] ahci 122f.sata: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 
impl platform mode
[2.351392] ahci 122f.sata: flags: ncq sntf stag pm led clo only pmp pio 
slum part ccc apst 
[2.364181] scsi0 : ahci_platform
[2.368469] ata1: SATA max UDMA/133 mmio [mem 0x122f-0x122f01fe] port 
0x100 irq 147
[2.865454] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[2.870972] ata1.00: ATA-8: HGST HTS545050A7E380, GG2OAC90, max UDMA/133
[2.876867] ata1.00: 976773168 sectors, multi 16: LBA48 NCQ (depth 31/32)
[2.884496] ata1.00: configured for UDMA/133
[2.888172] scsi 0:0:0:0: Direct-Access ATA  HGST HTS545050A7 AC90 
PQ: 0 ANSI: 5
[3.277166] sd 0:0:0:0: [sda] Attached SCSI disk
[3.286625] sd 0:0:0:0: Attached scsi generic sg0 type 0

My suspicion is that the SATA PHY is not being properly reset by Linux,
but I've mucked around with it in various ways (on the u-boot side only)
to no avail. The u-boot and Linux code here is identical AFAICT (modulo
my mucking around and the use of clr/setbits in u-boot, but Linux open
codes the same thing).

Kukjin  Yuvaraj, I've included you in the CC line in case you can shed
any light on the issue from the Linux side.

Thanks,
Ian.

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[U-Boot] [PATCH 2/2] HACK: arndale: deinit scsi before launching Linux

[Ian Campbell]

From: Ian Campbell ian.campb...@citrix.com

NOT TO BE APPLIED AS IS

Without this Linux fails to correctly init the phy (or something) and cannot
detect the disk.

Even with this we can fail to detect the disk outselves on some fraction of
boots, so something else is clearly up too.
---
 arch/arm/cpu/armv7/exynos/sata.c | 11 +++
 arch/arm/lib/bootm.c |  4 
 board/samsung/arndale/arndale.c  |  5 +
 drivers/block/ahci.c |  4 
 include/scsi.h   |  1 +
 5 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/exynos/sata.c b/arch/arm/cpu/armv7/exynos/sata.c
index 14d42e7..05f1372 100644
--- a/arch/arm/cpu/armv7/exynos/sata.c
+++ b/arch/arm/cpu/armv7/exynos/sata.c
@@ -310,6 +310,11 @@ static int exynos5_ahci_init(void __iomem *mmio)
printf(%s: already calibrated?\n, __func__);
}
 
+   /* Clear phy control enable. Seems to be necessary to
+* reinitialise on a warm reboot, at least sometimes. */
+   clrbits_le32(EXYNOS5_SATA_PHY_CONTROL, S5P_PMU_SATA_PHY_CONTROL_EN);
+   udelay(1000);
+
setbits_le32(EXYNOS5_SATA_PHY_CONTROL, S5P_PMU_SATA_PHY_CONTROL_EN);
 
__raw_writel(0, phy_ctrl + SATA_RESET);
@@ -368,3 +373,9 @@ int exynos5_sata_init(void)
}
return -ENODEV;
 }
+
+int exynos5_sata_deinit(void)
+{
+   clrbits_le32(EXYNOS5_SATA_PHY_CONTROL, S5P_PMU_SATA_PHY_CONTROL_EN);
+   return 0;
+}
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 39fe7a1..9c8d242 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -15,6 +15,7 @@
 #include common.h
 #include command.h
 #include image.h
+#include scsi.h
 #include u-boot/zlib.h
 #include asm/byteorder.h
 #include libfdt.h
@@ -81,6 +82,9 @@ static void announce_and_cleanup(int fake)
 #ifdef CONFIG_USB_DEVICE
udc_disconnect();
 #endif
+#ifdef CONFIG_SCSI_AHCI_PLAT
+   scsi_deinit();
+#endif
cleanup_before_linux();
 }
 
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 551bfce..43c9694 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -36,6 +36,11 @@ int scsi_init(void)
printf(ARNDALE SCSI INIT\n);
return exynos5_sata_init();
 }
+
+int scsi_deinit(void)
+{
+   return exynos5_sata_deinit();
+}
 #endif
 
 int board_init(void)
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index a93a8e1..a7e57be 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -959,6 +959,10 @@ void __weak scsi_init(void)
 {
 }
 
+void __weak scsi_deinit(void)
+{
+}
+
 #endif
 
 /*
diff --git a/include/scsi.h b/include/scsi.h
index 73de7b7..06ad192 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -172,6 +172,7 @@ void scsi_low_level_init(int busdevfunc);
  * functions residing inside cmd_scsi.c
  */
 void scsi_init(void);
+void scsi_deinit(void);
 void scsi_scan(int mode);
 
 /** @return the number of scsi disks */
-- 
2.1.0

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[U-Boot] [PATCH 1/2] exynos5250/arndale: Enable SATA/AHCI support.

[Ian Campbell]

From: Ian Campbell ian.campb...@citrix.com

This is based on some old patches from the chromeos-v2011.12 branch of
http://git.chromium.org/chromiumos/third_party/u-boot.git by Taylor Hutt.
Specifically:

http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=26f6c570b5deb37c52306920ae049203c68f014a
exynos: sata: on-board controller initialization
Signed-off-by: Taylor Hutt th...@chromium.org

http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=d8cac5cf0b63df00d2d6ac7df814613e4b60b9d1
exynos: sata: Add sata_initialize() interface
Signed-off-by: Taylor Hutt th...@chromium.org

http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=dd32462453d6328bc5770859d1b56501f7920d7d
exynos: sata: SATA self-configuration for when SATA device is enabled
Signed-off-by: Taylor Hutt th...@chromium.org

As well as rebasing there have been some significant changes.

 - Drop support for smdk5250, which I don't own.
 - Implement support for arndale, which I do.
 - Since arndale has no need to frob a GPIO on SATA init drop the associated
   code.
 - Initialise via the existing scsi_init hook rather than introducing
   sata_initialize, associated build system and include/configs/*.h changes.
 - Use set/clrbits in a bunch of places
 - Add some #defines for some magic numbers.

This relies on ahci: Don't start command DMA engine before buffers are set

NOTE: For some reason when running u-boot with this patch Linux is unable to
correct probe devices. See the next patch for an attempt at a hack/workaround.
Any ideas would be appreciated.

Signed-off-by: Ian Campbell ian.campb...@citrix.com
Cc: Taylor Hutt th...@chromium.org
Cc: Simon Glass s...@chromium.org
---
 arch/arm/cpu/armv7/exynos/Makefile  |   4 +
 arch/arm/cpu/armv7/exynos/sata.c| 370 
 arch/arm/include/asm/arch-exynos/sata.h |  29 +++
 arch/arm/lib/board.c|   1 +
 board/samsung/arndale/arndale.c |   9 +
 include/configs/arndale.h   |  13 ++
 6 files changed, 426 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/exynos/sata.c
 create mode 100644 arch/arm/include/asm/arch-exynos/sata.h

diff --git a/arch/arm/cpu/armv7/exynos/Makefile 
b/arch/arm/cpu/armv7/exynos/Makefile
index e207bd6..c74a2d4 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -7,6 +7,10 @@
 
 obj-y  += clock.o power.o soc.o system.o pinmux.o tzpc.o
 
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_EXYNOS5250_AHCI) += sata.o
+endif
+
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_EXYNOS5)  += clock_init_exynos5.o
 obj-$(CONFIG_EXYNOS5)  += dmc_common.o dmc_init_ddr3.o
diff --git a/arch/arm/cpu/armv7/exynos/sata.c b/arch/arm/cpu/armv7/exynos/sata.c
new file mode 100644
index 000..14d42e7
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/sata.c
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include asm/types.h
+#include ahci.h
+#include common.h
+#include fdtdec.h
+#include scsi.h
+#include asm/arch/sata.h
+#include asm/arch/pinmux.h
+#include asm/arch/clock.h
+#include asm/arch/clk.h
+#include asm/errno.h
+#include asm/gpio.h
+#include linux/compiler.h
+
+#define SATA_AHCI_AXI  0x122f
+#define SATA_PHCTRL_APB0x1217
+#define SATA_PHY_I2C_ABP   0x121d
+#define EXYNOS5_SATA_PHY_CONTROL   (0x1004 + 0x724)
+#define S5P_PMU_SATA_PHY_CONTROL_EN0x1
+
+void * const phy_ctrl = (void *)SATA_PHCTRL_APB;
+void * const phy_i2c_base = (void *)SATA_PHY_I2C_ABP;
+
+#define SATA_TIME_LIMIT1
+#define SATA_PHY_I2C_SLAVE_ADDRS   0x70
+
+#define SATA_RESET 0x4
+#define RESET_GLOBAL_RST_N  (1  0)
+#define RESET_CMN_RST_N(1  1)
+#define RESET_CMN_BLOCK_RST_N   (1  2)
+#define RESET_CMN_I2C_RST_N (1  3)
+#define RESET_TX_RX_PIPE_RST_N  (1  4)
+#define RESET_TX_RX_BLOCK_RST_N (1  5)
+#define RESET_TX_RX_I2C_RST_N   ((1  6) | BIT(7))
+
+#define LINK_RESET 0xF
+
+#define 

Re: [U-Boot] [PATCH] HACK: arndale: deinit scsi before launching Linux

[Albert ARIBAUD]

Hi Ian,

In any case, if a patch is not to be applied but only commented, please
think of adding the [RFC] tag to it.

On Tue, 07 Oct 2014 14:45:01 +0100, Ian Campbell i...@hellion.org.uk
wrote:

 On Tue, 2014-10-07 at 14:36 +0100, Ian Campbell wrote:
 
 Please ignore, I ran git send-email from the wrong branch, this isn't
 ready yet...

Amicalement,
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[U-Boot] Upstream uboot and Arndale 5250 support

[Paolo Pisati]

Hi,

i've been trying to update the u-boot on my board (sd booting), from the Linaro
one (2012.10) to a v2014.X, but so far had no luck:

make arndale_config
export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf-
make

...

dd if=arndale-bl1.bin of=/dev/sdc bs=512 skip=1
dd if=arndale-spl.bin of=/dev/sdc bs=512 skip=17
dd if=./u-boot-dtb.bin of=/dev/sdc bs=512 skip=49

...

u-boot 3.10rc3 (same happens with v2014.07 or 2014.04):

U-Boot 2014.10-rc3 (Oct 07 2014 - 13:26:48) for ARNDALE

CPU:Exynos5250@1000MHz

Board: Arndale
I2C:   i2c_init: failed to init bus 0 for speed = 10
ready
DRAM:  2 GiB
trace: copying 00086db4 bytes of early data from 5000 to beff
trace: enabled
WARNING: Caches not enabled
MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1
dwmci_send_cmd: DATA ERROR!
i2c_init: failed to init bus 0 for speed = 10
In:serial
Out:   serial
Err:   serial
Net:   Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot:  0 
ARNDALE # printenv
baudrate=115200
bootargs=console=ttySAC2,115200n8 root=/dev/mmcblk1p1 rw rootwait debug 
earlyprintk
bootcmd=run bootcmd_ubuntu
bootcmd_ubuntu=run loadk; run loadf; run loadr; bootm ${kernel_addr_r} 
${ramdisk_addr_r}:${filesize} ${fdt_addr_r}
bootdelay=3
fdt_addr_r=0x4100
filesize=5b9902
kernel_addr_r=0x40007000
loadf=ext2load mmc 1:1 ${fdt_addr_r} /boot/exynos5250-arndale.dtb
loadk=ext2load mmc 1:1 ${kernel_addr_r} /boot/uImage
loadr=ext2load mmc 1:1 ${ramdisk_addr_r} /boot/uInitrd
ramdisk_addr_r=0x4200
stderr=serial
stdin=serial
stdout=serial

Environment size: 589/16380 bytes
ARNDALE # run loadk
6002946 bytes read in 1117 ms (5.1 MiB/s)
ARNDALE # bootm ${kernel_addr_r}
## Booting kernel from Legacy Image at 40007000 ...
   Image Name:   kernel 3.16.0-20-generic
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:6002882 Bytes = 5.7 MiB
   Load Address: 40008000
   Entry Point:  40008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Starting kernel ...(fake run for tracing)

Starting kernel ...

[stuck here]

here for a more complete log:

http://pastebin.ubuntu.com/8514108/plain/

Any idea what's going wrong? Did you try this board lately?

It's a kernel with the DTB concatenated (and it works fine with Linaro 2012
uboot), but the same happens if i explicitely pass the dtb:

U-Boot 2014.07 (Sep 30 2014 - 15:26:03) for ARNDALE

CPU:Exynos5250@1000MHz

Board: Arndale
I2C:   i2c_init: failed to init bus 0 for speed = 10
ready
DRAM:  2 GiB
trace: copying 00085818 bytes of early data from 5000 to beff
trace: enabled
WARNING: Caches not enabled
MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1
i2c_init: failed to init bus 0 for speed = 10
In:serial
Out:   serial
Err:   serial
Net:   Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot:  0 
ARNDALE # printenv
baudrate=115200
bootargs=console=ttySAC2,115200n8 root=/dev/mmcblk1p1 rw rootwait debug 
earlyprintk
bootcmd=run bootcmd_ubuntu
bootcmd_ubuntu=run loadk; run loadf; run loadr; bootm ${kernel_addr_r} 
${ramdisk_addr_r}:${filesize} ${fdt_addr_r}
bootdelay=3
fdt_addr_r=0x4100
filesize=5b9902
kernel_addr_r=0x40007000
loadf=ext2load mmc 1:1 ${fdt_addr_r} /boot/exynos5250-arndale.dtb
loadk=ext2load mmc 1:1 ${kernel_addr_r} /boot/uImage
loadr=ext2load mmc 1:1 ${ramdisk_addr_r} /boot/uInitrd
ramdisk_addr_r=0x4200
stderr=serial
stdin=serial
stdout=serial

Environment size: 589/16380 bytes
ARNDALE # run loadk
6002946 bytes read in 1114 ms (5.1 MiB/s)
ARNDALE # run loadf
35450 bytes read in 34 ms (1017.6 KiB/s)
ARNDALE # bootm ${kernel_addr_r} - ${fdt_addr_r}
## Booting kernel from Legacy Image at 40007000 ...
   Image Name:   kernel 3.16.0-20-generic
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:6002882 Bytes = 5.7 MiB
   Load Address: 40008000
   Entry Point:  40008000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 4100
   Booting using the fdt blob at 0x4100
   Loading Kernel Image ... OK
   Loading Device Tree to 4fff4000, end 4a79 ... OK

Starting kernel ...(fake run for tracing)


Starting kernel ...

[stuck again]

(please cc: me as i'm off list)
-- 
bye,
p.
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[U-Boot] [PATCH] arndale: Increase command line buffer size (CONFIG_SYS_CBSIZE)

[Ian Campbell]

I was running into this limit with a not overly long PXE append line.

Since the PXE code wants to print the resulting command line increase
CONFIG_SYS_PBSIZE too.

Signed-off-by: Ian Campbell ian.campb...@citrix.com
---
 include/configs/arndale.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index f702b6e..adc3eaa 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -116,8 +116,8 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_PROMPT  ARNDALE # 
-#define CONFIG_SYS_CBSIZE  256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE  384 /* Print Buffer Size */
+#define CONFIG_SYS_CBSIZE  1024/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE  1024/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS 16  /* max number of command args */
 #define CONFIG_DEFAULT_CONSOLE console=ttySAC2,115200n8\0
 /* Boot Argument Buffer Size */
-- 
2.1.0

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[U-Boot] [PATCH] sunxi: Increase command line buffer size (CONFIG_SYS_CBSIZE)

[Ian Campbell]

I was running into this limit with a not overly long PXE append line.

Since the PXE code wants to print the resulting command line increase
CONFIG_SYS_PBSIZE too.

Signed-off-by: Ian Campbell ian.campb...@citrix.com
---
 include/configs/sunxi-common.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1d947d7..d4419a2 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -92,8 +92,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_CMD_ECHO
-#define CONFIG_SYS_CBSIZE  256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE  384 /* Print Buffer Size */
+#define CONFIG_SYS_CBSIZE  1024/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE  1024/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS 16  /* max number of command args */
 #define CONFIG_SYS_GENERIC_BOARD
 
-- 
2.1.0

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Re: [U-Boot] Upstream uboot and Arndale 5250 support

[Guillaume Gardet]

Hi,

Le 07/10/2014 14:58, Paolo Pisati a écrit :

Hi,

i've been trying to update the u-boot on my board (sd booting), from the Linaro
one (2012.10) to a v2014.X, but so far had no luck:

make arndale_config
export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf-
make

...

dd if=arndale-bl1.bin of=/dev/sdc bs=512 skip=1
dd if=arndale-spl.bin of=/dev/sdc bs=512 skip=17
dd if=./u-boot-dtb.bin of=/dev/sdc bs=512 skip=49

...

u-boot 3.10rc3 (same happens with v2014.07 or 2014.04):

U-Boot 2014.10-rc3 (Oct 07 2014 - 13:26:48) for ARNDALE

CPU:Exynos5250@1000MHz

Board: Arndale
I2C:   i2c_init: failed to init bus 0 for speed = 10
ready
DRAM:  2 GiB
trace: copying 00086db4 bytes of early data from 5000 to beff
trace: enabled
WARNING: Caches not enabled
MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1
dwmci_send_cmd: DATA ERROR!
i2c_init: failed to init bus 0 for speed = 10
In:serial
Out:   serial
Err:   serial
Net:   Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot:  0
ARNDALE # printenv
baudrate=115200
bootargs=console=ttySAC2,115200n8 root=/dev/mmcblk1p1 rw rootwait debug 
earlyprintk
bootcmd=run bootcmd_ubuntu
bootcmd_ubuntu=run loadk; run loadf; run loadr; bootm ${kernel_addr_r} 
${ramdisk_addr_r}:${filesize} ${fdt_addr_r}
bootdelay=3
fdt_addr_r=0x4100
filesize=5b9902
kernel_addr_r=0x40007000
loadf=ext2load mmc 1:1 ${fdt_addr_r} /boot/exynos5250-arndale.dtb
loadk=ext2load mmc 1:1 ${kernel_addr_r} /boot/uImage
loadr=ext2load mmc 1:1 ${ramdisk_addr_r} /boot/uInitrd
ramdisk_addr_r=0x4200
stderr=serial
stdin=serial
stdout=serial

Environment size: 589/16380 bytes
ARNDALE # run loadk
6002946 bytes read in 1117 ms (5.1 MiB/s)
ARNDALE # bootm ${kernel_addr_r}
## Booting kernel from Legacy Image at 40007000 ...
Image Name:   kernel 3.16.0-20-generic
Image Type:   ARM Linux Kernel Image (uncompressed)
Data Size:6002882 Bytes = 5.7 MiB
Load Address: 40008000
Entry Point:  40008000
Verifying Checksum ... OK
Loading Kernel Image ... OK

Starting kernel ...(fake run for tracing)

Starting kernel ...

[stuck here]


I faced this problem some times ago. Try to modify kernel, initrd and fdt 
addresses.


Guillaume

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Re: [U-Boot] [PATCH 29/32] nitrogen6x: config: configure usb_ether

[Stefano Babic]

Hi Eric,

On 06/10/2014 18:41, Eric Nelson wrote:

 I understand the use case, but it does not always work (I mean, in all
 network configurations) and we regret generally having IP addresses hard
 coded in the default configuration.

 
 Can you clarify which parts (mac/IP address/both) are a problem?
 
 The 'usb_ether' is kind of an odd beast, in that it's a link-local
 protocol, which is why the the IP addresses aren't read from or written
 to a persistent environment.

This is not completely true. I mean, I understand that you want to have
such as situation, with addresses valid only in the link host / target.

However, if a customer / user has a PC belonging to the  10.0.0.0/24
network, there is a conflict. And this is not a rare case, because as I
have seen in companies 10.0.0.0/8 are used more often as 192.168.0.0/16.

You can have two interface (ethernet and USB) acting on the same address
range and packets originally sent to network are readdressed to the
target, letting the customer without network.

I understand that you want to provide is a special case - but as you can
see, you cannot cover all cases by setting a hard coded address.

 
 Our goal was to only require configuration of one side of the link
 (the USB Host). It seems that without implementing a DHCP **server**,
 this is the most convenient.

If you really want, why don't you use a script as a 6x_ ? usbrecover can
load initially a script setting the network addresses, without
hardcoding to the u-boot image.

 
 The mac addresses above are ours, and we can confirm that they are
 not in use on any other hardware,

I know that and it is exactly the same we had in the past with other
boards. Customers can buy more as one instance of the boards, having
then multiple boards with the same MAC address - and very bad case.


 so they're guaranteed to be unique
 unless you happen to hook up multiple of our boards to a Host at the
 same time.

Yes, exactly. Why do you want to restrict your sales chances ? :-D

Seriously, hard coding mac and network addresses was strictly rejected -
even if after your patch I have found a couple of boards doing that
(maybe it was not seen during review, see for example  v38b.h).

 
 Since the configuration of network adapters on most hosts is based
 on mac addresses, hard-coding these prevents the need to re-configure
 each time a new board is connected to a host.

I understand that hard coding makes life easier, but I am not convinced
it is the correct way to do, specially with IP addresses.

Best regards,
Stefano Babic


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Re: [U-Boot] Upstream uboot and Arndale 5250 support

[Paolo Pisati]

those are the addresses suggested by u-boot and yes, i already tried
moving stuff around but it didn't fix it: what's the working config
with your board? u-boot version?

On Tue, Oct 7, 2014 at 4:34 PM, Guillaume Gardet
guillaume.gar...@free.fr wrote:
 Hi,

 Le 07/10/2014 14:58, Paolo Pisati a écrit :

 Hi,

 i've been trying to update the u-boot on my board (sd booting), from the
 Linaro
 one (2012.10) to a v2014.X, but so far had no luck:

 make arndale_config
 export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf-
 make

 ...

 dd if=arndale-bl1.bin of=/dev/sdc bs=512 skip=1
 dd if=arndale-spl.bin of=/dev/sdc bs=512 skip=17
 dd if=./u-boot-dtb.bin of=/dev/sdc bs=512 skip=49

 ...

 u-boot 3.10rc3 (same happens with v2014.07 or 2014.04):

 U-Boot 2014.10-rc3 (Oct 07 2014 - 13:26:48) for ARNDALE

 CPU:Exynos5250@1000MHz

 Board: Arndale
 I2C:   i2c_init: failed to init bus 0 for speed = 10
 ready
 DRAM:  2 GiB
 trace: copying 00086db4 bytes of early data from 5000 to beff
 trace: enabled
 WARNING: Caches not enabled
 MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1
 dwmci_send_cmd: DATA ERROR!
 i2c_init: failed to init bus 0 for speed = 10
 In:serial
 Out:   serial
 Err:   serial
 Net:   Net Initialization Skipped
 No ethernet found.
 Hit any key to stop autoboot:  0
 ARNDALE # printenv
 baudrate=115200
 bootargs=console=ttySAC2,115200n8 root=/dev/mmcblk1p1 rw rootwait debug
 earlyprintk
 bootcmd=run bootcmd_ubuntu
 bootcmd_ubuntu=run loadk; run loadf; run loadr; bootm ${kernel_addr_r}
 ${ramdisk_addr_r}:${filesize} ${fdt_addr_r}
 bootdelay=3
 fdt_addr_r=0x4100
 filesize=5b9902
 kernel_addr_r=0x40007000
 loadf=ext2load mmc 1:1 ${fdt_addr_r} /boot/exynos5250-arndale.dtb
 loadk=ext2load mmc 1:1 ${kernel_addr_r} /boot/uImage
 loadr=ext2load mmc 1:1 ${ramdisk_addr_r} /boot/uInitrd
 ramdisk_addr_r=0x4200
 stderr=serial
 stdin=serial
 stdout=serial

 Environment size: 589/16380 bytes
 ARNDALE # run loadk
 6002946 bytes read in 1117 ms (5.1 MiB/s)
 ARNDALE # bootm ${kernel_addr_r}
 ## Booting kernel from Legacy Image at 40007000 ...
 Image Name:   kernel 3.16.0-20-generic
 Image Type:   ARM Linux Kernel Image (uncompressed)
 Data Size:6002882 Bytes = 5.7 MiB
 Load Address: 40008000
 Entry Point:  40008000
 Verifying Checksum ... OK
 Loading Kernel Image ... OK

 Starting kernel ...(fake run for tracing)

 Starting kernel ...

 [stuck here]


 I faced this problem some times ago. Try to modify kernel, initrd and fdt
 addresses.


 Guillaume




-- 
bye,
p.
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Re: [U-Boot] [PATCH 29/32] nitrogen6x: config: configure usb_ether

[Eric Nelson]

Thanks Stefano,

On 10/07/2014 07:36 AM, Stefano Babic wrote:
 Hi Eric,
 
 On 06/10/2014 18:41, Eric Nelson wrote:
 
 I understand the use case, but it does not always work (I mean, in all
 network configurations) and we regret generally having IP addresses hard
 coded in the default configuration.


 Can you clarify which parts (mac/IP address/both) are a problem?

 The 'usb_ether' is kind of an odd beast, in that it's a link-local
 protocol, which is why the the IP addresses aren't read from or written
 to a persistent environment.
 
 This is not completely true. I mean, I understand that you want to have
 such as situation, with addresses valid only in the link host / target.
 
 However, if a customer / user has a PC belonging to the  10.0.0.0/24
 network, there is a conflict. And this is not a rare case, because as I
 have seen in companies 10.0.0.0/8 are used more often as 192.168.0.0/16.
 
 You can have two interface (ethernet and USB) acting on the same address
 range and packets originally sent to network are readdressed to the
 target, letting the customer without network.
 
 I understand that you want to provide is a special case - but as you can
 see, you cannot cover all cases by setting a hard coded address.
 

Right. I've also seen that.

It seems that 169.254.x.x is more appropriate.
http://tools.ietf.org/html/rfc3927


 Our goal was to only require configuration of one side of the link
 (the USB Host). It seems that without implementing a DHCP **server**,
 this is the most convenient.
 
 If you really want, why don't you use a script as a 6x_ ? usbrecover can
 load initially a script setting the network addresses, without
 hardcoding to the u-boot image.
 

Chicken and egg The goal for usbrecover was/is to allow access to
on-board storage (SATA on Nitrogen6x, eMMC on Nitrogen6_Max)

Thankfully, the ums utility now functions nicely for that purpose
without using IP.

A kernel gadget still performs much better though (~2x), since you can
interleave writes to storage with USB I/O.


 The mac addresses above are ours, and we can confirm that they are
 not in use on any other hardware,
 
 I know that and it is exactly the same we had in the past with other
 boards. Customers can buy more as one instance of the boards, having
 then multiple boards with the same MAC address - and very bad case.
 
 so they're guaranteed to be unique
 unless you happen to hook up multiple of our boards to a Host at the
 same time.
 
 Yes, exactly. Why do you want to restrict your sales chances ? :-D
 

This (and all of our patches) is an attempt to increase sales by
making life easier on users.

 Seriously, hard coding mac and network addresses was strictly rejected -
 even if after your patch I have found a couple of boards doing that
 (maybe it was not seen during review, see for example  v38b.h).
 

Understood.


 Since the configuration of network adapters on most hosts is based
 on mac addresses, hard-coding these prevents the need to re-configure
 each time a new board is connected to a host.
 
 I understand that hard coding makes life easier, but I am not convinced
 it is the correct way to do, specially with IP addresses.
 

Right.

Perhaps when we have some spare time we could write a DHCP
server component to get closer to auto-configuration, although it's not
clear how that would interact with other commands.

I appreciate your time in review and commenting.

Regards,


Eric

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Re: [U-Boot] [PATCH v5 0/15] samsung: Use common config files with Samsung boards

[Simon Glass]

Hi Minkyu,

On 7 October 2014 05:24, Minkyu Kang mk7.k...@samsung.com wrote:
 Dear Simon Glass,

 On 06/10/14 03:39, Simon Glass wrote:
 Hi Minkyu,

 On 1 October 2014 21:44, Simon Glass s...@chromium.org wrote:
 Hi Minkyu,

 On 1 October 2014 21:43, Simon Glass s...@chromium.org wrote:
 This series tries to unify the Samsung board configs into a few header
 files for exynos5 and exynos4.

 The purpose is to make it easier to move to driver model. In that case
 I would like things like the GPIO drivers and serial drivers to work in
 a standard way, and not need to support device tree and platform data at
 the same time. That would be quite painful.

 Another reason is that the Chrome OS EC drivers are currently included in
 boards that don't have a Chrome OS EC. This concern was raised by the
 Samsung maintainer (Minkyu) a while back.

 There are still a few boards that don't use CONFIG_OF_CONTROL so I have
 updated these rudimentary of device tree files based on feedback.

 This series has the side-effect of getting the EC interface working
 properly on Pit, so the keyboard works. It also provides access to the
 TPS65090 PMIC, which means that the backlight is enabled.

 Changes in v5:
 - Rebase on top of samsung/master

 Please check this and see if it works for what you need.

 I suppose the merge will be Albert's problem, but I will do a patch
 once I know the detla.

 Actually I see that Albert has pulled this in. So v4 should work for
 you now. I just tried applying it on u-boot-arm/master and it worked
 OK.

 Regards,
 Simon


 Hm, I tried to apply. but failed..

 Applying: Exynos: Use 900MHz ARM frequency in SPL for peach_pit
 Applying: exynos5: Enable data cache
 Applying: cros_ec: power: Add a tunnelled version of the tps65090 driver
 Applying: cros_ec: exynos: Use the correct tps65090 driver in each case
 Applying: dm: exynos: Split out the cros_ec drivers
 Applying: exynos: dts: Add device tree node for cros_ec keyboard
 Applying: exynos: Rename -dt config files to -common
 Applying: exynos: Move common exynos settings into a common file
 Applying: exynos: Move common smdk5420 things to common file
 Applying: exynos: config: Move cros_ec and tps65090 out of smdk boards
 Applying: config: Move arndale to use common exynos5250 file
 Applying: config: Move smdkv310 to use common exynos4 file
 Applying: samsung: Enable device tree for s5p_goni
 error: patch failed: arch/arm/Kconfig:547
 error: arch/arm/Kconfig: patch does not apply
 Patch failed at 0013 samsung: Enable device tree for s5p_goni


It looks like you still haven't synced up with the ARM tree?

In particular there are these patches there that are needed:

f1ef2b6 kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig
783e6a7 kconfig: move CONFIG_OF_* to Kconfig

I put a bundle here:

http://patchwork.ozlabs.org/bundle/sjg/pitv4/

This should apply OK once you sync up with arm again. If you still
have problems then, please let me know.

Regards,
Simon
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Re: [U-Boot] Pull request: u-boot-arm/master

[Tom Rini]

On Tue, Oct 07, 2014 at 01:16:00PM +0200, Albert ARIBAUD wrote:

 Hi Tom,
 
 The following changes since commit
 be9f643ae6aa9044c60fe80e3a2c10be8371c692:
 
   Merge branch 'for-tom' of git://git.denx.de/u-boot-dm (2014-09-26
   20:10:48 -0400)
 
 are available in the git repository at:
 
 
   git://git.denx.de/u-boot-arm master
 
 for you to fetch changes up to c19a8bc5711ec63e905ef91f045a1489f0aa3cb0:
 
   vf610twr: Tune DDR initialization settings (2014-10-07 13:08:31 +0200)
 
 
 Albert ARIBAUD (1):
   Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master'
 
 Anthony Felice (1):
   vf610twr: Tune DDR initialization settings
 
 DrEagle (5):
   ARM: sheevaplug: change env location
   ARM: sheevaplug: add MVSATA driver
   ARM: sheevaplug: add MTD defaults
   ARM: sheevaplug: redefine MTDPARTS
   ARM: sheevaplug: add HUSH parser
 
 Masahiro Yamada (7):
   mtd: denali: add Denali controller configs to Kconfig
   mtd: denali: add Denali NAND driver for SPL
   serial: add UniPhier serial driver
   ARM: UniPhier: add UniPhier SoC support code
   ARM: UniPhier: add Kconfig and defconfig
   MAINTAINERS: add me as a maintainer of UniPhier platform
   git-mailrc: add me as a maintainer of UniPhier platform
 
 Michael Walle (1):
   lsxl: convert to generic board and fix typo
 
  MAINTAINERS|9 +
  arch/arm/Kconfig   |5 +
  arch/arm/cpu/armv7/uniphier/Kconfig|   32 +
  arch/arm/cpu/armv7/uniphier/Makefile   |   23 +
  arch/arm/cpu/armv7/uniphier/board_common.c |   32 +
  arch/arm/cpu/armv7/uniphier/board_late_init.c  |   91 ++
  arch/arm/cpu/armv7/uniphier/cache_uniphier.c   |  154 +++
  arch/arm/cpu/armv7/uniphier/cmd_pinmon.c   |   33 +
  arch/arm/cpu/armv7/uniphier/cpu_info.c |   59 ++
  arch/arm/cpu/armv7/uniphier/dram_init.c|   37 +
  arch/arm/cpu/armv7/uniphier/init_page_table.c  | 1068
  
  arch/arm/cpu/armv7/uniphier/lowlevel_init.S|  159 +++
  arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile   |   10 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c |   33 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c   |   16
  + .../armv7/uniphier/ph1-ld4/board_postclk_init.c|   42 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c|1 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c  |   29 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c  |   63 ++
  arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c |  189 
  arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c |1 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c |   44 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c  |   28 +
  arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c |  162 +++
  arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile  |   10 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c  |   16
  + .../armv7/uniphier/ph1-pro4/board_postclk_init.c   |   39 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c   |   66 ++
  arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c |   29 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c |   45 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c|  168
  +++ .../arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c |   18 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c|   75 ++
  arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c |   28 +
  arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c|  136 +++
  arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile  |   10 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c|1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c  |   16
  + .../armv7/uniphier/ph1-sld8/board_postclk_init.c   |1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c   |1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c |   29 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c |   57 ++
  arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c|  201
   .../arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c |1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c|   51 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c |1 +
  arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c|  142 +++
  arch/arm/cpu/armv7/uniphier/reset.c|   29 +
  arch/arm/cpu/armv7/uniphier/smp.S  |   54 +
  arch/arm/cpu/armv7/uniphier/spl.c  |   17 +
  arch/arm/cpu/armv7/uniphier/support_card.c |  180 
  arch/arm/cpu/armv7/uniphier/timer.c|   39 +
  arch/arm/include/asm/arch-uniphier/arm-mpcore.h|   46 +
  arch/arm/include/asm/arch-uniphier/bcu-regs.h  |   30 +
  arch/arm/include/asm/arch-uniphier/board.h |   35 +
  arch/arm/include/asm/arch-uniphier/boot-device.h   |   20 +
  arch/arm/include/asm/arch-uniphier/led.h   |  101 

Re: [U-Boot] [PATCH 2/2] usb: eth: smsc95xx: Add EEPROM access support

[Pavel Machek]

Hi!

   +static u8 eeprom_defaults[] = {
   + /* 0x00 */
   + 0xA5,   /* Signature */
   + 0xFF, 0xFF, /* MAC bytes 0-1 */
   + 0xFF, 0xFF, /* MAC bytes 2-3 */
   + 0xFF, 0xFF, /* MAC bytes 4-5 */
  
  Normally, we use all zeros for unset...?
 
 That's what the controller use when the EEPROM hasn't been programmed,
 but I'll change it to all 0.

Aha, if this is in-controller-default, don't change it. But comment
explaining where this comes from would be nice.

Thanks,
Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) 
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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Re: [U-Boot] U-Boot Mini Summit

[Alexey Brodkin]

Hi Detlev,

On Tue, 2014-10-07 at 11:38 +0200, Detlev Zundel wrote:
 Hello Masahiro-san,
 
 [...]
 
  Perhaps, is it better to insert 5-minute break between talks?
  Speakers might need to get something prepared. (connecting their
  laptop to the beamer, etc.)
 
 Of course.  I did not explicitely include this in the agenda, but such a
 5 minute break is what I'll strive to maintain.

I would even propose to have a backup setup for slides presentation.

I remember I once tried to use a beamer attached to my Fedora-driven
laptop and didn't succeed with that.

Moreover new gen laptops may only have like mini-DisplayPort output
instead of VGA so there's a probability some laptops won't have a chance
to be connected to existing (not that advanced/modern) beamer.

So given you guys have all presentations beforehand (I believe in for of
PDFs) would be good to have an ability to display them if my laptop
refuses to work with beamer again.

-Alexey
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[U-Boot] [PATCH] cli: hush: Adjust 'run' command to run each line of the env var

[Simon Glass]

The run command treats each argument an an environment variable. It gets the
value of each variable and executes it as a command. If an environment
variable contains a newline and the hush cli is used, it is supposed to
execute each line one after the other.

Normally a newline signals to hush to exit - this is used in normal command
line entry - after a command is entered we want to return to allow the user
to enter the next one. But environment variables obviously need to execute
to completion.

Add a special case for the execution of environment variables which
continues when a newline is seen, and add a few tests to check this
behaviour.

Note: it's not impossible that this may cause regressions in other areas.
I can't think of a case but with any change of behaviour with limited test
coverage there is always a risk. From what I can tell this behaviour has
been around since at least U-Boot 2011.03, although this pre-dates sandbox
and I have not tested it on real hardware.

Reported-by: Wolfgang Denk w...@denx.de
Signed-off-by: Simon Glass s...@chromium.org
---

 common/cli.c   |  9 ++---
 common/cli_hush.c  |  3 ++-
 include/cli_hush.h |  1 +
 include/command.h  |  1 +
 test/command_ut.c  | 14 ++
 5 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/common/cli.c b/common/cli.c
index 272b028..075ae9d 100644
--- a/common/cli.c
+++ b/common/cli.c
@@ -36,8 +36,11 @@ int run_command(const char *cmd, int flag)
 
return 0;
 #else
-   return parse_string_outer(cmd,
-   FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+   int hush_flags = FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP;
+
+   if (flag  CMD_FLAG_ENV)
+   hush_flags |= FLAG_CONT_ON_NEWLINE;
+   return parse_string_outer(cmd, hush_flags);
 #endif
 }
 
@@ -125,7 +128,7 @@ int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
return 1;
}
 
-   if (run_command(arg, flag) != 0)
+   if (run_command(arg, flag | CMD_FLAG_ENV) != 0)
return 1;
}
return 0;
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 38da5a0..2b654b7 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3170,7 +3170,8 @@ static int parse_stream_outer(struct in_str *inp, int 
flag)
update_ifs_map();
if (!(flag  FLAG_PARSE_SEMICOLON) || (flag  FLAG_REPARSING)) 
mapset((uchar *);$|, 0);
inp-promptmode=1;
-   rcode = parse_stream(temp, ctx, inp, '\n');
+   rcode = parse_stream(temp, ctx, inp,
+flag  FLAG_CONT_ON_NEWLINE ? -1 : '\n');
 #ifdef __U_BOOT__
if (rcode == 1) flag_repeat = 0;
 #endif
diff --git a/include/cli_hush.h b/include/cli_hush.h
index 4951eef..57c870d 100644
--- a/include/cli_hush.h
+++ b/include/cli_hush.h
@@ -11,6 +11,7 @@
 #define FLAG_EXIT_FROM_LOOP 1
 #define FLAG_PARSE_SEMICOLON (1  1)/* symbol ';' is special for parser */
 #define FLAG_REPARSING   (1  2)/* =2nd pass */
+#define FLAG_CONT_ON_NEWLINE (1  3)/* continue when we see \n */
 
 extern int u_boot_hush_start(void);
 extern int parse_string_outer(const char *, int);
diff --git a/include/command.h b/include/command.h
index 6f06db1..bd3fc04 100644
--- a/include/command.h
+++ b/include/command.h
@@ -147,6 +147,7 @@ int cmd_process(int flag, int argc, char * const argv[],
  */
 #define CMD_FLAG_REPEAT0x0001  /* repeat last command  
*/
 #define CMD_FLAG_BOOTD 0x0002  /* command is from bootd*/
+#define CMD_FLAG_ENV   0x0004  /* command is from the environment */
 
 #ifdef CONFIG_AUTO_COMPLETE
 # define _CMD_COMPLETE(x) x,
diff --git a/test/command_ut.c b/test/command_ut.c
index ae6466d..e136075 100644
--- a/test/command_ut.c
+++ b/test/command_ut.c
@@ -66,7 +66,21 @@ static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
assert(run_command_list(false, -1, 0) == 1);
assert(run_command_list(echo, -1, 0) == 0);
 
+   run_command(setenv foo 'setenv monty 1; setenv python 2', 0);
+   run_command(run foo, 0);
+   assert(getenv(monty) != NULL);
+   assert(!strcmp(1, getenv(monty)));
+   assert(getenv(python) != NULL);
+   assert(!strcmp(2, getenv(python)));
+
 #ifdef CONFIG_SYS_HUSH_PARSER
+   run_command(setenv foo 'setenv black 1\nsetenv adder 2', 0);
+   run_command(run foo, 0);
+   assert(getenv(black) != NULL);
+   assert(!strcmp(1, getenv(black)));
+   assert(getenv(adder) != NULL);
+   assert(!strcmp(2, getenv(adder)));
+
/* Test the 'test' command */
 
 #define HUSH_TEST(name, expr, expected_result) \
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH] tools: compiler.h: Fix build on FreeBSD

[Jeroen Hofstee]

Commit 832472 tools: socfpga: Add socfpga preloader signing
to mkimage added tools/socfpga.c which relies on htole32,
le32toh and friends. While compiler.h includes these protypes
for linux from endian.h, it doesn't do so for FreeBSD. Hence
include sys/endian.h for FreeBSD.

Cc: Marek Vasut ma...@denx.de
CC: Tom Rini tr...@ti.com
Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl
---
 include/compiler.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/compiler.h b/include/compiler.h
index 1451916..2103602 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -48,6 +48,10 @@
 # include machine/endian.h
 typedef unsigned long ulong;
 #endif
+#ifdef __FreeBSD__
+# include sys/endian.h /* htole32 and friends */
+#endif
+
 #include time.h
 
 typedef uint8_t __u8;
-- 
2.1.0

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Re: [U-Boot] [ANN] U-Boot v2014.10-rc3 released

[Jeroen Hofstee]

Hello Tom,

On 07-10-14 02:28, Tom Rini wrote:

Hey all,

I've pushed v2014.10-rc4 out to the repository and tarballs should exist
soon.

I've lagged a bit behind in tagging this, but I think we'll be alright
in the end.  I've made
http://patchwork.ozlabs.org/bundle/trini/for-v2014.10-release/ for what
I intend to get in to the release.  If something is in patchwork and not
in there, please reply here and let me know.

As always, if anything is broken please speak up.


The socfpga merge broke builds on FreeBSD at least.
Don't known about Mac OS and other non glibc hosts.
FreeBSD specific patch is at [1].

Regards, Jeroen

http://patchwork.ozlabs.org/patch/397453/

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Re: [U-Boot] [PATCH V5] ARM: mx6: Add support for Kosagi Novena

[Nikolay Dimitrov]

Hi Marek,

I'm marking only the critical issues that are left unfixed from previous 
conversations, to speed-up the process a little bit.
I'll send later patches for the non-critical issues to spare you the 
extra work (and I'm sure my constructive criticism is already boring :D ).



On 10/06/2014 07:02 PM, Marek Vasut wrote:

+#define NOVENA_USB_HUB_RESET   IMX_GPIO_NR(7, 12)

...

+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+   /* Reset USB hub */
+   if (port == 1) {
+   gpio_set_value(NOVENA_USB_HUB_RESET, 0);
+   mdelay(2);
+   gpio_set_value(NOVENA_USB_HUB_RESET, 1);
+   }
+   return 0;
+}
+#endif


As we previously discussed, this pin definition conflicts with 
NOVENA_PCIE_POWER_ON_GPIO (GPIO7_IO12 is connected to PCIE_PWRON), so by 
asserting it, you'll turn-off the wrong sub-system.


Currently the USB hub is reset only by system reset (RESETBMCU asserted 
by the PMIC). I don't see how the CPU can selectively reset the USB hub 
via a GPIO, so it would be better to remove the reset code.


@Sean - can you please confirm/reject this finding?



+#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17)

...

+/*
+ * Audio
+ */
+static iomux_v3_cfg_t audio_pads[] = {
+   /* AUD_PWRON */
+   MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};


The speaker amplifiers will still be disabled, as AUDIO_PWRON is not 
connected to them (R30A is marked as DNP). You need to add one more GPIO 
to enable the speaker amplifiers, here's the fix:


#define NOVENA_AUDIO_PWRON  IMX_GPIO_NR(5, 17)
#define NOVENA_AUDIO_SPK_AMP_ON IMX_GPIO_NR(4, 9)

/*
 * Audio
 */
static iomux_v3_cfg_t audio_pads[] = {
/* AUD_PWRON */
MX6_PAD_KEY_ROW1__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),

/* Speakers' amplifiers #SHDWN  */
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void novena_spl_setup_iomux_audio(void)
{
imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));

gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
gpio_direction_output(NOVENA_AUDIO_SPK_AMP_ON, 1);
}


Side comment: If someone needs to talk to the Audio Codec via I2C3 in 
U-Boot environment, don't be surprised if the codec doesn't respond to 
any I2C requests at all (I've had such issues with SGTL5000). The most 
probable reason is that the codec doesn't receive reference clock from 
imx6 GPIO0. This is not a critical issues as later the kernel muxes this 
GPIO0 properly, but keep this in mind if you want to hack the 
audio-codec at low level.



Reviewed-by: Nikolay Dimitrov picmas...@mail.bg


Kind regards,
Nikolay
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Re: [U-Boot] [PATCH v5 0/15] samsung: Use common config files with Samsung boards

[Minkyu Kang]

On 08/10/14 00:14, Simon Glass wrote:
 Hi Minkyu,
 
 On 7 October 2014 05:24, Minkyu Kang mk7.k...@samsung.com wrote:
 Dear Simon Glass,

 On 06/10/14 03:39, Simon Glass wrote:
 Hi Minkyu,

 On 1 October 2014 21:44, Simon Glass s...@chromium.org wrote:
 Hi Minkyu,

 On 1 October 2014 21:43, Simon Glass s...@chromium.org wrote:
 This series tries to unify the Samsung board configs into a few header
 files for exynos5 and exynos4.

 The purpose is to make it easier to move to driver model. In that case
 I would like things like the GPIO drivers and serial drivers to work in
 a standard way, and not need to support device tree and platform data at
 the same time. That would be quite painful.

 Another reason is that the Chrome OS EC drivers are currently included in
 boards that don't have a Chrome OS EC. This concern was raised by the
 Samsung maintainer (Minkyu) a while back.

 There are still a few boards that don't use CONFIG_OF_CONTROL so I have
 updated these rudimentary of device tree files based on feedback.

 This series has the side-effect of getting the EC interface working
 properly on Pit, so the keyboard works. It also provides access to the
 TPS65090 PMIC, which means that the backlight is enabled.

 Changes in v5:
 - Rebase on top of samsung/master

 Please check this and see if it works for what you need.

 I suppose the merge will be Albert's problem, but I will do a patch
 once I know the detla.

 Actually I see that Albert has pulled this in. So v4 should work for
 you now. I just tried applying it on u-boot-arm/master and it worked
 OK.

 Regards,
 Simon


 Hm, I tried to apply. but failed..

 Applying: Exynos: Use 900MHz ARM frequency in SPL for peach_pit
 Applying: exynos5: Enable data cache
 Applying: cros_ec: power: Add a tunnelled version of the tps65090 driver
 Applying: cros_ec: exynos: Use the correct tps65090 driver in each case
 Applying: dm: exynos: Split out the cros_ec drivers
 Applying: exynos: dts: Add device tree node for cros_ec keyboard
 Applying: exynos: Rename -dt config files to -common
 Applying: exynos: Move common exynos settings into a common file
 Applying: exynos: Move common smdk5420 things to common file
 Applying: exynos: config: Move cros_ec and tps65090 out of smdk boards
 Applying: config: Move arndale to use common exynos5250 file
 Applying: config: Move smdkv310 to use common exynos4 file
 Applying: samsung: Enable device tree for s5p_goni
 error: patch failed: arch/arm/Kconfig:547
 error: arch/arm/Kconfig: patch does not apply
 Patch failed at 0013 samsung: Enable device tree for s5p_goni

 
 It looks like you still haven't synced up with the ARM tree?
 
 In particular there are these patches there that are needed:
 
 f1ef2b6 kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig
 783e6a7 kconfig: move CONFIG_OF_* to Kconfig
 
 I put a bundle here:
 
 http://patchwork.ozlabs.org/bundle/sjg/pitv4/
 
 This should apply OK once you sync up with arm again. If you still
 have problems then, please let me know.
 

No. I've sync with arm tree but it failed.
and I tried to apply on arm tree directly, it also failed.
Please test it.

Thanks,
Minkyu Kang.

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[U-Boot] [PATCH v2 0/4] x86: Enable FIT images on x86

[Simon Glass]

This little series adds support for booting FITs on x86. A FIT is a single
file that can contain a kernel, device tree and ramdisk.

x86 kernels require a setup.bin file to boot. Rather than try to pack this
into the image in a clever way, this series just adds it as another image
in the FIT. At present compression is not supported for the setup binary.

The kernel image can be compressed using FIT's normal compression options,
such as bzip2 and lzo. U-Boot will decompress it as part of the 'bootm'
command.

More work is needed to make this implementation also support a zImage
(which contains a setup.bin and a compressed kernel in a single image) in
the FIT.

The full series is available at:

http://git.denx.de/u-boot-x86.git

in branch 'working'.

Changes in v2:
- Correct setup of setup.bin file
- Move license header to SPDX
- Add a README to explain how to use this feature
- Correct addresses in kernel.its example file

Simon Glass (4):
  x86: Enable LMB and RAMDISK_HIGH by default
  x86: Rewrite bootm.c to make it similar to ARM
  x86: Allow cmdline setup in setup_zimage() to be optional
  x86: Support loading kernel setup from a FIT

 arch/x86/include/asm/bootm.h  |  12 ++
 arch/x86/include/asm/config.h |   3 +
 arch/x86/lib/bootm.c  | 151 +--
 arch/x86/lib/zimage.c |  41 +++
 common/bootm.c|  23 +++-
 common/cmd_bootm.c|   1 +
 common/image-fit.c|  24 +++-
 common/image.c|  11 ++
 doc/uImage.FIT/kernel.its |  50 
 doc/uImage.FIT/source_file_format.txt |  19 +--
 doc/uImage.FIT/x86-fit-boot.txt   | 220 ++
 include/bootstage.h   |   3 +
 include/image.h   |  13 ++
 13 files changed, 498 insertions(+), 73 deletions(-)
 create mode 100644 arch/x86/include/asm/bootm.h
 create mode 100644 doc/uImage.FIT/x86-fit-boot.txt

-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v2 1/4] x86: Enable LMB and RAMDISK_HIGH by default

[Simon Glass]

These options are used by the image code. To allow us to use the generic
code more easily, define these for x86.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v2: None

 arch/x86/include/asm/config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h
index f06a15c..ff15828 100644
--- a/arch/x86/include/asm/config.h
+++ b/arch/x86/include/asm/config.h
@@ -8,4 +8,7 @@
 #define _ASM_CONFIG_H_
 
 #define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #endif
-- 
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[U-Boot] [PATCH v2 4/4] x86: Support loading kernel setup from a FIT

[Simon Glass]

Add a new setup@ section to the FIT which can be used to provide a setup
binary for booting Linux on x86. This makes it possible to boot x86 from
a FIT.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v2:
- Add a README to explain how to use this feature
- Correct addresses in kernel.its example file

 common/bootm.c|  23 +++-
 common/cmd_bootm.c|   1 +
 common/image-fit.c|  24 +++-
 common/image.c|  11 ++
 doc/uImage.FIT/kernel.its |  50 
 doc/uImage.FIT/source_file_format.txt |  19 +--
 doc/uImage.FIT/x86-fit-boot.txt   | 220 ++
 include/bootstage.h   |   3 +
 include/image.h   |  13 ++
 9 files changed, 353 insertions(+), 11 deletions(-)
 create mode 100644 doc/uImage.FIT/x86-fit-boot.txt

diff --git a/common/bootm.c b/common/bootm.c
index ff81a27..17ed389 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -9,6 +9,7 @@
 #include common.h
 #include bootstage.h
 #include bzlib.h
+#include errno.h
 #include fdt_support.h
 #include lmb.h
 #include malloc.h
@@ -83,6 +84,7 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc,
 {
const void *os_hdr;
bool ep_found = false;
+   int ret;
 
/* get kernel image header, start address and length */
os_hdr = boot_get_kernel(cmdtp, flag, argc, argv,
@@ -102,6 +104,7 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int 
argc,
 
images.os.end = image_get_image_end(os_hdr);
images.os.load = image_get_load(os_hdr);
+   images.os.arch = image_get_arch(os_hdr);
break;
 #endif
 #if defined(CONFIG_FIT)
@@ -129,6 +132,13 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int 
argc,
return 1;
}
 
+   if (fit_image_get_arch(images.fit_hdr_os,
+  images.fit_noffset_os,
+  images.os.arch)) {
+   puts(Can't get image ARCH!\n);
+   return 1;
+   }
+
images.os.end = fit_get_end(images.fit_hdr_os);
 
if (fit_image_get_load(images.fit_hdr_os, images.fit_noffset_os,
@@ -156,8 +166,17 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int 
argc,
return 1;
}
 
-   /* find kernel entry point */
-   if (images.legacy_hdr_valid) {
+   /* If we have a valid setup.bin, we will use that for entry (x86) */
+   if (images.os.arch == IH_ARCH_I386) {
+   ulong len;
+
+   ret = boot_get_setup(images, IH_ARCH_I386, images.ep, len);
+   if (ret  0  ret != -ENOENT) {
+   puts(Could not find a valid setup.bin for x86\n);
+   return 1;
+   }
+   /* Kernel entry point is the setup.bin */
+   } else if (images.legacy_hdr_valid) {
images.ep = image_get_ep(images.legacy_hdr_os_copy);
 #if defined(CONFIG_FIT)
} else if (images.fit_uname_os) {
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 843ec6e..6723360 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -12,6 +12,7 @@
 #include bootm.h
 #include command.h
 #include environment.h
+#include errno.h
 #include image.h
 #include lmb.h
 #include malloc.h
diff --git a/common/image-fit.c b/common/image-fit.c
index 255c4ca..2016d1e 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1497,6 +1497,8 @@ static const char *fit_get_image_type_property(int type)
return FIT_KERNEL_PROP;
case IH_TYPE_RAMDISK:
return FIT_RAMDISK_PROP;
+   case IH_TYPE_X86_SETUP:
+   return FIT_SETUP_PROP;
}
 
return unknown;
@@ -1591,7 +1593,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
}
 
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
-#ifndef USE_HOSTCC
+#if !defined(USE_HOSTCC)  !defined(CONFIG_SANDBOX)
if (!fit_image_check_target_arch(fit, noffset)) {
puts(Unsupported Architecture\n);
bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
@@ -1693,3 +1695,23 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 
return noffset;
 }
+
+int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch,
+   ulong *setup_start, ulong *setup_len)
+{
+   int noffset;
+   ulong addr;
+   ulong len;
+   int ret;
+
+   addr = map_to_sysmem(images-fit_hdr_os);
+   noffset = fit_get_node_from_config(images, FIT_SETUP_PROP, addr);
+   if (noffset  0)
+   return noffset;
+
+   ret = fit_image_load(images, addr, NULL, NULL, arch,
+IH_TYPE_X86_SETUP, BOOTSTAGE_ID_FIT_SETUP_START,
+FIT_LOAD_REQUIRED, 

[U-Boot] [PATCH v2 2/4] x86: Rewrite bootm.c to make it similar to ARM

[Simon Glass]

The x86 bootm code is quite special, and geared to zimage. Adjust it
to support device tree and make it more like the ARM code, with
separate bootm stages and functions for each stage.

Create a function announce_and_cleanup() to handle printing the
Starting kernel ... message and put it in bootm so it is in one
place and can be used by any loading code. Also move the
board_final_cleanup() function into bootm.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v2:
- Correct setup of setup.bin file
- Move license header to SPDX

 arch/x86/include/asm/bootm.h |  12 
 arch/x86/lib/bootm.c | 151 +--
 arch/x86/lib/zimage.c|  20 +-
 3 files changed, 130 insertions(+), 53 deletions(-)
 create mode 100644 arch/x86/include/asm/bootm.h

diff --git a/arch/x86/include/asm/bootm.h b/arch/x86/include/asm/bootm.h
new file mode 100644
index 000..033ab79
--- /dev/null
+++ b/arch/x86/include/asm/bootm.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef ARM_BOOTM_H
+#define ARM_BOOTM_H
+
+void bootm_announce_and_cleanup(void);
+
+#endif
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index ff158dd..4c5c7f5 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -10,80 +10,161 @@
 
 #include common.h
 #include command.h
+#include fdt_support.h
 #include image.h
 #include u-boot/zlib.h
 #include asm/bootparam.h
 #include asm/byteorder.h
 #include asm/zimage.h
+#ifdef CONFIG_SYS_COREBOOT
+#include asm/arch/timestamp.h
+#endif
 
 #define COMMAND_LINE_OFFSET 0x9000
 
-/*cmd_boot.c*/
-int do_bootm_linux(int flag, int argc, char * const argv[],
-   bootm_headers_t *images)
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
 {
-   struct boot_params *base_ptr = NULL;
-   ulong os_data, os_len;
-   image_header_t *hdr;
-   void *load_address;
+}
 
-#if defined(CONFIG_FIT)
-   const void  *data;
-   size_t  len;
+void bootm_announce_and_cleanup(void)
+{
+   printf(\nStarting kernel ...\n\n);
+
+#ifdef CONFIG_SYS_COREBOOT
+   timestamp_add_now(TS_U_BOOT_START_KERNEL);
+#endif
+   bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, start_kernel);
+#ifdef CONFIG_BOOTSTAGE_REPORT
+   bootstage_report();
 #endif
+   board_final_cleanup();
+}
 
-   if (flag  BOOTM_STATE_OS_PREP)
-   return 0;
-   if ((flag != 0)  (flag != BOOTM_STATE_OS_GO))
-   return 1;
+#if defined(CONFIG_OF_LIBFDT)  !defined(CONFIG_OF_NO_KERNEL)
+int arch_fixup_memory_node(void *blob)
+{
+   bd_t*bd = gd-bd;
+   int bank;
+   u64 start[CONFIG_NR_DRAM_BANKS];
+   u64 size[CONFIG_NR_DRAM_BANKS];
+
+   for (bank = 0; bank  CONFIG_NR_DRAM_BANKS; bank++) {
+   start[bank] = bd-bi_dram[bank].start;
+   size[bank] = bd-bi_dram[bank].size;
+   }
+
+   return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
+#endif
 
+/* Subcommand: PREP */
+static int boot_prep_linux(bootm_headers_t *images)
+{
+   char *cmd_line_dest = NULL;
+   image_header_t *hdr;
+   int is_zimage = 0;
+   void *data = NULL;
+   size_t len;
+   int ret;
+
+#ifdef CONFIG_OF_LIBFDT
+   if (images-ft_len) {
+   debug(using: FDT\n);
+   if (image_setup_linux(images)) {
+   puts(FDT creation failed! hanging...);
+   hang();
+   }
+   }
+#endif
if (images-legacy_hdr_valid) {
hdr = images-legacy_hdr_os;
if (image_check_type(hdr, IH_TYPE_MULTI)) {
+   ulong os_data, os_len;
+
/* if multi-part image, we need to get first subimage */
image_multi_getimg(hdr, 0, os_data, os_len);
+   data = (void *)os_data;
+   len = os_len;
} else {
/* otherwise get image data */
-   os_data = image_get_data(hdr);
-   os_len = image_get_data_size(hdr);
+   data = (void *)image_get_data(hdr);
+   len = image_get_data_size(hdr);
}
+   is_zimage = 1;
 #if defined(CONFIG_FIT)
-   } else if (images-fit_uname_os) {
-   int ret;
-
+   } else if (images-fit_uname_os  is_zimage) {
ret = fit_image_get_data(images-fit_hdr_os,
-   images-fit_noffset_os, data, len);
+   images-fit_noffset_os,
+   (const void **)data, len);
if (ret) {
puts(Can't get image data/size!\n);
goto error;
}
- 

[U-Boot] [PATCH v2 3/4] x86: Allow cmdline setup in setup_zimage() to be optional

[Simon Glass]

If we are passing this using the device tree then we may not want to
set this up here.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v2: None

 arch/x86/lib/zimage.c | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 1f59bf2..2f0e92f 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -243,18 +243,21 @@ int setup_zimage(struct boot_params *setup_base, char 
*cmd_line, int auto_boot,
hdr-loadflags |= HEAP_FLAG;
}
 
-   if (bootproto = 0x0202) {
-   hdr-cmd_line_ptr = (uintptr_t)cmd_line;
-   } else if (bootproto = 0x0200) {
-   setup_base-screen_info.cl_magic = COMMAND_LINE_MAGIC;
-   setup_base-screen_info.cl_offset =
-   (uintptr_t)cmd_line - (uintptr_t)setup_base;
+   if (cmd_line) {
+   if (bootproto = 0x0202) {
+   hdr-cmd_line_ptr = (uintptr_t)cmd_line;
+   } else if (bootproto = 0x0200) {
+   setup_base-screen_info.cl_magic = COMMAND_LINE_MAGIC;
+   setup_base-screen_info.cl_offset =
+   (uintptr_t)cmd_line - (uintptr_t)setup_base;
+
+   hdr-setup_move_size = 0x9100;
+   }
 
-   hdr-setup_move_size = 0x9100;
+   /* build command line at COMMAND_LINE_OFFSET */
+   build_command_line(cmd_line, auto_boot);
}
 
-   /* build command line at COMMAND_LINE_OFFSET */
-   build_command_line(cmd_line, auto_boot);
return 0;
 }
 
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v2 2/4] ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.

[Xiubo Li]

For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.

Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's
frequency need to config here.

Signed-off-by: Xiubo Li li.xi...@freescale.com
---
 arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
 include/configs/sun7i.h  | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 1ab5d54..30d81db 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -169,11 +169,11 @@ ENTRY(_nonsec_init)
  * we do this here instead.
  * But first check if we have the generic timer.
  */
-#ifdef CONFIG_SYS_CLK_FREQ
+#ifdef CONFIG_TIMER_CLK_FREQ
mrc p15, 0, r0, c0, c1, 1   @ read ID_PFR1
and r0, r0, #CPUID_ARM_GENTIMER_MASK@ mask arch timer bits
cmp r0, #(1  CPUID_ARM_GENTIMER_SHIFT)
-   ldreq   r1, =CONFIG_SYS_CLK_FREQ
+   ldreq   r1, =CONFIG_TIMER_CLK_FREQ
mcreq   p15, 0, r1, c14, c0, 0  @ write CNTFRQ
 #endif
 
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index a902b84..6e201f2f 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -35,6 +35,7 @@
 #define CONFIG_ARMV7_PSCI_NR_CPUS  2
 #define CONFIG_ARMV7_SECURE_BASE   SUNXI_SRAM_B_BASE
 #define CONFIG_SYS_CLK_FREQ2400
+#define CONFIG_SYS_TIMER_CLK_FREQ  CONFIG_SYS_CLK_FREQ
 
 /*
  * Include common sunxi configuration where most the settings are
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 1/4] ARM: HYP/non-sec: add the pen address byte reverting support.

[Xiubo Li]

For some SoCs, the pen address may has different endianness with
the CPUs, so this need the byte revertion for it,

Signed-off-by: Xiubo Li li.xi...@freescale.com
---
 arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 745670e..1ab5d54 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -191,6 +191,9 @@ ENTRY(smp_waitloop)
wfi
ldr r1, =CONFIG_SMP_PEN_ADDR@ load start address
ldr r1, [r1]
+#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
+   rev r1, r1
+#endif
cmp r0, r1  @ make sure we dont execute this code
beq smp_waitloop@ again (due to a spurious wakeup)
mov r0, r1
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 3/4] ls102xa: HYP/non-sec: support for ls102xa boards

[Xiubo Li]

Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function
to set the start address for secondary cores in the LS1021A specific
manner.

Signed-off-by: Xiubo Li li.xi...@freescale.com
---
 arch/arm/cpu/armv7/ls102xa/cpu.c  | 15 +++
 arch/arm/include/asm/arch-ls102xa/config.h|  2 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  3 +++
 include/configs/ls1021aqds.h  |  7 +++
 include/configs/ls1021atwr.h  |  7 +++
 5 files changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index b7dde45..69d1801 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -101,3 +101,18 @@ int cpu_eth_init(bd_t *bis)
 
return 0;
 }
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Setting the address at which secondary cores start from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+   /*
+* After setting the secondary cores start address,
+* just release them to boot.
+*/
+   out_be32(gur-scratchrw[0], addr);
+   out_be32(gur-brrl, 0x2);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index ed78c33..4856388 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -11,6 +11,8 @@
 
 #define OCRAM_BASE_ADDR0x1000
 #define OCRAM_SIZE 0x0002
+#define OCRAM_BASE_S_ADDR  0x1001
+#define OCRAM_S_SIZE   0x0001
 
 #define CONFIG_SYS_IMMR0x0100
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..0bac353 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -17,6 +17,9 @@
 #define SOC_VER_LS1021 0x11
 #define SOC_VER_LS1022 0x12
 
+#define CCSR_BRR_OFFSET0xe4
+#define CCSR_SCRATCHRW1_OFFSET 0x200
+
 #define RCWSR0_SYS_PLL_RAT_SHIFT   25
 #define RCWSR0_SYS_PLL_RAT_MASK0x1f
 #define RCWSR0_MEM_PLL_RAT_SHIFT   16
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 657e3b6..6976cfa 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -324,6 +324,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_CMD_IMLS
 
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_SMP_PEN_ADDR0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ  1250
+#define CONFIG_ARMV7_SECURE_BASE   OCRAM_BASE_S_ADDR
+
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE   128
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272..655b39a 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -227,6 +227,13 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_CMD_IMLS
 
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_SMP_PEN_ADDR0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ  1250
+#define CONFIG_ARMV7_SECURE_BASE   OCRAM_BASE_S_ADDR
+
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE   128
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 0/4] ls102xa: HYP/non-sec: for ls102xa.

[Xiubo Li]

Change for V2:
- All the registers are defined as a struct, here use it.
- Use CONFIG_PEN_ADDR_BIG_ENDIAN instead of CONFIG_SOC_BIG_ENDIAN.


Xiubo Li (4):
  ARM: HYP/non-sec: add the pen address byte reverting support.
  ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
  ls102xa: HYP/non-sec: support for ls102xa boards
  ARM: ls102xa: allow all the peripheral access permissions as R/W.

 arch/arm/cpu/armv7/ls102xa/cpu.c  |  16 +++
 arch/arm/cpu/armv7/nonsec_virt.S  |   7 +-
 arch/arm/include/asm/arch-ls102xa/config.h|   3 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |   3 +
 arch/arm/include/asm/arch-ls102xa/ns_access.h | 118 ++
 board/freescale/common/Makefile   |   2 +
 board/freescale/common/ns_access.c|  32 ++
 board/freescale/ls1021aqds/ls1021aqds.c   |  92 +
 board/freescale/ls1021atwr/ls1021atwr.c   |  91 +
 include/configs/ls1021aqds.h  |   8 ++
 include/configs/ls1021atwr.h  |   8 ++
 include/configs/sun7i.h   |   1 +
 12 files changed, 379 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h
 create mode 100644 board/freescale/common/ns_access.c

-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 4/4] ARM: ls102xa: allow all the peripheral access permissions as R/W.

[Xiubo Li]

The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.

For now we configure all the peripheral access permissions as R/W.

Signed-off-by: Xiubo Li li.xi...@freescale.com
---
 arch/arm/include/asm/arch-ls102xa/config.h|   1 +
 arch/arm/include/asm/arch-ls102xa/ns_access.h | 118 ++
 board/freescale/common/Makefile   |   2 +
 board/freescale/common/ns_access.c|  30 +++
 board/freescale/ls1021aqds/ls1021aqds.c   |  92 
 board/freescale/ls1021atwr/ls1021atwr.c   |  91 
 include/configs/ls1021aqds.h  |   1 +
 include/configs/ls1021atwr.h  |   1 +
 8 files changed, 336 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h
 create mode 100644 board/freescale/common/ns_access.c

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 4856388..0754296 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -18,6 +18,7 @@
 
 #define CONFIG_SYS_FSL_DDR_ADDR(CONFIG_SYS_IMMR + 
0x0008)
 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
+#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x0051)
 #define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0053)
 #define CONFIG_SYS_FSL_ESDHC_ADDR  (CONFIG_SYS_IMMR + 0x0056)
 #define CONFIG_SYS_FSL_SCFG_ADDR   (CONFIG_SYS_IMMR + 0x0057)
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h 
b/arch/arm/include/asm/arch-ls102xa/ns_access.h
new file mode 100644
index 000..b53f699
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_access {
+   CSU_NS_SUP_R = 0x08,
+   CSU_NS_SUP_W = 0x80,
+   CSU_NS_SUP_RW = 0x88,
+   CSU_NS_USER_R = 0x04,
+   CSU_NS_USER_W = 0x40,
+   CSU_NS_USER_RW = 0x44,
+   CSU_S_SUP_R = 0x02,
+   CSU_S_SUP_W = 0x20,
+   CSU_S_SUP_RW = 0x22,
+   CSU_S_USER_R = 0x01,
+   CSU_S_USER_W = 0x10,
+   CSU_S_USER_RW = 0x11,
+   CSU_ALL_RW = 0xff,
+};
+
+enum csu_cslx_ind {
+   CSU_CSLX_PCIE2_IO = 0,
+   CSU_CSLX_PCIE1_IO,
+   CSU_CSLX_MG2TPR_IP,
+   CSU_CSLX_IFC_MEM,
+   CSU_CSLX_OCRAM,
+   CSU_CSLX_GIC,
+   CSU_CSLX_PCIE1,
+   CSU_CSLX_OCRAM2,
+   CSU_CSLX_QSPI_MEM,
+   CSU_CSLX_PCIE2,
+   CSU_CSLX_SATA,
+   CSU_CSLX_USB3,
+   CSU_CSLX_SERDES = 32,
+   CSU_CSLX_QDMA,
+   CSU_CSLX_LPUART2,
+   CSU_CSLX_LPUART1,
+   CSU_CSLX_LPUART4,
+   CSU_CSLX_LPUART3,
+   CSU_CSLX_LPUART6,
+   CSU_CSLX_LPUART5,
+   CSU_CSLX_DSPI2 = 40,
+   CSU_CSLX_DSPI1,
+   CSU_CSLX_QSPI,
+   CSU_CSLX_ESDHC,
+   CSU_CSLX_2D_ACE,
+   CSU_CSLX_IFC,
+   CSU_CSLX_I2C1,
+   CSU_CSLX_USB2,
+   CSU_CSLX_I2C3,
+   CSU_CSLX_I2C2,
+   CSU_CSLX_DUART2 = 50,
+   CSU_CSLX_DUART1,
+   CSU_CSLX_WDT2,
+   CSU_CSLX_WDT1,
+   CSU_CSLX_EDMA,
+   CSU_CSLX_SYS_CNT,
+   CSU_CSLX_DMA_MUX2,
+   CSU_CSLX_DMA_MUX1,
+   CSU_CSLX_DDR,
+   CSU_CSLX_QUICC,
+   CSU_CSLX_DCFG_CCU_RCPM = 60,
+   CSU_CSLX_SECURE_BOOTROM,
+   CSU_CSLX_SFP,
+   CSU_CSLX_TMU,
+   CSU_CSLX_SECURE_MONITOR,
+   CSU_CSLX_RESERVED0,
+   CSU_CSLX_ETSEC1,
+   CSU_CSLX_SEC5_5,
+   CSU_CSLX_ETSEC3,
+   CSU_CSLX_ETSEC2,
+   CSU_CSLX_GPIO2 = 70,
+   CSU_CSLX_GPIO1,
+   CSU_CSLX_GPIO4,
+   CSU_CSLX_GPIO3,
+   CSU_CSLX_PLATFORM_CONT,
+   CSU_CSLX_CSU,
+   CSU_CSLX_ASRC,
+   CSU_CSLX_SPDIF,
+   CSU_CSLX_FLEXCAN2,
+   CSU_CSLX_FLEXCAN1,
+   CSU_CSLX_FLEXCAN4 = 80,
+   CSU_CSLX_FLEXCAN3,
+   CSU_CSLX_SAI2,
+   CSU_CSLX_SAI1,
+   CSU_CSLX_SAI4,
+   CSU_CSLX_SAI3,
+   CSU_CSLX_FTM2,
+   CSU_CSLX_FTM1,
+   CSU_CSLX_FTM4,
+   CSU_CSLX_FTM3,
+   CSU_CSLX_FTM6 = 90,
+   CSU_CSLX_FTM5,
+   CSU_CSLX_FTM8,
+   CSU_CSLX_FTM7,
+   CSU_CSLX_COP_DCSR,
+   CSU_CSLX_EPU,
+   CSU_CSLX_GDI,
+   CSU_CSLX_DDI,
+   CSU_CSLX_RESERVED1,
+   CSU_CSLX_USB3_PHY = 117,
+   CSU_CSLX_RESERVED2,
+   CSU_CSLX_MAX,
+};
+
+struct csu_ns_dev {
+   unsigned long ind;
+   uint32_t val;
+};
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
+
+#endif
diff 

[U-Boot] [PATCH] ARM: LS1021A: Configure device stream id for smmu.

[Xiubo Li]

Signed-off-by: Xiubo Li li.xi...@freescale.com
---
 .../include/asm/arch-ls102xa/ls102xa_stream_id.h   | 17 +
 board/freescale/common/Makefile|  2 ++
 board/freescale/common/ls102xa_stream_id.c | 19 +++
 board/freescale/ls1021aqds/ls1021aqds.c| 22 ++
 board/freescale/ls1021atwr/ls1021atwr.c| 22 ++
 include/configs/ls1021aqds.h   |  2 ++
 include/configs/ls1021atwr.h   |  2 ++
 7 files changed, 86 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
 create mode 100644 board/freescale/common/ls102xa_stream_id.c

diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h 
b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
new file mode 100644
index 000..abd70fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_STREAM_ID_H_
+#define __FSL_LS102XA_STREAM_ID_H_
+
+struct smmu_stream_id {
+   uint16_t offset;
+   uint16_t stream_id;
+   char dev_name[32];
+};
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 7296bbb..726f52c 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -54,6 +54,8 @@ obj-$(CONFIG_VSC_CROSSBAR)+= vsc3316_3308.o
 obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
 obj-$(CONFIG_ZM7300)   += zm7300.o
 
+obj-$(CONFIG_LS102XA_STREAM_ID)+= ls102xa_stream_id.o
+
 # deal with common files for P-series corenet based devices
 obj-$(CONFIG_P2041RDB) += p_corenet/
 obj-$(CONFIG_P3041DS)  += p_corenet/
diff --git a/board/freescale/common/ls102xa_stream_id.c 
b/board/freescale/common/ls102xa_stream_id.c
new file mode 100644
index 000..dd0c710
--- /dev/null
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/ls102xa_stream_id.h
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
+{
+   uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+   int i;
+
+   for (i = 0; i  num; i++) {
+   out_be32(scfg + id[i].offset, id[i].stream_id);
+   }
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index 07df7d2..2021411 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -11,6 +11,7 @@
 #include asm/arch/ns_access.h
 #include asm/arch/clock.h
 #include asm/arch/fsl_serdes.h
+#include asm/arch/ls102xa_stream_id.h
 #include mmc.h
 #include fsl_esdhc.h
 #include fsl_ifc.h
@@ -300,6 +301,24 @@ static struct csu_ns_dev ns_dev[] = {
 };
 #endif
 
+struct smmu_stream_id dev_stream_id[] =
+{
+   { 0x100, 0x01, ETSEC MAC1 },
+   { 0x104, 0x02, ETSEC MAC2 },
+   { 0x108, 0x03, ETSEC MAC3 },
+   { 0x10c, 0x04, PEX1 },
+   { 0x110, 0x05, PEX2 },
+   { 0x114, 0x06, qDMA },
+   { 0x118, 0x07, SATA },
+   { 0x11c, 0x08, USB3 },
+   { 0x120, 0x09, QE },
+   { 0x124, 0x0a, eSDHC },
+   { 0x128, 0x0b, eMA },
+   { 0x14c, 0x0c, 2D-ACE },
+   { 0x150, 0x0d, USB2 },
+   { 0x18c, 0x0e, DEBUG },
+};
+
 int board_init(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -315,6 +334,9 @@ int board_init(void)
config_serdes_mux();
 #endif
 
+   ls102xa_config_smmu_stream_id(dev_stream_id,
+   ARRAY_SIZE(dev_stream_id));
+
 #ifdef CONFIG_SYS_FSL_CSU_ADDR
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 #endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c 
b/board/freescale/ls1021atwr/ls1021atwr.c
index c4d3600..3281277 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -11,6 +11,7 @@
 #include asm/arch/ns_access.h
 #include asm/arch/clock.h
 #include asm/arch/fsl_serdes.h
+#include asm/arch/ls102xa_stream_id.h
 #include mmc.h
 #include fsl_esdhc.h
 #include fsl_ifc.h
@@ -357,6 +358,24 @@ static struct csu_ns_dev ns_dev[] = {
 };
 #endif
 
+struct smmu_stream_id dev_stream_id[] =
+{
+   { 0x100, 0x01, ETSEC MAC1 },
+   { 0x104, 0x02, ETSEC MAC2 },
+   { 0x108, 0x03, ETSEC MAC3 },
+   { 0x10c, 0x04, PEX1 },
+   { 0x110, 0x05, PEX2 },
+   { 0x114, 0x06, qDMA },
+   { 0x118, 0x07, SATA },
+   { 0x11c, 0x08, USB3 },
+   { 0x120, 0x09, QE },
+   { 0x124, 0x0a, eSDHC },
+   { 0x128, 0x0b, eMA },
+   { 0x14c, 0x0c, 2D-ACE },
+   { 0x150, 0x0d, USB2 },
+   { 0x18c, 0x0e, DEBUG },
+};
+
 int 

[U-Boot] [PATCH v6 0/15] samsung: Use common config files with Samsung boards

[Simon Glass]

This series tries to unify the Samsung board configs into a few header
files for exynos5 and exynos4.

The purpose is to make it easier to move to driver model. In that case
I would like things like the GPIO drivers and serial drivers to work in
a standard way, and not need to support device tree and platform data at
the same time. That would be quite painful.

Another reason is that the Chrome OS EC drivers are currently included in
boards that don't have a Chrome OS EC. This concern was raised by the
Samsung maintainer (Minkyu) a while back.

There are still a few boards that don't use CONFIG_OF_CONTROL so I have
updated these rudimentary of device tree files based on feedback.

This series has the side-effect of getting the EC interface working
properly on Pit, so the keyboard works. It also provides access to the
TPS65090 PMIC, which means that the backlight is enabled.

Changes in v6:
- Rebase on top of samsung/master and 'git pull upstream-arm master'

Changes in v4:
- Address review nits from Minkyu
- Make this driver more like the one it came from
- Rebase on top of master (CONFIG_OF settings moved to Kconfig)
- Remove special FET_ERR_NOT_READY etc. as use standard errors

Changes in v3:
- Adjust device tree file based on Robert Baldyga's example

Changes in v2:
- Add new patch to enable keyboard on pit
- Add new patch to split out cros_ec drivers
- Add new patch to use 900MHz ARM frequeny in SPL for peach_pit
- Avoid using a common file, and just add a device tree
- Don't enable the cros_ec on smdk5420
- Fix 'cashe' typo in commit subject
- Fix device tree base addresses
- Leave CONFIG_SERIAL3 in the individual board files
- Leave in a few configs which are not in fact common to all boards
- Reduce the number of common elements to avoid needing #undefs later
- Slightly reword the commit message

Simon Glass (15):
  Exynos: Use 900MHz ARM frequency in SPL for peach_pit
  exynos5: Enable data cache
  cros_ec: power: Add a tunnelled version of the tps65090 driver
  cros_ec: exynos: Use the correct tps65090 driver in each case
  dm: exynos: Split out the cros_ec drivers
  exynos: dts: Add device tree node for cros_ec keyboard
  exynos: Rename -dt config files to -common
  exynos: Move common exynos settings into a common file
  exynos: Move common smdk5420 things to common file
  exynos: config: Move cros_ec and tps65090 out of smdk boards
  config: Move arndale to use common exynos5250 file
  config: Move smdkv310 to use common exynos4 file
  samsung: Enable device tree for s5p_goni
  samsung: Enable device tree for smdkc100
  exynos: Enable pre-relocation malloc()

 arch/arm/Kconfig   |  13 +-
 arch/arm/cpu/armv7/exynos/Kconfig  |   1 +
 arch/arm/cpu/armv7/s5pc1xx/Kconfig |  25 +++
 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/exynos4210-smdkv310.dts   |  21 ++
 arch/arm/dts/exynos5420-peach-pit.dts  |  57 +-
 arch/arm/dts/s5pc1xx-goni.dts  |  28 +++
 arch/arm/dts/s5pc1xx-smdkc100.dts  |  29 +++
 arch/arm/include/asm/arch-s5pc1xx/periph.h |  61 ++
 arch/arm/include/asm/arch-s5pc1xx/pinmux.h |  50 +
 configs/s5p_goni_defconfig |   2 +
 configs/smdkc100_defconfig |   2 +
 configs/smdkv310_defconfig |   1 +
 drivers/mmc/s5p_sdhci.c|   2 -
 drivers/power/pmic/Makefile|   3 +-
 drivers/power/pmic/pmic_tps65090_ec.c  | 218 +
 include/configs/arndale.h  | 195 +-
 include/configs/{exynos4-dt.h = exynos-common.h}  | 110 +++
 include/configs/exynos4-common.h   |  68 +++
 include/configs/{exynos5-dt.h = exynos5-common.h} | 126 ++--
 include/configs/exynos5-dt-common.h|  35 
 .../{exynos5250-dt.h = exynos5250-common.h}   |   7 +-
 .../configs/{exynos5420.h = exynos5420-common.h}  |  22 ++-
 include/configs/odroid.h   |   4 +-
 include/configs/origen.h   |   5 +-
 include/configs/peach-pit.h|  16 +-
 include/configs/s5p_goni.h |   9 +-
 include/configs/s5pc210_universal.h|   5 +-
 include/configs/smdk5250.h |  23 ++-
 include/configs/smdk5420.h |   5 +-
 include/configs/smdkc100.h |   6 +
 include/configs/smdkv310.h |  61 +-
 include/configs/snow.h |  25 ++-
 include/configs/trats.h|   6 +-
 include/configs/trats2.h   |   6 +-
 35 files changed, 760 insertions(+), 490 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/s5pc1xx/Kconfig
 create mode 100644 arch/arm/dts/exynos4210-smdkv310.dts
 

Re: [U-Boot] [PATCH v5 0/15] samsung: Use common config files with Samsung boards

[Simon Glass]

Hi Minkyu,

On 7 October 2014 19:09, Minkyu Kang mk7.k...@samsung.com wrote:
 On 08/10/14 00:14, Simon Glass wrote:
 Hi Minkyu,

 On 7 October 2014 05:24, Minkyu Kang mk7.k...@samsung.com wrote:
 Dear Simon Glass,

 On 06/10/14 03:39, Simon Glass wrote:
 Hi Minkyu,

 On 1 October 2014 21:44, Simon Glass s...@chromium.org wrote:
 Hi Minkyu,

 On 1 October 2014 21:43, Simon Glass s...@chromium.org wrote:
 This series tries to unify the Samsung board configs into a few header
 files for exynos5 and exynos4.

 The purpose is to make it easier to move to driver model. In that case
 I would like things like the GPIO drivers and serial drivers to work in
 a standard way, and not need to support device tree and platform data at
 the same time. That would be quite painful.

 Another reason is that the Chrome OS EC drivers are currently included in
 boards that don't have a Chrome OS EC. This concern was raised by the
 Samsung maintainer (Minkyu) a while back.

 There are still a few boards that don't use CONFIG_OF_CONTROL so I have
 updated these rudimentary of device tree files based on feedback.

 This series has the side-effect of getting the EC interface working
 properly on Pit, so the keyboard works. It also provides access to the
 TPS65090 PMIC, which means that the backlight is enabled.

 Changes in v5:
 - Rebase on top of samsung/master

 Please check this and see if it works for what you need.

 I suppose the merge will be Albert's problem, but I will do a patch
 once I know the detla.

 Actually I see that Albert has pulled this in. So v4 should work for
 you now. I just tried applying it on u-boot-arm/master and it worked
 OK.

 Regards,
 Simon


 Hm, I tried to apply. but failed..

 Applying: Exynos: Use 900MHz ARM frequency in SPL for peach_pit
 Applying: exynos5: Enable data cache
 Applying: cros_ec: power: Add a tunnelled version of the tps65090 driver
 Applying: cros_ec: exynos: Use the correct tps65090 driver in each case
 Applying: dm: exynos: Split out the cros_ec drivers
 Applying: exynos: dts: Add device tree node for cros_ec keyboard
 Applying: exynos: Rename -dt config files to -common
 Applying: exynos: Move common exynos settings into a common file
 Applying: exynos: Move common smdk5420 things to common file
 Applying: exynos: config: Move cros_ec and tps65090 out of smdk boards
 Applying: config: Move arndale to use common exynos5250 file
 Applying: config: Move smdkv310 to use common exynos4 file
 Applying: samsung: Enable device tree for s5p_goni
 error: patch failed: arch/arm/Kconfig:547
 error: arch/arm/Kconfig: patch does not apply
 Patch failed at 0013 samsung: Enable device tree for s5p_goni


 It looks like you still haven't synced up with the ARM tree?

 In particular there are these patches there that are needed:

 f1ef2b6 kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig
 783e6a7 kconfig: move CONFIG_OF_* to Kconfig

 I put a bundle here:

 http://patchwork.ozlabs.org/bundle/sjg/pitv4/

 This should apply OK once you sync up with arm again. If you still
 have problems then, please let me know.


 No. I've sync with arm tree but it failed.
 and I tried to apply on arm tree directly, it also failed.
 Please test it.

Having a bit of a guess at what you are doing, since samsung/master
still is not synced with arm/master.

I tried this:

git checkout -b try-samsung samsung/master
git pull upstream-arm master

and then applied the patches on top of this without errors. Maybe git
is automatically fixing them up?

I'll send a v6 second with the resulting patches, If that doesn't
work, can I ask you please to push your branch to samsung/master so I
can be sure of what your base is?

Regards,
Simon
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[U-Boot] [PATCH v6 05/15] dm: exynos: Split out the cros_ec drivers

[Simon Glass]

With the driver model conversion we are going to be using driver model for
SPI and not for I2C. This works OK so long as a board doesn't need both
dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow
uses I2C we need to split the configs so that only one driver is compiled
for each platform.

We can fix this later when driver model supports I2C.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add new patch to split out cros_ec drivers
- Don't enable the cros_ec on smdk5420

 include/configs/exynos5-dt.h| 2 --
 include/configs/exynos5250-dt.h | 2 ++
 include/configs/peach-pit.h | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index 68f3a41..0c400b1 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -69,8 +69,6 @@
 
 /* Enable keyboard */
 #define CONFIG_CROS_EC /* CROS_EC protocol */
-#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
-#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
 #define CONFIG_CROS_EC_KEYB/* CROS_EC keyboard input */
 #define CONFIG_CMD_CROS_EC
 #define CONFIG_KEYBOARD
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 5504515..05d33a7 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -22,6 +22,8 @@
 
 #define CONFIG_SPL_MAX_FOOTPRINT   (14 * 1024)
 
+#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
+
 /* USB */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_XHCI
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 34734ad..8db889c 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -31,5 +31,6 @@
 #endif
 
 #define CONFIG_POWER_TPS65090_EC
+#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
 
 #endif /* __CONFIG_PEACH_PIT_H */
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v6 04/15] cros_ec: exynos: Use the correct tps65090 driver in each case

[Simon Glass]

Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards
cannot due to a hardware design decision. Select the correct driver to use
in each case.

Signed-off-by: Simon Glass s...@chromium.org
Tested-by: Ajay Kumar ajaykumar...@samsung.com
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Don't enable the cros_ec on smdk5420
- Slightly reword the commit message

 drivers/power/pmic/Makefile | 2 +-
 include/configs/exynos5250-dt.h | 1 +
 include/configs/peach-pit.h | 2 ++
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 0b76611..e7b07eb 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
 obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
-obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
+obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
 obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
 obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
 obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index c24984b..5504515 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -42,6 +42,7 @@
 
 /* PMIC */
 #define CONFIG_POWER_MAX77686
+#define CONFIG_POWER_TPS65090_I2C
 
 /* Sound */
 #define CONFIG_CMD_SOUND
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 987cef5..34734ad 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -30,4 +30,6 @@
 #define LCD_BPPLCD_COLOR16
 #endif
 
+#define CONFIG_POWER_TPS65090_EC
+
 #endif /* __CONFIG_PEACH_PIT_H */
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v6 03/15] cros_ec: power: Add a tunnelled version of the tps65090 driver

[Simon Glass]

Unfortunately on Pit the AP has no direct access to the tps65090 but must
talk through the EC (over SPI) to the EC's I2C bus.

When driver model supports PMICs this will be relatively easy. In the
meantime the best approach is to duplicate the driver. It will be refactored
once driver model support is expanded.

Signed-off-by: Simon Glass s...@chromium.org
Tested-by: Ajay Kumar ajaykumar...@samsung.com
---

Changes in v6: None
Changes in v4:
- Address review nits from Minkyu
- Make this driver more like the one it came from
- Remove special FET_ERR_NOT_READY etc. as use standard errors

Changes in v3: None
Changes in v2: None

 drivers/power/pmic/Makefile   |   1 +
 drivers/power/pmic/pmic_tps65090_ec.c | 218 ++
 2 files changed, 219 insertions(+)
 create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c

diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index a472f61..0b76611 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
 obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
+obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
 obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
 obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
 obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_tps65090_ec.c 
b/drivers/power/pmic/pmic_tps65090_ec.c
new file mode 100644
index 000..ac0d44f
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65090_ec.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include cros_ec.h
+#include errno.h
+#include power/tps65090_pmic.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TPS65090_ADDR  0x48
+
+static struct tps65090 {
+   struct cros_ec_dev *dev;/* The CROS_EC device */
+} config;
+
+/* TPS65090 register addresses */
+enum {
+   REG_IRQ1 = 0,
+   REG_CG_CTRL0 = 4,
+   REG_CG_STATUS1 = 0xa,
+   REG_FET1_CTRL = 0x0f,
+   REG_FET2_CTRL,
+   REG_FET3_CTRL,
+   REG_FET4_CTRL,
+   REG_FET5_CTRL,
+   REG_FET6_CTRL,
+   REG_FET7_CTRL,
+   TPS65090_NUM_REGS,
+};
+
+enum {
+   IRQ1_VBATG = 1  3,
+   CG_CTRL0_ENC_MASK   = 0x01,
+
+   MAX_FET_NUM = 7,
+   MAX_CTRL_READ_TRIES = 5,
+
+   /* TPS65090 FET_CTRL register values */
+   FET_CTRL_TOFET  = 1  7,  /* Timeout, startup, overload */
+   FET_CTRL_PGFET  = 1  4,  /* Power good for FET status */
+   FET_CTRL_WAIT   = 3  2,  /* Overcurrent timeout max */
+   FET_CTRL_ADENFET= 1  1,  /* Enable output auto discharge */
+   FET_CTRL_ENFET  = 1  0,  /* Enable FET */
+};
+
+/**
+ * tps65090_read - read a byte from tps6090
+ *
+ * @param reg  The register address to read from.
+ * @param val  We'll return value value read here.
+ * @return 0 if ok; error if EC returns failure.
+ */
+static int tps65090_read(u32 reg, u8 *val)
+{
+   return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,
+   val, 1, true);
+}
+
+/**
+ * tps65090_write - write a byte to tps6090
+ *
+ * @param reg  The register address to write to.
+ * @param val  The value to write.
+ * @return 0 if ok; error if EC returns failure.
+ */
+static int tps65090_write(u32 reg, u8 val)
+{
+   return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,
+   val, 1, false);
+}
+
+/**
+ * Checks for a valid FET number
+ *
+ * @param fet_id   FET number to check
+ * @return 0 if ok, -EINVAL if FET value is out of range
+ */
+static int tps65090_check_fet(unsigned int fet_id)
+{
+   if (fet_id == 0 || fet_id  MAX_FET_NUM) {
+   debug(parameter fet_id is out of range, %u not in 1 ~ %u\n,
+ fet_id, MAX_FET_NUM);
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+/**
+ * Set the power state for a FET
+ *
+ * @param fet_id   Fet number to set (1..MAX_FET_NUM)
+ * @param set  1 to power on FET, 0 to power off
+ * @return -EIO if we got a comms error, -EAGAIN if the FET failed to
+ * change state. If all is ok, returns 0.
+ */
+static int tps65090_fet_set(int fet_id, bool set)
+{
+   int retry;
+   u8 reg, value;
+
+   value = FET_CTRL_ADENFET | FET_CTRL_WAIT;
+   if (set)
+   value |= FET_CTRL_ENFET;
+
+   if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value))
+   return -EIO;
+
+   /* Try reading until we get a result */
+   for (retry = 0; retry  MAX_CTRL_READ_TRIES; retry++) {
+   if (tps65090_read(REG_FET1_CTRL + fet_id - 1, reg))
+   return -EIO;
+
+   /* Check that the fet went into the expected state */
+   

[U-Boot] [PATCH v6 09/15] exynos: Move common smdk5420 things to common file

[Simon Glass]

A few things are common but are not in the common file. Fix this and
rename the file to fit with the other exynos*-common files.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Leave CONFIG_SERIAL3 in the individual board files
- Reduce the number of common elements to avoid needing #undefs later

 include/configs/{exynos5420.h = exynos5420-common.h} | 8 +++-
 include/configs/peach-pit.h   | 4 +---
 include/configs/smdk5420.h| 4 +---
 3 files changed, 5 insertions(+), 11 deletions(-)
 rename include/configs/{exynos5420.h = exynos5420-common.h} (88%)

diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420-common.h
similarity index 88%
rename from include/configs/exynos5420.h
rename to include/configs/exynos5420-common.h
index d2a9556..27e7edc 100644
--- a/include/configs/exynos5420.h
+++ b/include/configs/exynos5420-common.h
@@ -9,7 +9,9 @@
 #ifndef __CONFIG_EXYNOS5420_H
 #define __CONFIG_EXYNOS5420_H
 
-#define CONFIG_EXYNOS5420  /* which is in a Exynos5 Family */
+#define CONFIG_EXYNOS5420
+
+#include configs/exynos5-common.h
 
 #define MACH_TYPE_SMDK5420 8002
 #define CONFIG_MACH_TYPE   MACH_TYPE_SMDK5420
@@ -31,10 +33,6 @@
 
 #define CONFIG_MAX_I2C_NUM 11
 
-/* Enable FIT support and comparison */
-#define CONFIG_FIT
-#define CONFIG_FIT_BEST_MATCH
-
 #define CONFIG_BOARD_REV_GPIO_COUNT2
 
 #define CONFIG_BOOTCOMMAND mmc read 20007000 451 2000; bootm 20007000
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 5e428cc..e9736fc 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -9,9 +9,7 @@
 #ifndef __CONFIG_PEACH_PIT_H
 #define __CONFIG_PEACH_PIT_H
 
-#include configs/exynos5-common.h
-
-#include configs/exynos5420.h
+#include configs/exynos5420-common.h
 
 
 /* select serial console configuration */
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index abda141..894ed11 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -9,9 +9,7 @@
 #ifndef __CONFIG_SMDK5420_H
 #define __CONFIG_SMDK5420_H
 
-#include configs/exynos5-common.h
-
-#include configs/exynos5420.h
+#include configs/exynos5420-common.h
 
 #define CONFIG_SMDK5420/* which is in a SMDK5420 */
 
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v6 06/15] exynos: dts: Add device tree node for cros_ec keyboard

[Simon Glass]

Add a keyboard definition so that the keyboard can be used on pit.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add new patch to enable keyboard on pit

 arch/arm/dts/exynos5420-peach-pit.dts | 55 +++
 1 file changed, 55 insertions(+)

diff --git a/arch/arm/dts/exynos5420-peach-pit.dts 
b/arch/arm/dts/exynos5420-peach-pit.dts
index 207782e..995e62b 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -28,6 +28,61 @@
pmic = /i2c@12ca;
};
 
+   cros-ec-keyb {
+   compatible = google,cros-ec-keyb;
+   google,key-rows = 8;
+   google,key-columns = 13;
+   google,repeat-delay-ms = 240;
+   google,repeat-rate-ms = 30;
+   google,ghost-filter;
+   /*
+* Keymap entries take the form of 0xRRCC where
+* RR=Row CC=Column =Key Code
+* The values below are for a US keyboard layout and
+* are taken from the Linux driver. Note that the
+* 102ND key is not used for US keyboards.
+*/
+   linux,keymap = 
+   /* CAPSLCK F1 B  F10 */
+   0x0001003a 0x0002003b 0x00030030 0x00040044
+   /* N   =  R_ALT  ESC */
+   0x00060031 0x0008000d 0x000a0064 0x01010001
+   /* F4  G  F7 H   */
+   0x0102003e 0x01030022 0x01040041 0x01060023
+   /* '   F9 BKSPACEL_CTRL  */
+   0x01080028 0x01090043 0x010b000e 0x021d
+   /* TAB F3 T  F6  */
+   0x0201000f 0x0202003d 0x02030014 0x02040040
+   /* ]   Y  102ND  [   */
+   0x0205001b 0x02060015 0x02070056 0x0208001a
+   /* F8  GRAVE  F2 5   */
+   0x02090042 0x03010029 0x0302003c 0x03030006
+   /* F5  6  -  \   */
+   0x0304003f 0x03060007 0x0308000c 0x030b002b
+   /* R_CTRL  A  D  F   */
+   0x0461 0x0401001e 0x04020020 0x04030021
+   /* S   K  J  ;   */
+   0x0404001f 0x04050025 0x04060024 0x04080027
+   /* L   ENTER  Z  C   */
+   0x04090026 0x040b001c 0x0501002c 0x0502002e
+   /* V   X  ,  M   */
+   0x0503002f 0x0504002d 0x05050033 0x05060032
+   /* L_SHIFT /  .  SPACE   */
+   0x0507002a 0x05080035 0x05090034 0x050B0039
+   /* 1   3  4  2   */
+   0x06010002 0x06020004 0x06030005 0x06040003
+   /* 8   7  0  9   */
+   0x06050009 0x06060008 0x0608000b 0x0609000a
+   /* L_ALT   DOWN   RIGHT  Q   */
+   0x060a0038 0x060b006c 0x060c006a 0x07010010
+   /* E   R  W  I   */
+   0x07020012 0x07030013 0x07040011 0x07050017
+   /* U   R_SHIFTP  O   */
+   0x07060016 0x07070036 0x07080019 0x07090018
+   /* UP  LEFT*/
+   0x070b0067 0x070c0069;
+   };
+
dmc {
mem-manuf = samsung;
mem-type = ddr3;
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v6 08/15] exynos: Move common exynos settings into a common file

[Simon Glass]

Since exynos4 and exyno5 share many settings, we should move these into
a common file to avoid duplication.

In effect the changes are that all exynos boards now have EXT4 and FAT
write support. This affects exynos5250 and exynos5420 which previously
did not. This also disables the ext2 commands which are equivalent to
ext4 anyway.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4:
- Rebase on top of master (CONFIG_OF settings moved to Kconfig)

Changes in v3: None
Changes in v2:
- Reduce the number of common elements to avoid needing #undefs later

 include/configs/exynos-common.h | 91 +
 include/configs/exynos4-common.h| 77 +--
 include/configs/exynos5-common.h| 86 +--
 include/configs/origen.h|  3 --
 include/configs/s5pc210_universal.h |  3 --
 include/configs/smdk5250.h  |  4 --
 include/configs/snow.h  |  4 --
 include/configs/trats.h |  4 --
 include/configs/trats2.h|  4 --
 9 files changed, 105 insertions(+), 171 deletions(-)
 create mode 100644 include/configs/exynos-common.h

diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
new file mode 100644
index 000..7b9eda4
--- /dev/null
+++ b/include/configs/exynos-common.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Common configuration settings for the SAMSUNG EXYNOS boards.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __EXYNOS_COMMON_H
+#define __EXYNOS_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+
+#include asm/arch/cpu.h  /* get chip and board defs */
+#include linux/sizes.h
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Enable fdt support */
+#define CONFIG_OF_LIBFDT
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_CMD_CACHE
+
+/* input clock of PLL: 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ2400
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_ENV_OVERWRITE
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (80 * SZ_1M))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE115200
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_S5P_SDHCI
+#define CONFIG_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_BOOTDELAY   3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Command definition*/
+#include config_cmd_default.h
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use hush command parser*/
+#define CONFIG_SYS_CBSIZE  256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE  384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16  /* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index 38b8961..972add4 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -9,81 +9,29 @@
 #ifndef __CONFIG_EXYNOS4_COMMON_H
 #define __CONFIG_EXYNOS4_COMMON_H
 
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P /* S5P Family */
-#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */
+#define CONFIG_EXYNOS4 /* Exynos4 Family */
 
-#include asm/arch/cpu.h  /* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_COMMON
-#define CONFIG_SYS_GENERIC_BOARD
+#include exynos-common.h
 
 #define CONFIG_SYS_CACHELINE_SIZE  32
-
-/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ2400
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
 #define 

[U-Boot] [PATCH v6 13/15] samsung: Enable device tree for s5p_goni

[Simon Glass]

Change this board to add a device tree.

This also adds a pinmux header file although it is not used as yet.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4:
- Rebase on top of master (CONFIG_OF settings moved to Kconfig)

Changes in v3:
- Adjust device tree file based on Robert Baldyga's example

Changes in v2:
- Avoid using a common file, and just add a device tree
- Fix device tree base addresses

 arch/arm/Kconfig   |  9 +++--
 arch/arm/cpu/armv7/s5pc1xx/Kconfig | 20 ++
 arch/arm/dts/Makefile  |  1 +
 arch/arm/dts/s5pc1xx-goni.dts  | 28 ++
 arch/arm/include/asm/arch-s5pc1xx/periph.h | 61 ++
 arch/arm/include/asm/arch-s5pc1xx/pinmux.h | 50 
 configs/s5p_goni_defconfig |  2 +
 drivers/mmc/s5p_sdhci.c|  2 -
 include/configs/s5p_goni.h |  4 +-
 9 files changed, 170 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/s5pc1xx/Kconfig
 create mode 100644 arch/arm/dts/s5pc1xx-goni.dts
 create mode 100644 arch/arm/include/asm/arch-s5pc1xx/periph.h
 create mode 100644 arch/arm/include/asm/arch-s5pc1xx/pinmux.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 43ba33a..22ceb9d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -336,6 +336,9 @@ config TARGET_BCM958622HR
 config ARCH_EXYNOS
bool Samsung EXYNOS
 
+config ARCH_S5PC1XX
+   bool Samsung S5PC1XX
+
 config ARCH_HIGHBANK
bool Calxeda Highbank
 
@@ -429,9 +432,6 @@ config RMOBILE
 config TARGET_CM_FX6
bool Support cm_fx6
 
-config TARGET_S5P_GONI
-   bool Support s5p_goni
-
 config TARGET_SMDKC100
bool Support smdkc100
 
@@ -550,6 +550,8 @@ source arch/arm/cpu/arm926ejs/orion5x/Kconfig
 
 source arch/arm/cpu/armv7/rmobile/Kconfig
 
+source arch/arm/cpu/armv7/s5pc1xx/Kconfig
+
 source arch/arm/cpu/armv7/tegra-common/Kconfig
 
 source arch/arm/cpu/armv7/uniphier/Kconfig
@@ -657,7 +659,6 @@ source board/raspberrypi/rpi_b/Kconfig
 source board/ronetix/pm9261/Kconfig
 source board/ronetix/pm9263/Kconfig
 source board/ronetix/pm9g45/Kconfig
-source board/samsung/goni/Kconfig
 source board/samsung/smdk2410/Kconfig
 source board/samsung/smdkc100/Kconfig
 source board/sandisk/sansa_fuze_plus/Kconfig
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig 
b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
new file mode 100644
index 000..1a8941d
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_S5PC1XX
+
+choice
+   prompt S5PC1XX board select
+
+config TARGET_S5P_GONI
+   bool S5P Goni board
+   select OF_CONTROL if !SPL_BUILD
+
+endchoice
+
+config SYS_CPU
+   default armv7
+
+config SYS_SOC
+   default s5pc1xx
+
+source board/samsung/goni/Kconfig
+
+endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 43a70e4..076e0f7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-universal_c210.dtb \
diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts
new file mode 100644
index 000..2e671bb
--- /dev/null
+++ b/arch/arm/dts/s5pc1xx-goni.dts
@@ -0,0 +1,28 @@
+/*
+ * Samsung's S5PC110-based Goni board device tree source
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include skeleton.dtsi
+
+/ {
+   model = Samsung Goni based on S5PC110;
+   compatible = samsung,goni, samsung,s5pc110;
+
+   aliases {
+   serial2 = /serial@e2900800;
+   console = /serial@e2900800;
+   };
+
+   serial@e2900800 {
+   compatible = samsung,exynos4210-uart;
+   reg = 0xe2900800 0x400;
+   id = 2;
+   };
+
+};
diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h 
b/arch/arm/include/asm/arch-s5pc1xx/periph.h
new file mode 100644
index 000..5c1c3d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-s5pc1xx/periph.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde rajeshwar...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+   PERIPH_ID_UART0 = 51,
+   PERIPH_ID_UART1,
+   PERIPH_ID_UART2,
+   PERIPH_ID_UART3,
+   PERIPH_ID_I2C0 = 56,
+   PERIPH_ID_I2C1,
+   PERIPH_ID_I2C2,
+   PERIPH_ID_I2C3,
+   PERIPH_ID_I2C4,
+   PERIPH_ID_I2C5,
+   PERIPH_ID_I2C6,
+   PERIPH_ID_I2C7,
+   PERIPH_ID_SPI0 = 68,
+   PERIPH_ID_SPI1,
+   PERIPH_ID_SPI2,
+   PERIPH_ID_SDMMC0 = 75,

[U-Boot] [PATCH v6 02/15] exynos5: Enable data cache

[Simon Glass]

Things run faster when the data cache is enabled, so turn it on along with
the 'dcache' command.

Signed-off-by: Simon Glass s...@chromium.org
Tested-by: Ajay Kumar ajaykumar...@samsung.com
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix 'cashe' typo in commit subject

 include/configs/exynos5-dt.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index 1dc3002..68f3a41 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -33,8 +33,8 @@
 #define CONFIG_TRACE_EARLY_ADDR0x5000
 
 /* Keep L2 Cache Disabled */
-#define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE  64
+#define CONFIG_CMD_CACHE
 
 /* Enable ACE acceleration for SHA1 and SHA256 */
 #define CONFIG_EXYNOS_ACE_SHA
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v6 10/15] exynos: config: Move cros_ec and tps65090 out of smdk boards

[Simon Glass]

These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so
move the settings into a separate common file to be used by those that need
it.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/exynos5-common.h| 18 +++---
 include/configs/exynos5-dt-common.h | 35 +++
 include/configs/exynos5250-common.h |  3 ---
 include/configs/peach-pit.h |  1 +
 include/configs/snow.h  |  4 
 5 files changed, 43 insertions(+), 18 deletions(-)
 create mode 100644 include/configs/exynos5-dt-common.h

diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 380a46f..3581a38 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -48,17 +48,10 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_CONSOLE_MUX
 
-/* Enable keyboard */
-#define CONFIG_CROS_EC /* CROS_EC protocol */
-#define CONFIG_CROS_EC_KEYB/* CROS_EC keyboard input */
-#define CONFIG_CMD_CROS_EC
-#define CONFIG_KEYBOARD
-
-/* Console configuration */
 #define EXYNOS_DEVICE_SETTINGS \
-   stdin=serial,cros-ec-keyb\0 \
-   stdout=serial,lcd\0 \
-   stderr=serial,lcd\0
+   stdin=serial\0 \
+   stdout=serial\0 \
+   stderr=serial\0
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
EXYNOS_DEVICE_SETTINGS
@@ -185,11 +178,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ  5000
 #endif
 
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_TPS65090
-
 /* Ethernet Controllor Driver */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_SMC911X
diff --git a/include/configs/exynos5-dt-common.h 
b/include/configs/exynos5-dt-common.h
new file mode 100644
index 000..66547fa
--- /dev/null
+++ b/include/configs/exynos5-dt-common.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * Configuration settings for generic Exynos 5 board
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS5_DT_COMMON_H
+#define __CONFIG_EXYNOS5_DT_COMMON_H
+
+#include exynos5-common.h
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_TPS65090
+
+/* Enable keyboard */
+#define CONFIG_CROS_EC /* CROS_EC protocol */
+#define CONFIG_CROS_EC_KEYB/* CROS_EC keyboard input */
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_KEYBOARD
+
+/* Console configuration */
+#undef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+   stdin=serial,cros-ec-keyb\0 \
+   stdout=serial,lcd\0 \
+   stderr=serial,lcd\0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   EXYNOS_DEVICE_SETTINGS
+
+#endif
diff --git a/include/configs/exynos5250-common.h 
b/include/configs/exynos5250-common.h
index b4c1ccf..987eb15 100644
--- a/include/configs/exynos5250-common.h
+++ b/include/configs/exynos5250-common.h
@@ -22,8 +22,6 @@
 
 #define CONFIG_SPL_MAX_FOOTPRINT   (14 * 1024)
 
-#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
-
 /* USB */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_XHCI
@@ -44,7 +42,6 @@
 
 /* PMIC */
 #define CONFIG_POWER_MAX77686
-#define CONFIG_POWER_TPS65090_I2C
 
 /* Sound */
 #define CONFIG_CMD_SOUND
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index e9736fc..046813d 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -10,6 +10,7 @@
 #define __CONFIG_PEACH_PIT_H
 
 #include configs/exynos5420-common.h
+#include configs/exynos5-dt-common.h
 
 
 /* select serial console configuration */
diff --git a/include/configs/snow.h b/include/configs/snow.h
index 0834cc9..dc09c66 100644
--- a/include/configs/snow.h
+++ b/include/configs/snow.h
@@ -10,6 +10,10 @@
 #define __CONFIG_SNOW_H
 
 #include configs/exynos5250-common.h
+#include configs/exynos5-dt-common.h
 
 
+#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
+#define CONFIG_POWER_TPS65090_I2C
+
 #endif /* __CONFIG_SNOW_H */
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v6 07/15] exynos: Rename -dt config files to -common

[Simon Glass]

We want exynos5250-dt.h to be a board which can support any exynos5250
device. This matches the naming used by Linux. As a first step, rename
the existing -dt files to -common to make it clear they are common files,
and not specific boards.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/{exynos4-dt.h = exynos4-common.h}   | 6 +++---
 include/configs/{exynos5-dt.h = exynos5-common.h}   | 6 +++---
 include/configs/{exynos5250-dt.h = exynos5250-common.h} | 2 +-
 include/configs/odroid.h | 2 +-
 include/configs/origen.h | 2 +-
 include/configs/peach-pit.h  | 2 +-
 include/configs/s5pc210_universal.h  | 2 +-
 include/configs/smdk5250.h   | 2 +-
 include/configs/smdk5420.h   | 2 +-
 include/configs/snow.h   | 2 +-
 include/configs/trats.h  | 2 +-
 include/configs/trats2.h | 2 +-
 12 files changed, 16 insertions(+), 16 deletions(-)
 rename include/configs/{exynos4-dt.h = exynos4-common.h} (97%)
 rename include/configs/{exynos5-dt.h = exynos5-common.h} (98%)
 rename include/configs/{exynos5250-dt.h = exynos5250-common.h} (97%)

diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-common.h
similarity index 97%
rename from include/configs/exynos4-dt.h
rename to include/configs/exynos4-common.h
index 99472ac..38b8961 100644
--- a/include/configs/exynos4-dt.h
+++ b/include/configs/exynos4-common.h
@@ -6,8 +6,8 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_EXYNOS4_COMMON_H
+#define __CONFIG_EXYNOS4_COMMON_H
 
 /* High Level Configuration Options */
 #define CONFIG_SAMSUNG /* in a SAMSUNG core */
@@ -136,4 +136,4 @@
 /* Enable devicetree support */
 #define CONFIG_OF_LIBFDT
 
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_EXYNOS4_COMMON_H */
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-common.h
similarity index 98%
rename from include/configs/exynos5-dt.h
rename to include/configs/exynos5-common.h
index 0c400b1..fede0e8 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-common.h
@@ -6,8 +6,8 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_EXYNOS5_COMMON_H
+#define __CONFIG_EXYNOS5_COMMON_H
 
 /* High Level Configuration Options */
 #define CONFIG_SAMSUNG /* in a SAMSUNG core */
@@ -289,4 +289,4 @@
 #define EXYNOS_USB_SECONDARY_BOOT  0xfeed0002
 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
 
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_EXYNOS5_COMMON_H */
diff --git a/include/configs/exynos5250-dt.h 
b/include/configs/exynos5250-common.h
similarity index 97%
rename from include/configs/exynos5250-dt.h
rename to include/configs/exynos5250-common.h
index 05d33a7..b4c1ccf 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-common.h
@@ -10,7 +10,7 @@
 #ifndef __CONFIG_5250_H
 #define __CONFIG_5250_H
 
-#include configs/exynos5-dt.h
+#include configs/exynos5-common.h
 #define CONFIG_EXYNOS5250
 
 #define CONFIG_SYS_SDRAM_BASE  0x4000
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index b616ac2..07a2ff6 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -12,7 +12,7 @@
 #ifndef __CONFIG_ODROID_U3_H
 #define __CONFIG_ODROID_U3_H
 
-#include configs/exynos4-dt.h
+#include configs/exynos4-common.h
 
 #define CONFIG_SYS_PROMPT  Odroid #  /* Monitor Command Prompt */
 
diff --git a/include/configs/origen.h b/include/configs/origen.h
index fb1536c..fc8a202 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -9,7 +9,7 @@
 #ifndef __CONFIG_ORIGEN_H
 #define __CONFIG_ORIGEN_H
 
-#include configs/exynos4-dt.h
+#include configs/exynos4-common.h
 
 #define CONFIG_SYS_PROMPT  ORIGEN # 
 
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 8db889c..5e428cc 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -9,7 +9,7 @@
 #ifndef __CONFIG_PEACH_PIT_H
 #define __CONFIG_PEACH_PIT_H
 
-#include configs/exynos5-dt.h
+#include configs/exynos5-common.h
 
 #include configs/exynos5420.h
 
diff --git a/include/configs/s5pc210_universal.h 
b/include/configs/s5pc210_universal.h
index 082d51c..e26522d 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -10,7 +10,7 @@
 #ifndef __CONFIG_UNIVERSAL_H
 #define __CONFIG_UNIVERSAL_H
 
-#include configs/exynos4-dt.h
+#include configs/exynos4-common.h
 
 #define CONFIG_SYS_PROMPT  Universal #   /* Monitor Command Prompt */
 
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 6117094..56d41e6 

[U-Boot] [PATCH v6 12/15] config: Move smdkv310 to use common exynos4 file

[Simon Glass]

Most of the smdkv310 features are common with other exynos4 boards. To
permit easier addition of driver model support, use the common file and
add a device tree file.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4:
- Rebase on top of master (CONFIG_OF settings moved to Kconfig)

Changes in v3: None
Changes in v2:
- Leave in a few configs which are not in fact common to all boards

 arch/arm/cpu/armv7/exynos/Kconfig|  1 +
 arch/arm/dts/Makefile|  1 +
 arch/arm/dts/exynos4210-smdkv310.dts | 21 +
 configs/smdkv310_defconfig   |  1 +
 include/configs/smdkv310.h   | 61 ++--
 5 files changed, 34 insertions(+), 51 deletions(-)
 create mode 100644 arch/arm/dts/exynos4210-smdkv310.dts

diff --git a/arch/arm/cpu/armv7/exynos/Kconfig 
b/arch/arm/cpu/armv7/exynos/Kconfig
index e7c93d8..7a0d182 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -5,6 +5,7 @@ choice
 
 config TARGET_SMDKV310
bool Exynos4210 SMDKV310 board
+   select OF_CONTROL if !SPL_BUILD
 
 config TARGET_TRATS
bool Exynos4210 Trats board
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5f2b946..43a70e4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,4 +1,5 @@
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
+   exynos4210-smdkv310.dtb \
exynos4210-universal_c210.dtb \
exynos4210-trats.dtb \
exynos4412-trats2.dtb \
diff --git a/arch/arm/dts/exynos4210-smdkv310.dts 
b/arch/arm/dts/exynos4210-smdkv310.dts
new file mode 100644
index 000..c390c8f
--- /dev/null
+++ b/arch/arm/dts/exynos4210-smdkv310.dts
@@ -0,0 +1,21 @@
+/*
+ * Samsung's Exynos4210-based SMDKV310 board device tree source
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ exynos4.dtsi
+
+/ {
+   model = Samsung SMDKV310 on Exynos4210;
+   compatible = samsung,smdkv310, samsung,exynos4210;
+
+   aliases {
+   serial0 = /serial@1380;
+   console = /serial@1382;
+   };
+
+};
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 44da273..0d1a24f 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_SMDKV310=y
+CONFIG_DEFAULT_DEVICE_TREE=exynos4210-smdkv310
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 048c178..a2469eb 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -9,71 +9,42 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include exynos4-common.h
+
+#undef CONFIG_BOARD_COMMON
+#undef CONFIG_USB_GADGET
+#undef CONFIG_USB_GADGET_S3C_UDC_OTG
+#undef CONFIG_CMD_USB_MASS_STORAGE
+#undef CONFIG_REVISION_TAG
+#undef CONFIG_CMD_THOR_DOWNLOAD
+#undef CONFIG_CMD_DFU
+
 /* High Level Configuration Options */
-#define CONFIG_SAMSUNG 1   /* in a SAMSUNG core */
-#define CONFIG_S5P 1   /* S5P Family */
-#define CONFIG_EXYNOS4 /* EXYNOS4 Family */
 #define CONFIG_EXYNOS4210  1   /* which is a EXYNOS4210 SoC */
 #define CONFIG_SMDKV3101   /* working with 
SMDKV310*/
 
-#include asm/arch/cpu.h  /* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
 /* Mach Type */
 #define CONFIG_MACH_TYPE   MACH_TYPE_SMDKV310
 
 #define CONFIG_SYS_SDRAM_BASE  0x4000
 #define CONFIG_SYS_TEXT_BASE   0x43E0
 
-/* input clock of PLL: SMDKV310 has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ2400
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
 /* Handling Sleep Mode*/
 #define S5P_CHECK_SLEEP0x0BAD
 #define S5P_CHECK_DIDLE0xBAD0
 #define S5P_CHECK_LPA  0xABAD
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (1  20))
-
 /* select serial console configuration */
 #define CONFIG_SERIAL1 1   /* use SERIAL 1 */
-#define CONFIG_BAUDRATE115200
 #define EXYNOS4_DEFAULT_UART_OFFSET0x01
 
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-
-/* PWM */
-#define CONFIG_PWM 1
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-/* Command definition*/
-#include config_cmd_default.h
-
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_FAT
-
-#define CONFIG_BOOTDELAY 

[U-Boot] [PATCH v6 11/15] config: Move arndale to use common exynos5250 file

[Simon Glass]

Most of the arndale features are common with other exynos5250 boards. To
permit easier addition of driver model support, use the common file.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Reduce the number of common elements to avoid needing #undefs later

 include/configs/arndale.h   | 195 +---
 include/configs/exynos-common.h |   1 -
 include/configs/exynos4-common.h|   2 +
 include/configs/exynos5-common.h|  12 ---
 include/configs/exynos5250-common.h |   5 -
 include/configs/exynos5420-common.h |  14 +++
 include/configs/peach-pit.h |  10 ++
 include/configs/smdk5250.h  |  19 
 include/configs/smdk5420.h  |   3 +
 include/configs/snow.h  |  17 
 10 files changed, 66 insertions(+), 212 deletions(-)

diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 43077cf..f9ee40f 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -9,109 +9,19 @@
 #ifndef __CONFIG_ARNDALE_H
 #define __CONFIG_ARNDALE_H
 
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P /* S5P Family */
-#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
-#define CONFIG_EXYNOS5250
-
-#include asm/arch/cpu.h  /* get chip and board defs */
-
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-
-/* Allow tracing to be enabled */
-#define CONFIG_TRACE
-#define CONFIG_CMD_TRACE
-#define CONFIG_TRACE_BUFFER_SIZE   (16  20)
-#define CONFIG_TRACE_EARLY_SIZE(8  20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR0x5000
-
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define CONFIG_SYS_SDRAM_BASE  0x4000
-#define CONFIG_SYS_TEXT_BASE   0x43E0
-
-/* input clock of PLL: SMDK5250 has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ2400
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP0x0BAD
-#define S5P_CHECK_DIDLE0xBAD0
-#define S5P_CHECK_LPA  0xABAD
-
-/* Offset for inform registers */
-#define INFORM0_OFFSET 0x800
-#define INFORM1_OFFSET 0x804
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (4  20))
-
-/* select serial console configuration */
-#define CONFIG_BAUDRATE115200
-#define EXYNOS5_DEFAULT_UART_OFFSET0x01
-#define CONFIG_SILENT_CONSOLE
-
-/* Console configuration */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define EXYNOS_DEVICE_SETTINGS \
-   stdin=serial\0 \
-   stdout=serial\0 \
-   stderr=serial\0
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   EXYNOS_DEVICE_SETTINGS
+#include exynos5250-common.h
 
 /* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-#define CONFIG_DWMMC
-#define CONFIG_EXYNOS_DWMMC
 #define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_BOUNCE_BUFFER
-
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* PWM */
-#define CONFIG_PWM
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-/* Command definition*/
-#include config_cmd_default.h
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_HASH
-
-#define CONFIG_BOOTDELAY   3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 /* USB */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_EXYNOS
-#define CONFIG_USB_STORAGE
 
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define CONFIG_USB_HOST_ETHER
@@ -119,106 +29,23 @@
 
 /* MMC SPL */
 #define CONFIG_EXYNOS_SPL
-#define COPY_BL2_FNPTR_ADDR0x02020030
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-
-/* specific .lds file */
-#define CONFIG_SPL_LDSCRIPTboard/samsung/common/exynos-uboot-spl.lds
-#define CONFIG_SPL_TEXT_BASE   0x02023400
-#define CONFIG_SPL_MAX_FOOTPRINT   (14 * 1024)
-
-#define CONFIG_BOOTCOMMAND mmc read 40007000 451 2000; bootm 40007000
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use hush command parser*/
 #define CONFIG_SYS_PROMPT  ARNDALE # 
-#define CONFIG_SYS_CBSIZE  256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE  384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16   

[U-Boot] [PATCH v6 15/15] exynos: Enable pre-relocation malloc()

[Simon Glass]

Enable this feature to support driver model before relocation.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/exynos-common.h | 5 +++--
 include/configs/odroid.h| 2 --
 include/configs/s5p_goni.h  | 5 +++--
 include/configs/smdkc100.h  | 4 
 4 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 54b61d7..371f32d 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -38,8 +38,9 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_ENV_OVERWRITE
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (80 * SZ_1M))
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_F_LEN(1  10)
+#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (80  20))
 
 /* select serial console configuration */
 #define CONFIG_BAUDRATE115200
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 07a2ff6..b928af8 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -37,8 +37,6 @@
 #define CONFIG_SYS_TEXT_BASE   0x43e0
 
 #include linux/sizes.h
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
 #define CONFIG_SERIAL1
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index feb4d76..0c6e9c7 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -39,8 +39,9 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_EDITING
 
-/* Size of malloc() pool.*/
-#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + 80 * SZ_1M)
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_F_LEN(1  10)
+#define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (80  20))
 
 /*
  * select serial console configuration
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 566028d..22835ff 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -47,6 +47,10 @@
  * 1MB = 0x10, 0x10 = 1024 * 1024
  */
 #define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + (1  20))
+
+/* Small malloc pool before relocation */
+#define CONFIG_SYS_MALLOC_F_LEN(1  10)
+
 /*
  * select serial console configuration
  */
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v6 14/15] samsung: Enable device tree for smdkc100

[Simon Glass]

Change this board to add a device tree.

Signed-off-by: Simon Glass s...@chromium.org
---

Changes in v6:
- Rebase on top of samsung/master and 'git pull upstream-arm master'

Changes in v4:
- Rebase on top of master (CONFIG_OF settings moved to Kconfig)

Changes in v3: None
Changes in v2:
- Avoid using a common file, and just add a device tree
- Fix device tree base addresses

 arch/arm/Kconfig   |  4 
 arch/arm/cpu/armv7/s5pc1xx/Kconfig |  5 +
 arch/arm/dts/Makefile  |  1 +
 arch/arm/dts/s5pc1xx-smdkc100.dts  | 29 +
 configs/smdkc100_defconfig |  2 ++
 include/configs/smdkc100.h |  2 ++
 6 files changed, 39 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/dts/s5pc1xx-smdkc100.dts

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22ceb9d..6c5ecd2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -432,9 +432,6 @@ config RMOBILE
 config TARGET_CM_FX6
bool Support cm_fx6
 
-config TARGET_SMDKC100
-   bool Support smdkc100
-
 config TARGET_SOCFPGA_CYCLONE5
bool Support socfpga_cyclone5
 
@@ -660,7 +657,6 @@ source board/ronetix/pm9261/Kconfig
 source board/ronetix/pm9263/Kconfig
 source board/ronetix/pm9g45/Kconfig
 source board/samsung/smdk2410/Kconfig
-source board/samsung/smdkc100/Kconfig
 source board/sandisk/sansa_fuze_plus/Kconfig
 source board/scb9328/Kconfig
 source board/schulercontrol/sc_sps_1/Kconfig
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig 
b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
index 1a8941d..2fbbc18 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig
+++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
@@ -7,6 +7,10 @@ config TARGET_S5P_GONI
bool S5P Goni board
select OF_CONTROL if !SPL_BUILD
 
+config TARGET_SMDKC100
+   bool Support smdkc100 board
+   select OF_CONTROL if !SPL_BUILD
+
 endchoice
 
 config SYS_CPU
@@ -16,5 +20,6 @@ config SYS_SOC
default s5pc1xx
 
 source board/samsung/goni/Kconfig
+source board/samsung/smdkc100/Kconfig
 
 endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 076e0f7..c37580e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts 
b/arch/arm/dts/s5pc1xx-smdkc100.dts
new file mode 100644
index 000..42754ce
--- /dev/null
+++ b/arch/arm/dts/s5pc1xx-smdkc100.dts
@@ -0,0 +1,29 @@
+/*
+ * Samsung's Exynos4210-based SMDKV310 board device tree source
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include skeleton.dtsi
+
+/ {
+   model = Samsung SMDKC100 based on S5PC100;
+   compatible = samsung,smdkc100, samsung,s5pc100;
+
+   aliases {
+   serial0 = /serial@ec00;
+   console = /serial@ec00;
+   };
+
+   serial@ec00 {
+   compatible = samsung,exynos4210-uart;
+   reg = 0xec00 0x100;
+   interrupts = 0 51 0;
+   id = 0;
+   };
+
+};
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 7455235..041030f 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -1,2 +1,4 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SMDKC100=y
+CONFIG_ARCH_S5PC1XX=y
+CONFIG_DEFAULT_DEVICE_TREE=s5pc1xx-smdkc100
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index c9a2e15..566028d 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -217,4 +217,6 @@
 #define CONFIG_ENV_SROM_BANK   3   /* Select SROM Bank-3 for Ethernet*/
 #endif /* CONFIG_CMD_NET */
 
+#define CONFIG_OF_LIBFDT
+
 #endif /* __CONFIG_H */
-- 
2.1.0.rc2.206.gedb03e5

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Re: [U-Boot] [PATCH] linker_lists: include linux/compiler.h

[Simon Glass]

On 6 October 2014 23:48, Masahiro Yamada yamad...@jp.panasonic.com wrote:
 The header file include/linker_lists.h uses __aligned();
 therefore it depends on include/linux/compiler.h

 Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com

Acked-by: Simon Glass s...@chromium.org
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Re: [U-Boot] [PATCH] dm: add of_match_ptr() macro

[Simon Glass]

On 6 October 2014 23:51, Masahiro Yamada yamad...@jp.panasonic.com wrote:
 The driver model supports two ways for passing device parameters;
 Device Tree and platform_data (board file).
 Each driver should generally support both of them because some
 popular IPs are used on various platforms.

 Assume the following scenario:
   - The driver Foo is used on SoC Bar and SoC Baz
   - The SoC Bar uses Device Tree control (CONFIG_OF_CONTROL=y)
   - The SoC Baz does not support Device Tree; uses a board file

 In this situation, the device driver Foo should work with/without
 the device tree control.  The driver should have .of_match and
 .ofdata_to_platdata members for SoC Bar, while they are meaningless
 for SoC Baz; therefore those device-tree control code should go
 inside #ifdef CONFIG_OF_CONTROL.

 The driver code will be like this:

   #ifdef CONFIG_OF_CONTROL
   static const struct udevice_id foo_of_match = {
   { .compatible = foo_driver },
   {},
   }

   static int foo_ofdata_to_platdata(struct udevice *dev)
   {
   ...
   }
   #endif

   U_BOOT_DRIVER(foo_driver) = {
   ...
   .of_match = of_match_ptr(foo_of_match),
   .ofdata_to_platdata = of_match_ptr(foo_ofdata_to_platdata),
   ...
   }

 This idea has been borrowed from Linux.
 (In Linux, this macro is defined in include/linux/of.h)

 Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com

Acked-by: Simon Glass s...@chromium.org
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Re: [U-Boot] [PATCH] dm: include linker_lists.h from platdata.h and uclass.h

[Simon Glass]

On 6 October 2014 23:49, Masahiro Yamada yamad...@jp.panasonic.com wrote:
 The header files include/dm/platdata.h and include/dm/uclass.h
 use ll_entry_declare(); therefore they depend on
 include/linker_lists.h.

 Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com

Acked-by: Simon Glass s...@chromium.org
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Re: [U-Boot] [PATCH] dm: fix include guard

[Simon Glass]

On 6 October 2014 23:49, Masahiro Yamada yamad...@jp.panasonic.com wrote:
 Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com

Acked-by: Simon Glass s...@chromium.org
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Re: [U-Boot] [PATCH v3 0/3] spi, sf: add mtdparts feature to spi and sf commands

[Heiko Schocher]

Hello Jagannadha Sutradharudu Teki,

Am 05.09.2014 07:38, schrieb Heiko Schocher:

This patchserie add the popssibility to define mtd partitions on
spi nor flash, and use this settings with the sf commands.

steps:

- add MTD layer driver for spi, original patch from:
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced

   and addapted it to current mainline.

- move common functions to get offset and size from
   cmdline nand command to extract offset and size from
   a mtd partition to common place drivers/mtd/mtd_uboot.c
   maybe another place is better?

- add to the sf command the possibility to use offset and size from
   the settings in mtdparts

With this patchset, the sf command looks now:

=  sf
sf - SPI flash sub-system

Usage:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
   and chip select
sf read addr offset|partition len   - read `len' bytes starting at
   `offset' to memory at `addr'
sf write addr offset|partition len  - write `len' bytes from memory
   at `addr' to flash at `offset'
sf erase offset|partition [+]len- erase `len' bytes from `offset'
   `+len' round up `len' to block size
sf update addr offset|partition len - erase and write `len' bytes from 
memory
   at `addr' to flash at `offset'
=
for example env is defined in mtdparts:

=  sf read 1300 env
device 0 offset 0xd, size 0x1
SF: 65536 bytes @ 0xd Read: OK
=





There are the followings checkpatch warnings:

CHECK: Alignment should match open parenthesis
#153: FILE: common/cmd_nand.c:217:
+   if (arg_off(argv[2],idx,addr,maxsize,maxsize,
+   MTD_DEV_TYPE_NAND, nand_info[idx].size)) {

CHECK: Alignment should match open parenthesis
#179: FILE: common/cmd_nand.c:557:
+   if (arg_off(argv[3],dev,off,size,maxsize,
+   MTD_DEV_TYPE_NAND, nand_info[dev].size))

CHECK: Alignment should match open parenthesis
#193: FILE: common/cmd_nand.c:576:
+   if (arg_off_size(argc - 3, argv + 3,dev,off,size,
+maxsize, MTD_DEV_TYPE_NAND,

total: 0 errors, 0 warnings, 3 checks, 361 lines checked

NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX 
MULTISTATEMENT_MACRO_USE_DO_WHILE NETWORKING_BLOCK_COMMENT_STYLE USLEEP_RANGE

20140714_ml_mtdparts/0002-mtd-nand-move-common-functions-from-cmd_nand.c-to-co.patch
 has style problems, please review.

I see not, why this warning pops up ...

- changes for v2:
   - mtd-spi-add-MTD-layer-driver.patch
 - add comment from Daniel Schwierzeck:
   fix compile error from original patch with
   static inline rather than static __maybe_unused
- changes for v3:
   - rebase with d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6
   - add comments from scott wood:
 - align MTD_DEV_TYPE_NAND correct
 - remove unnecessary inline
 - rework jffs2 header problem later

Cc: Scott Woodscottw...@freescale.com
Cc: Tom Rinitr...@ti.com
Cc: Daniel Schwierzeckdaniel.schwierz...@gmail.com
Cc: Jagannadha Sutradharudu Tekijagannadh.t...@gmail.com


ping? Do you have any objections against this patchseries, or do you
think it is ok?

bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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