[U-Boot] mpc85xx: inhibit bman portals by default

[Jeffrey Ladouceur]

Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is needed for deepsleep.

Signed-off-by: Jeffrey Ladouceur 
---
Depends on at minimum:
Developed during T102X testing.
http://patchwork.ozlabs.org/patch/403533
http://patchwork.ozlabs.org/patch/403539/
 
 arch/powerpc/cpu/mpc85xx/portals.c  |   41 +++
 include/configs/B4860QDS.h  |8 +++
 include/configs/P1023RDB.h  |8 +++
 include/configs/P1023RDS.h  |8 +++
 include/configs/P2041RDB.h  |8 +++
 include/configs/T102xQDS.h  |8 +++
 include/configs/T102xRDB.h  |8 +++
 include/configs/T1040QDS.h  |8 +++
 include/configs/T104xRDB.h  |8 +++
 include/configs/T208xQDS.h  |8 +++
 include/configs/T208xRDB.h  |8 +++
 include/configs/T4240EMU.h  |8 +++
 include/configs/T4240QDS.h  |8 +++
 include/configs/T4240RDB.h  |8 +++
 include/configs/corenet_ds.h|8 +++
 include/configs/km/kmp204x-common.h |8 +++
 16 files changed, 161 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/portals.c 
b/arch/powerpc/cpu/mpc85xx/portals.c
index 98815f8..4c2ee98 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -14,6 +14,44 @@
 #include 
 #include 
 
+#define MAX_PORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
+void inhibit_bman_portals(void)
+{
+   void __iomem *addr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
+   CONFIG_SYS_BMAN_SWP_ISDR_REG;
+   uint32_t val;
+   int portal_count = 0;
+
+   /* Dynamically determine number of portals */
+   do {
+   val = in_be32(addr);
+   if (val) {
+   printf("ERROR: should be zero at 0x%p\n", addr);
+   goto done;
+   }
+   out_be32(addr, -1);
+   val = in_be32(addr);
+   if (!val) {
+   /* end of portals */
+   if (!portal_count)
+   printf("ERROR: No portals\n");
+   goto done;
+   }
+   portal_count++;
+   addr += CONFIG_SYS_BMAN_SP_CINH_SIZE;
+   if (portal_count >= MAX_PORTALS)
+   goto done;
+   } while (1);
+
+done:
+
+#ifdef DEBUG
+   printf("BMan portal counted %u, defined is %u\n",
+  portal_count, CONFIG_SYS_BMAN_NUM_PORTALS);
+#endif
+   return;
+}
+
 void setup_portals(void)
 {
ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
@@ -38,6 +76,9 @@ void setup_portals(void)
out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
 #endif
out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+
+   /* Change default state of BMan ISDR portals to all 1s */
+   inhibit_bman_portals();
 }
 
 /* Update portal containter to match LAW setup of portal in phy map */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2fbb2c7..3f074ea 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -641,6 +641,14 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_BMAN_MEM_PHYS   CONFIG_SYS_BMAN_MEM_BASE
 #endif
 #define CONFIG_SYS_BMAN_MEM_SIZE   0x0200
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE   0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE   0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE  CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE  (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE  (CONFIG_SYS_BMAN_MEM_BASE + \
+   CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE  (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS25
 #define CONFIG_SYS_QMAN_MEM_BASE   0xf600
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index ba3da06..107db72 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -347,6 +347,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BMAN_MEM_BASE   0xff20
 #define CONFIG_SYS_BMAN_MEM_PHYS   CONFIG_SYS_BMAN_MEM_BASE
 #define CONFIG_SYS_BMAN_MEM_SIZE   0x0020
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE   CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE   (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE   (CONFIG_SYS_BMAN_MEM_BASE + \
+   CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE   (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 
 /* For FM

Re: [U-Boot] [PATCH 1/8] ARM: PSCI: Update psci.h for psci v0.2

[Albert ARIBAUD]

Hello Arnab,

On Thu, 28 Aug 2014 01:59:54 +0530, Arnab Basu
 wrote:
> Signed-off-by: Arnab Basu 
> Reviewed-by: Bhupesh Sharma 
> Cc: Marc Zyngier 
> ---
>  arch/arm/include/asm/psci.h |   42 +-
>  1 files changed, 41 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index 704b4b0..68579cd 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -2,6 +2,10 @@
>   * Copyright (C) 2013 - ARM Ltd
>   * Author: Marc Zyngier 
>   *
> + * Copyright (C) 2014 - Freescale Semiconductor Ltd
> + * Author: Arnab Basu 
> + *  updated file for PSCI v0.2
> + *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
> @@ -18,7 +22,7 @@
>  #ifndef __ARM_PSCI_H__
>  #define __ARM_PSCI_H__
>  
> -/* PSCI interface */
> +/* PSCI v0.1 interface */
>  #define ARM_PSCI_FN_BASE 0x95c1ba5e
>  #define ARM_PSCI_FN(n)   (ARM_PSCI_FN_BASE + (n))
>  
> @@ -27,9 +31,45 @@
>  #define ARM_PSCI_FN_CPU_ON   ARM_PSCI_FN(2)
>  #define ARM_PSCI_FN_MIGRATE  ARM_PSCI_FN(3)
>  
> +/* PSCI v0.2 interface */
> +#define PSCI_0_2_FN_BASE 0x8400
> +#define PSCI_0_2_FN(n)   (PSCI_0_2_FN_BASE + (n))
> +#define PSCI_0_2_64BIT   0x4000
> +#define PSCI_0_2_FN64_BASE   \
> + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
> +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
> +
> +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
> +#define PSCI_0_2_FN_CPU_SUSPEND  PSCI_0_2_FN(1)
> +#define PSCI_0_2_FN_CPU_OFF  PSCI_0_2_FN(2)
> +#define PSCI_0_2_FN_CPU_ON   PSCI_0_2_FN(3)
> +#define PSCI_0_2_FN_AFFINITY_INFOPSCI_0_2_FN(4)
> +#define PSCI_0_2_FN_MIGRATE  PSCI_0_2_FN(5)
> +#define PSCI_0_2_FN_MIGRATE_INFO_TYPEPSCI_0_2_FN(6)
> +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU  PSCI_0_2_FN(7)
> +#define PSCI_0_2_FN_SYSTEM_OFF   PSCI_0_2_FN(8)
> +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
> +
> +#define PSCI_0_2_FN64_CPU_SUSPENDPSCI_0_2_FN64(1)
> +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
> +#define PSCI_0_2_FN64_AFFINITY_INFO  PSCI_0_2_FN64(4)
> +#define PSCI_0_2_FN64_MIGRATEPSCI_0_2_FN64(5)
> +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPUPSCI_0_2_FN64(7)
> +
> +
> +/*
> + * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
> + * INVALID_PARAMS, and DENIED defined below are applicable
> + * to PSCI v0.1.
> + */
>  #define ARM_PSCI_RET_SUCCESS 0
>  #define ARM_PSCI_RET_NI  (-1)
>  #define ARM_PSCI_RET_INVAL   (-2)
>  #define ARM_PSCI_RET_DENIED  (-3)
> +#define PSCI_RET_ALREADY_ON  (-4)
> +#define PSCI_RET_ON_PENDING  (-5)
> +#define PSCI_RET_INTERNAL_FAILURE(-6)
> +#define PSCI_RET_NOT_PRESENT (-7)
> +#define PSCI_RET_DISABLED(-8)
>  
>  #endif /* __ARM_PSCI_H__ */
> -- 
> 1.7.7.4

Applied, with apologies for the delay. This patch will appear in
2015.01.

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH] usb_storage: blacklist Enclosure Service Devices

[Nikolay Dimitrov]

Hi Soeren,

On 11/08/2014 08:02 AM, Soeren Moch wrote:

Skip enclosure service devices when probing for usb storage devices.

This avoids long timeouts when probing for external usb harddisks
which provide "Enclosure Services".

Signed-off-by: Soeren Moch 
--

This is a new version of the patch
"usb_storage: skip all unknown devices when probing"
http://http://lists.denx.de/pipermail/u-boot/2014-November/194622.html

Cc: Marek Vasut 
Cc: Tom Rini 
---
  common/usb_storage.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/common/usb_storage.c b/common/usb_storage.c
index eb7706c..9198f73 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -1351,8 +1351,9 @@ int usb_stor_get_info(struct usb_device *dev, struct 
us_data *ss,
perq = usb_stor_buf[0];
modi = usb_stor_buf[1];

-   if ((perq & 0x1f) == 0x1f) {
-   /* skip unknown devices */
+   if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) {
+   /* skip unknown devices and enclosure service devices, */
+   /* they would not respond to test_unit_ready   */
return 0;
}
if ((modi&0x80) == 0x80) {



Is it possible to provide a configuration option and some default 
behavior, instead of just disabling it?


Regards,
Nikolay
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[U-Boot] [PATCH] usb_storage: blacklist Enclosure Service Devices

[Soeren Moch]

Skip enclosure service devices when probing for usb storage devices.

This avoids long timeouts when probing for external usb harddisks
which provide "Enclosure Services".

Signed-off-by: Soeren Moch 
--

This is a new version of the patch
"usb_storage: skip all unknown devices when probing"
http://http://lists.denx.de/pipermail/u-boot/2014-November/194622.html

Cc: Marek Vasut 
Cc: Tom Rini 
---
 common/usb_storage.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/common/usb_storage.c b/common/usb_storage.c
index eb7706c..9198f73 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -1351,8 +1351,9 @@ int usb_stor_get_info(struct usb_device *dev, struct 
us_data *ss,
perq = usb_stor_buf[0];
modi = usb_stor_buf[1];
 
-   if ((perq & 0x1f) == 0x1f) {
-   /* skip unknown devices */
+   if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) {
+   /* skip unknown devices and enclosure service devices, */
+   /* they would not respond to test_unit_ready   */
return 0;
}
if ((modi&0x80) == 0x80) {
-- 
1.9.1

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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

[Peng Fan]

在 11/8/2014 12:07 PM, Peng Fan 写道:



在 11/7/2014 8:17 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:45:51 PM, Peng Fan wrote:

在 11/7/2014 7:09 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:

[...]


@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct
usb_ehci *ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 |
USBPHY_CTRL_ENUTMILEVEL3);

__raw_writel(val, phy_ctrl);

-return val & USBPHY_CTRL_OTG_ID;
+return board_usb_phy_mode(index);


This should be called from ehci_hcd_init() right after
usb_phy_enable(). Afterall, the mode detection has nothing to do with
the PHY enabling.


This back to what I did in patch v2. right after usb_phy_enable(),
just
paste that piece of code here:

The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+

   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;

+   board_usb_phy_mode(index, &type);
+


The usb_phy_enable() should not return the PHY mode at all though.
It should be the board_usb_phy_mode() which adjusts the PHY type.
The usb_phy_enable() should return just a success/failure return
value.


ok. got it.


What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+if (port == 1)
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent
this patch set.


It should really explicitly set it, not modify it, see above.


I have an idea about this patch:
1. usb_phy_enable will not be touched.
2. replace "type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;" with "usb_phy_enable(index, ehci)".
3. right after usb_phy_enable, add this line "type =
board_usb_phy_mode(index)" or "type = board_usb_phy_mode((struct usb_phy
*)PHY_ADDRESS)". Here I also think pass phy register definition to board
level code is not fine just as what we talked about passing ehci struct
to board level code in patch v2.
4. in ehci-mx6.c, implement the weak function "int __weak
board_usb_phy_mode(xxx)", and it's return value is the mode, HOST or
DEVICE. If the board code want to implement this function, just return
what the board want.

After all, this patch may looks like this:
In ehci-mx6.c
+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val & USBPHY_CTRL_OTG_ID;
+}
+

- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);

in board code, which is not in this patch, just list here:
+int board_usb_phy_mode(int port)
+{
+if (port == 1)
+return USB_INIT_HOST;
+else
+return USB_INIT_DEVICE;
+}
I just want to keep it simple and do not want to touch usb phy register
in board code.

Any ideas?


This seems OKish for all but the part where usb_phy_enable() shouldn't be
touched. The return value of usb_phy_enable() should really be a regular
return code, not the PHY mode.


ok. I'll fix this.

You can also still implement a function to query a PHY for it's mode,
so you
don't need to explicitly read the USBPHY_CTRL_OTG_ID in the board code.



I am not sure whether this following way is fine or not.
+int board_usb_phy_mode(int index)
+   __attribute__((weak, alias("usb_phy_mode")));
+
in usb_phy_mode, query a PHY for it's mode.

And righter after usb_phy_enable in ehci-mx6.c.
-   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;
+   usb_phy_enable(index, ehci);
+   type = usb_phy_mode(index);

This should be 'type = board_usb_phy_mode(index);'


usb_phy_enable return 0 but not return val & USBPHY_CTRL_OTG_ID. There
is no status bit for query enabled or not, so just return 0.

In board file:
int board_usb_phy_mode(int port)
{
 if (port == 1)
 return USB_INIT_HOST;
 else
 return usb_phy_mode(port);
}

I think this is better way then previous patch, but i did not find where
to put the usb_phy_mode prototype type, since board file will use it.

Regards,
Peng.

Regards,
Peng.
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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

[Peng Fan]

在 11/7/2014 8:17 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:45:51 PM, Peng Fan wrote:

在 11/7/2014 7:09 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:

[...]


@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct
usb_ehci *ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 |
USBPHY_CTRL_ENUTMILEVEL3);

__raw_writel(val, phy_ctrl);

-   return val & USBPHY_CTRL_OTG_ID;
+   return board_usb_phy_mode(index);


This should be called from ehci_hcd_init() right after
usb_phy_enable(). Afterall, the mode detection has nothing to do with
the PHY enabling.


This back to what I did in patch v2. right after usb_phy_enable(), just
paste that piece of code here:

The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+

   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;

+   board_usb_phy_mode(index, &type);
+


The usb_phy_enable() should not return the PHY mode at all though.
It should be the board_usb_phy_mode() which adjusts the PHY type.
The usb_phy_enable() should return just a success/failure return
value.


ok. got it.


What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+   if (port == 1)
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent
this patch set.


It should really explicitly set it, not modify it, see above.


I have an idea about this patch:
1. usb_phy_enable will not be touched.
2. replace "type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;" with "usb_phy_enable(index, ehci)".
3. right after usb_phy_enable, add this line "type =
board_usb_phy_mode(index)" or "type = board_usb_phy_mode((struct usb_phy
*)PHY_ADDRESS)". Here I also think pass phy register definition to board
level code is not fine just as what we talked about passing ehci struct
to board level code in patch v2.
4. in ehci-mx6.c, implement the weak function "int __weak
board_usb_phy_mode(xxx)", and it's return value is the mode, HOST or
DEVICE. If the board code want to implement this function, just return
what the board want.

After all, this patch may looks like this:
In ehci-mx6.c
+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val & USBPHY_CTRL_OTG_ID;
+}
+

- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);

in board code, which is not in this patch, just list here:
+int board_usb_phy_mode(int port)
+{
+   if (port == 1)
+   return USB_INIT_HOST;
+   else
+   return USB_INIT_DEVICE;
+}
I just want to keep it simple and do not want to touch usb phy register
in board code.

Any ideas?


This seems OKish for all but the part where usb_phy_enable() shouldn't be
touched. The return value of usb_phy_enable() should really be a regular
return code, not the PHY mode.


ok. I'll fix this.

You can also still implement a function to query a PHY for it's mode, so you
don't need to explicitly read the USBPHY_CTRL_OTG_ID in the board code.



I am not sure whether this following way is fine or not.
+int board_usb_phy_mode(int index)
+   __attribute__((weak, alias("usb_phy_mode")));
+
in usb_phy_mode, query a PHY for it's mode.

And righter after usb_phy_enable in ehci-mx6.c.
-   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : 
USB_INIT_HOST;

+   usb_phy_enable(index, ehci);
+   type = usb_phy_mode(index);

usb_phy_enable return 0 but not return val & USBPHY_CTRL_OTG_ID. There 
is no status bit for query enabled or not, so just return 0.


In board file:
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return usb_phy_mode(port);
}

I think this is better way then previous patch, but i did not find where 
to put the usb_phy_mode prototype type, since board file will use it.


Regards,
Peng.
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[U-Boot] [PATCH] broadcom: add seven boards

[Steve Rae]

- 5 based on cygnus, 2 based on 28155
- updates to support board families better
- add functions so CONFIG_ARMV7_NONSEC can be enabled on Cygnus boards

Signed-off-by: Steve Rae 
---

 arch/arm/Kconfig | 12 ++--
 board/broadcom/bcm11130/MAINTAINERS  |  6 ++
 board/broadcom/bcm11130_nand/MAINTAINERS |  6 ++
 board/broadcom/bcm911360_entphn-ns/MAINTAINERS   |  6 ++
 board/broadcom/bcm911360_entphn/MAINTAINERS  |  6 ++
 board/broadcom/bcm911360k/MAINTAINERS|  6 ++
 board/broadcom/bcm958300k-ns/MAINTAINERS |  6 ++
 board/broadcom/bcm958300k/MAINTAINERS|  4 ++--
 board/broadcom/bcm958305k/MAINTAINERS|  6 ++
 board/broadcom/bcm958622hr/MAINTAINERS   |  4 ++--
 board/broadcom/bcm_ep/board.c| 14 ++
 board/broadcom/{bcm958300k => bcmcygnus}/Kconfig |  2 +-
 board/broadcom/{bcm958622hr => bcmnsp}/Kconfig   |  2 +-
 configs/bcm11130_defconfig   |  3 +++
 configs/bcm11130_nand_defconfig  |  3 +++
 configs/bcm911360_entphn-ns_defconfig|  3 +++
 configs/bcm911360_entphn_defconfig   |  3 +++
 configs/bcm911360k_defconfig |  3 +++
 configs/bcm958300k-ns_defconfig  |  3 +++
 configs/bcm958300k_defconfig |  4 ++--
 configs/bcm958305k_defconfig |  3 +++
 configs/bcm958622hr_defconfig|  2 +-
 22 files changed, 92 insertions(+), 15 deletions(-)
 create mode 100644 board/broadcom/bcm11130/MAINTAINERS
 create mode 100644 board/broadcom/bcm11130_nand/MAINTAINERS
 create mode 100644 board/broadcom/bcm911360_entphn-ns/MAINTAINERS
 create mode 100644 board/broadcom/bcm911360_entphn/MAINTAINERS
 create mode 100644 board/broadcom/bcm911360k/MAINTAINERS
 create mode 100644 board/broadcom/bcm958300k-ns/MAINTAINERS
 create mode 100644 board/broadcom/bcm958305k/MAINTAINERS
 rename board/broadcom/{bcm958300k => bcmcygnus}/Kconfig (88%)
 rename board/broadcom/{bcm958622hr => bcmnsp}/Kconfig (88%)
 create mode 100644 configs/bcm11130_defconfig
 create mode 100644 configs/bcm11130_nand_defconfig
 create mode 100644 configs/bcm911360_entphn-ns_defconfig
 create mode 100644 configs/bcm911360_entphn_defconfig
 create mode 100644 configs/bcm911360k_defconfig
 create mode 100644 configs/bcm958300k-ns_defconfig
 create mode 100644 configs/bcm958305k_defconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22eb2d5..0da7068 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -508,12 +508,12 @@ config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
select CPU_V7
 
-config TARGET_BCM958300K
-   bool "Support bcm958300k"
+config TARGET_BCMCYGNUS
+   bool "Support bcmcygnus"
select CPU_V7
 
-config TARGET_BCM958622HR
-   bool "Support bcm958622hr"
+config TARGET_BCMNSP
+   bool "Support bcmnsp"
select CPU_V7
 
 config ARCH_EXYNOS
@@ -842,8 +842,8 @@ source "board/bluegiga/apx4devkit/Kconfig"
 source "board/bluewater/snapper9260/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
-source "board/broadcom/bcm958300k/Kconfig"
-source "board/broadcom/bcm958622hr/Kconfig"
+source "board/broadcom/bcmcygnus/Kconfig"
+source "board/broadcom/bcmnsp/Kconfig"
 source "board/calao/sbc35_a9g20/Kconfig"
 source "board/calao/tny_a9260/Kconfig"
 source "board/calao/usb_a9263/Kconfig"
diff --git a/board/broadcom/bcm11130/MAINTAINERS 
b/board/broadcom/bcm11130/MAINTAINERS
new file mode 100644
index 000..b22e86f
--- /dev/null
+++ b/board/broadcom/bcm11130/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM11130 BOARD
+M: Steve Rae 
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm11130_defconfig
diff --git a/board/broadcom/bcm11130_nand/MAINTAINERS 
b/board/broadcom/bcm11130_nand/MAINTAINERS
new file mode 100644
index 000..881db5b
--- /dev/null
+++ b/board/broadcom/bcm11130_nand/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM11130_NAND BOARD
+M: Steve Rae 
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm11130_nand_defconfig
diff --git a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS 
b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
new file mode 100644
index 000..b5f0207
--- /dev/null
+++ b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360_ENTPHN-NS BOARD
+M: Steve Rae 
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn-ns_defconfig
diff --git a/board/broadcom/bcm911360_entphn/MAINTAINERS 
b/board/broadcom/bcm911360_entphn/MAINTAINERS
new file mode 100644
index 000..fb7ee2b
--- /dev/null
+++ b/board/broadcom/bcm911360_entphn/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360_ENTPHN BOARD
+M: Steve Rae 
+S: Maintained
+F: board/b

[U-Boot] Pull request: u-boot-arm/master

[Albert ARIBAUD]

Hello Tom,

The following changes since commit 5b3ee386fde82a1ba42ff09b95247842c9a1585e:

  kbuild: clear VENDOR variable to fix build error on tcsh (2014-10-23 16:35:12 
-0400)

are available in the git repository at:

  git://git.denx.de/u-boot-arm master

for you to fetch changes up to 59a9cfdd16ad7ab14f22697bf1e049c6bea0d3e2:

  gic: fixed compilation error in GICv2 wait for interrupt macro (2014-10-28 
07:57:31 +0100)


Masahiro Yamada (4):
  arm: debug: import debug files from Linux 3.16
  arm: debug: replace license blocks with SPDX
  arm: debug: add Kconfig entries for lowlevel debug
  arm: debug: adjust for U-Boot

Yehuda Yitschak (1):
  gic: fixed compilation error in GICv2 wait for interrupt macro

 arch/arm/Kconfig  |   2 +
 arch/arm/Kconfig.debug|  64 +++
 arch/arm/include/asm/macro.h  |   2 +-
 arch/arm/include/debug/8250.S |  52 ++
 arch/arm/lib/Makefile |   2 +
 arch/arm/lib/debug.S  | 136 
+++
 include/linux/serial_reg.h| 388 
+++
 7 files changed, 645 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/Kconfig.debug
 create mode 100644 arch/arm/include/debug/8250.S
 create mode 100644 arch/arm/lib/debug.S
 create mode 100644 include/linux/serial_reg.h

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH v2] test: ums: Add sleep before unmount directory

[Wolfgang Denk]

Dear Stephen,

In message <545d40e1.2030...@wwwdotorg.org> you wrote:
>
> > My gut feeling is that there might be some USB driver error involved
> > here.
> 
> Where I've seen this is writing to an SD card in a USB-based SD card reader.
> 
> I have a fairly regular amd64 machine running Ubuntu. I put the loop 
> above into my own scripts that mount an SD card, copy new data to it, 
> and then immediately unmount it for the same reason that Lukasz made 
> this patch; umount doesn't always unmount. I did this so long ago that I 
> don't recall which Ubuntu version I had at the time, nor the kernel 
> version. It was *probably* Ubuntu 10.04 or 12.10 though. Now I'm on 
> 14.04, but have no idea if I still need the loop since it's already in 
> place:-)

But this is a bug.  Papering over is not a good idea.  It should be
analyzed, reported, and finally fixed.

Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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[U-Boot] [PATCH 8/8] imx: SPL support for iMX6 SabreSD

[John Tobias]

This file will enable the support for SPL on iMX6 Sabrex families.
It tested on SD2 and SD3 mmc port.
---
 board/freescale/mx6sabresd/mx6sabresd_spl.c | 277 
 1 file changed, 277 insertions(+)
 create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.c

diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.c 
b/board/freescale/mx6sabresd/mx6sabresd_spl.c
new file mode 100644
index 000..1d9ec6e
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6sabresd_spl.c
@@ -0,0 +1,277 @@
+/*
+ * Author: John Tobias 
+ *
+ * Derived from EDM_CF_IMX6 code by TechNexion,Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#if defined(CONFIG_SPL_BUILD)
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOOT_CFG   0x20D8004
+
+#define __REG(x)(*((volatile u32 *)(x)))
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |   \
+   PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+   PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+struct fsl_esdhc_cfg spl_usdhc_cfg;
+
+iomux_v3_cfg_t const spl_usdhc2_pads[] = {
+   MX6_PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD2_CMD__SD2_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NANDF_D2__GPIO2_IO02| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const spl_usdhc3_pads[] = {
+   MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NANDF_D0__GPIO2_IO00| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const spl_usdhc4_pads[] = {
+   MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+/*
+ * Got it from mx6q_4x_mt41j128.cfg file
+ */
+void set_mt41j128_ddr(void)
+{
+   __REG(0x020e05a8) = 0x0028;
+   __REG(0x020e05b0) = 0x0028;
+   __REG(0x020e0524) = 0x0028;
+   __REG(0x020e051c) = 0x0028;
+
+   __REG(0x020e0518) = 0x0028;
+   __REG(0x020e050c) = 0x0028;
+   __REG(0x020e05b8) = 0x0028;
+   __REG(0x020e05c0) = 0x0028;
+
+   __REG(0x020e05ac) = 0x0028;
+   __REG(0x020e05b4) = 0x0028;
+   __REG(0x020e0528) = 0x0028;
+   __REG(0x020e0520) = 0x0028;
+
+   __REG(0x020e0514) = 0x0028;
+   __REG(0x020e0510) = 0x0028;
+   __REG(0x020e05bc) = 0x0028;
+   __REG(0x020e05c4) = 0x0028;
+
+   __REG(0x020e056c) = 0x0030;
+   __REG(0x020e0578) = 0x0030;
+   __REG(0x020e0588) = 0x0030;
+   __REG(0x020e0594) = 0x0030;
+
+   __REG(0x020e057c) = 0x0030;
+   __REG(0x020e0590) = 0x0030;
+   __REG(0x020e0598) = 0x0030;
+   __REG(0x020e058c) = 0x;
+
+   __REG(0x020e059c) = 0x3030;
+   __REG(0x020e05a0) = 0x3030;
+   __REG(0x020e0784) = 0x0028;
+   __REG(0x020e0788) = 0x0028;
+
+   __REG(0x020e0794) = 0x0028;
+   __REG(0x020e079c) = 0x0028;
+   __REG(0x020e07a0) = 0x0028;
+   __REG(0x020e07a4) = 0x0028;
+
+   __REG(0x020e07a8) = 0x0028;
+   __REG(0x020e0748) = 0x0028;
+   __REG(0x020e074c) = 0x0030;
+   __REG(0x020e0750) 

[U-Boot] [PATCH 7/8] imx: add configuration file for SPL

[John Tobias]

This file is the default DCD configuration file for SPL
---
 board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 54 +++
 1 file changed, 54 insertions(+)
 create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg

diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg 
b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
new file mode 100644
index 000..2e2f850
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
@@ -0,0 +1,54 @@
+/*
+ * Maintainer : Richard Hu 
+ *
+ * Derived from Nitrogen6x code by Boundary Devices
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM  sd
+
+#define __ASSEMBLY__
+#include 
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* set the default clock gate to save power */
+DATA 4 0x020C4068 0x00C03F3F /* CCM_CCGR0 */
+DATA 4 0x020C406c 0x0030FC03 /* CCM_CCGR1 */
+DATA 4 0x020C4070 0x0FFFC000 /* CCM_CCGR2 */
+DATA 4 0x020C4074 0x3FF0 /* CCM_CCGR3 */
+DATA 4 0x020C4078 0xFFF300   /* CCM_CCGR4 */
+DATA 4 0x020C407c 0x0FF3 /* CCM_CCGR5 - enable SATA clocks */
+DATA 4 0x020C4080 0x03FF /* CCM_CCGR6 - enable ushdc and usb clocks */
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF0CF /* IOMUXC_GPR4 */
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F /* IOMUXC_GPR6 */
+DATA 4 0x020e001c 0x007F007F /* IOMUXC_GPR7 */
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x00fb /* CCM_CCOSR */
+
+
-- 
1.9.1

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[U-Boot] [PATCH 6/8] mx6: add SPL support in the header

[John Tobias]

---
 include/configs/mx6sabresd.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 938030d..4d2e54a 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -12,6 +12,13 @@
 #include 
 #include 
 
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_STACK 0x0093FFB8
+#include "imx6_spl.h"
+#endif
+
 #define CONFIG_MACH_TYPE   3980
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 #define CONFIG_CONSOLE_DEV "ttymxc0"
-- 
1.9.1

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[U-Boot] [PATCH 5/8] mmc: imx: add spl_board_mmc_init

[John Tobias]

When CONFIG_SPL_MMC_SUPPORT is defined, by default the
mmc_initialize function will call board_mmc_init. But,
the said function is not link to the spl image.
---
 drivers/mmc/mmc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 44a4feb..8b68e3e 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1441,10 +1441,13 @@ int mmc_initialize(bd_t *bis)
INIT_LIST_HEAD (&mmc_devices);
cur_dev_num = 0;
 
+#ifdef CONFIG_SPL_BUILD
+   if (spl_board_mmc_init(bis) < 0)
+   cpu_mmc_init(bis);
+#else  
if (board_mmc_init(bis) < 0)
cpu_mmc_init(bis);
 
-#ifndef CONFIG_SPL_BUILD
print_mmc_devices(',');
 #endif
 
-- 
1.9.1

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[U-Boot] [PATCH 4/8] imx6: add flexibility for defining stack address

[John Tobias]

iMX6 SabreSD has different stack address compare
to the default stack address defined on the file.
---
 include/configs/imx6_spl.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 308e520..003dfe7 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -29,7 +29,9 @@
 #define CONFIG_SPL_TEXT_BASE   0x00908000
 #define CONFIG_SPL_MAX_SIZE(64 * 1024)
 #define CONFIG_SPL_START_S_PATH"arch/arm/cpu/armv7"
+#ifndef CONFIG_SPL_STACK
 #define CONFIG_SPL_STACK   0x0091FFB8
+#endif
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
-- 
1.9.1

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[U-Boot] [PATCH 0/8] *** iMX6 SabreSD SPL Support ***

[John Tobias]

This patch is for SPL support for iMX6 SabreSD. The said
patches has been tested to work on SD2 and SD3 port of the
said board.

After applying the following patches, it will produces
SPL and u-boot.img binary images. You should run the
two commands below to store it in your SD or eMMC.

sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync
sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69


John Tobias (8):
  kconfig: add SUPPORT_SPL
  imx: add file in makefile
  imx6: add spl on board configuration
  imx6: add flexibility for defining stack address
  mmc: imx: add spl_board_mmc_init
  mx6: add SPL support in the header
  imx: add configuration file for SPL
  imx: SPL support for iMX6 SabreSD

 arch/arm/Kconfig  |   1 +
 board/freescale/mx6sabresd/Makefile   |   2 +-
 board/freescale/mx6sabresd/mx6sabresd_spl.c   | 277 ++
 board/freescale/mx6sabresd/mx6sabresd_spl.cfg |  54 +
 configs/mx6qsabresd_defconfig |   8 +-
 drivers/mmc/mmc.c |   5 +-
 include/configs/imx6_spl.h|   2 +
 include/configs/mx6sabresd.h  |   7 +
 8 files changed, 351 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.c
 create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg

-- 
1.9.1

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[U-Boot] [PATCH 3/8] imx6: add spl on board configuration

[John Tobias]

add the spl on build configuration of iMX6 SabreSD
---
 configs/mx6qsabresd_defconfig | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 67c1b77..b7b26df 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -1,3 +1,5 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
-CONFIG_ARM=y
-CONFIG_TARGET_MX6SABRESD=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_MX6SABRESD=y
+
-- 
1.9.1

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[U-Boot] [PATCH 1/8] kconfig: add SUPPORT_SPL

[John Tobias]

add SUPPORT_SPL for iMX6 SabreSD by default
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd774d4..6eafc20 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -609,6 +609,7 @@ config TARGET_MX6QSABREAUTO
 config TARGET_MX6SABRESD
bool "Support mx6sabresd"
select CPU_V7
+   select SUPPORT_SPL
 
 config TARGET_MX6SLEVK
bool "Support mx6slevk"
-- 
1.9.1

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[U-Boot] [PATCH 2/8] imx: add file in makefile

[John Tobias]

mx6sabresd_spl is the support file to enable SPL in iMX6 SabreSD
---
 board/freescale/mx6sabresd/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/mx6sabresd/Makefile 
b/board/freescale/mx6sabresd/Makefile
index cfca2ef..b8d0297 100644
--- a/board/freescale/mx6sabresd/Makefile
+++ b/board/freescale/mx6sabresd/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := mx6sabresd.o
+obj-y  := mx6sabresd.o mx6sabresd_spl.o
-- 
1.9.1

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Re: [U-Boot] [PATCH v2] test: ums: Add sleep before unmount directory

[Stephen Warren]

On 11/07/2014 02:54 PM, Wolfgang Denk wrote:

Dear Lukasz,

In message <141536-9790-1-git-send-email-l.majew...@samsung.com> you wrote:


-umount $MNT_DIR

+while true; do
+   umount $MNT_DIR > /dev/null 2>&1
+   if [ $? -eq 0 ]; then
+   break
+   fi
+   printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n"
+   sleep 1
+done


As Marek already pointed out, umount (both the command (8) and the
syscall (2)) are supposed to be blocking (except for typical error
cases like no permission, mountpoint does not exist, no file system
mounted, etc.).

If you really ever see the umount entering above loop, then there is
some bug somewhere.  It would be indeed interesting to see the strace
log for such umount calls.  Also, can you please add details about the
exact execution environment (host system / architecture, kernel
version, distro, and _especially_ which sort of USB driver is involved
here.

My gut feeling is that there might be some USB driver error involved
here.


Where I've seen this is writing to an SD card in a USB-based SD card reader.

I have a fairly regular amd64 machine running Ubuntu. I put the loop 
above into my own scripts that mount an SD card, copy new data to it, 
and then immediately unmount it for the same reason that Lukasz made 
this patch; umount doesn't always unmount. I did this so long ago that I 
don't recall which Ubuntu version I had at the time, nor the kernel 
version. It was *probably* Ubuntu 10.04 or 12.10 though. Now I'm on 
14.04, but have no idea if I still need the loop since it's already in 
place:-)

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Re: [U-Boot] [PATCH v2] test: ums: Add sleep before unmount directory

[Wolfgang Denk]

Dear Lukasz,

In message <141536-9790-1-git-send-email-l.majew...@samsung.com> you wrote:
>
> -umount $MNT_DIR
>  
> +while true; do
> + umount $MNT_DIR > /dev/null 2>&1
> + if [ $? -eq 0 ]; then
> + break
> + fi
> + printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n"
> + sleep 1
> +done

As Marek already pointed out, umount (both the command (8) and the
syscall (2)) are supposed to be blocking (except for typical error
cases like no permission, mountpoint does not exist, no file system
mounted, etc.).

If you really ever see the umount entering above loop, then there is
some bug somewhere.  It would be indeed interesting to see the strace
log for such umount calls.  Also, can you please add details about the
exact execution environment (host system / architecture, kernel
version, distro, and _especially_ which sort of USB driver is involved
here.

My gut feeling is that there might be some USB driver error involved
here.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
If the hours are long enough and the pay  is  short  enough,  someone
will say it's women's work.
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Re: [U-Boot] [PATCH V4 1/3] usb: eth: fix Makefile

[Marek Vasut]

On Friday, November 07, 2014 at 04:53:47 PM, Rene Griessl wrote:
> fix obj-y term
> 
> Signed-off-by: Rene Griessl 

Applied, thanks!

I'll look at the rest tomorrow or so.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] test: ums: Add sleep before unmount directory

[Marek Vasut]

On Friday, November 07, 2014 at 05:52:27 PM, Lukasz Majewski wrote:
> Hi Marek,
> 
> > On Friday, November 07, 2014 at 02:05:55 PM, Lukasz Majewski wrote:
> > > This change helps to run script on machines with quite long uptime.
> > > Without this the following error emerges:
> > > 
> > > File: ./dat_14M.img
> > > umount: /mnt/tmp-ums-test: device is busy.
> > > 
> > > (In some cases useful info about processes that use
> > > 
> > >  the device is found by lsof(8) or fuser(1))
> > > 
> > > TX: md5sum:083d3d22b542d3ecba61b12d17e03f9f
> > > mount: /dev/sdd6 already mounted or /mnt/tmp-ums-test busy
> > > mount: according to mtab, /dev/sdd6 is already mounted
> > > on /mnt/tmp-ums-test
> > > 
> > > Signed-off-by: Lukasz Majewski 
> > 
> > Why exactly does mount not block until it can unmount the device
> > anyway ?
> 
> Has mount or umount expose any blocking behavior?

I would expect umount to be blocking by default in the first place.
ie. umount /mnt/foo should wait until all data are synced on device
under /mnt/foo and only then it should be unmounted.

Can you check (with strace or something) what exact return value will
the umount() syscall return when it does NOT unmount the mountpoint
and returns to the shell ? Is it EBUSY ?

> As fair as I remember you cannot umount directory when any process
> holds reference to it.
>
> Here it looks like process which copy data queues data for writing and
> exit from cp.
> 
> Presumably, when we call umount there is still some pending data for
> write.
> 
> Hence the error.

In case there are data which are not yet sync'd to the device, the umount() 
syscall should block until those data are written and return only after that.
Why would it return -EBUSY ... hm ...

> Maybe there is a switch for mount/umount/cp which can correct such
> behavior?

That should be the default ...

Best regards,
Marek Vasut
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[U-Boot] [PATCH] driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots

[York Sun]

Increase write-to-write and read-to-read turnaround time for two-slot DDR
configurations. Previously only quad-rank and two dual-rank configurations
have this additional turnaround time. A recent test on two single-rank
DIMMs shows the shorter additional turnaround time is also needed.

Signed-off-by: York Sun 
---
 drivers/ddr/fsl/ctrl_regs.c |   31 +--
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9a156bf..f9be3ca 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -253,22 +253,30 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t 
*ddr)
 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 
 #if !defined(CONFIG_SYS_FSL_DDR1)
+/*
+ * Check DIMM configuration, return 2 if quad-rank or two dual-rank
+ * Return 1 if other two slots configuration. Return 0 if single slot.
+ */
 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 {
 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
if (dimm_params[0].n_ranks == 4)
-   return 1;
+   return 2;
 #endif
 
 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
if ((dimm_params[0].n_ranks == 2) &&
(dimm_params[1].n_ranks == 2))
-   return 1;
+   return 2;
 
 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
if (dimm_params[0].n_ranks == 4)
-   return 1;
+   return 2;
 #endif
+
+   if ((dimm_params[0].n_ranks != 0) &&
+   (dimm_params[2].n_ranks != 0))
+   return 1;
 #endif
return 0;
 }
@@ -316,6 +324,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 #elif defined(CONFIG_SYS_FSL_DDR3)
unsigned int data_rate = get_ddr_freq(0);
int txp;
+   int odt_overlap;
/*
 * (tXARD and tXARDS). Empirical?
 * The DDR3 spec has not tXARD,
@@ -331,13 +340,23 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
/* set the turnaround time */
 
/*
-* for single quad-rank DIMM and two dual-rank DIMMs
+* for single quad-rank DIMM and two-slot DIMMs
 * to avoid ODT overlap
 */
-   if (avoid_odt_overlap(dimm_params)) {
+   odt_overlap = avoid_odt_overlap(dimm_params);
+   switch (odt_overlap) {
+   case 2:
twwt_mclk = 2;
trrt_mclk = 1;
+   break;
+   case 1:
+   twwt_mclk = 1;
+   trrt_mclk = 0;
+   break;
+   default:
+   break;
}
+
/* for faster clock, need more time for data setup */
trwt_mclk = (data_rate/100 > 1800) ? 2 : 1;
 
@@ -383,7 +402,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
);
debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 }
-#endif /* defined(CONFIG_SYS_FSL_DDR2) */
+#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
 
 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
-- 
1.7.9.5

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Re: [U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Dinh Nguyen]

+CC: Graham Moore

On 11/07/2014 09:26 AM, Stefan Roese wrote:
> Hi Dinh, Hi Vince!
> 
> a quick question for you:
> 
> On 07.11.2014 16:04, Marek Vasut wrote:
> 
> 
> 
>>> diff --git a/drivers/spi/cadence_qspi_apb.c
>>> b/drivers/spi/cadence_qspi_apb.c new file mode 100644
>>> index 000..00a115f
>>> --- /dev/null
>>> +++ b/drivers/spi/cadence_qspi_apb.c
>>> @@ -0,0 +1,898 @@
>>> +/*
>>> + * Copyright (C) 2012 Altera Corporation 
>>> + * All rights reserved.
>>> + *
>>> + * Redistribution and use in source and binary forms, with or without
>>> + * modification, are permitted provided that the following conditions are
>>> met: + *  - Redistributions of source code must retain the above copyright
>>> + *notice, this list of conditions and the following disclaimer. + *
>>> - Redistributions in binary form must reproduce the above copyright + *
>>> notice, this list of conditions and the following disclaimer in the + *
>>> documentation and/or other materials provided with the distribution. + *
>>> - Neither the name of the Altera Corporation nor the
>>> + *names of its contributors may be used to endorse or promote products
>>> + *derived from this software without specific prior written
>>> permission. + *
>>> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
>>> IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
>>> TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
>>> PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA
>>> CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>>> EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO,
>>> PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR
>>> PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF
>>> LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING
>>> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS
>>> SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */
>>
>> This license is kinda iffy. What is this all about please ?
> 
> Yes, I was wondering about this as well. And in the Linux kernel 
> (Rocketboards)
> this file is dual licensed. Here an extract:
> 
> <---
> /*
>  * Driver for Cadence QSPI Controller
>  *
>  * Copyright (C) 2012 Altera Corporation
>  *
>  * This software is available to you under a choice of one of two
>  * licenses.  You may choose to be licensed under the terms of the GNU
>  * General Public License (GPL) Version 2, available from the file
>  * COPYING in the main directory of this source tree, or the
>  * OpenIB.org BSD license below:
>  *
>  * Redistribution and use in source and binary forms, with or
>  * without modification, are permitted provided that the following
>  * conditions are met:
>  *
>  *  - Redistributions of source code must retain the above
>  *copyright notice, this list of conditions and the following
>  *disclaimer.
>  *
>  *  - Redistributions in binary form must reproduce the above
>  *copyright notice, this list of conditions and the following
>  *disclaimer in the documentation and/or other materials
>  *provided with the distribution.
>  *
>  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
>  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
>  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
>  * SOFTWARE.
>  *
>  */
> <--
> 
> Could we not just use a "plain" GPL (v2) license here as well. Especially
> since the other files in this driver are just normal GPL files.
> 
> Comments welcome.
> 

Graham recent posted to lkml a patch series for QSPI that has a plain GPLv2.

http://marc.info/?l=linux-kernel&m=141417788514196&w=2

Dinh

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[U-Boot] [PATCH v3 11/11] sun6i: ehci: Add sun6i ehci support

[Hans de Goede]

Add support for the 2 ehci controllers found on the sun6i (A31) soc.

Signed-off-by: Hans de Goede 
---
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h |  3 ++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 11 +++
 arch/arm/include/asm/arch-sunxi/cpu.h |  8 +
 board/sunxi/Kconfig   |  2 ++
 configs/Mele_M9_defconfig |  3 ++
 drivers/usb/host/ehci-sunxi.c | 45 +--
 include/configs/sun6i.h   |  5 +++
 7 files changed, 61 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 90af8e2..9dca800 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -262,5 +262,8 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
 #define CCM_USB_CTRL_PHYGATE (0x1 << 8)
+/* These 2 are sun6i only, define them as 0 on sun4i */
+#define CCM_USB_CTRL_PHY1_CLK 0
+#define CCM_USB_CTRL_PHY2_CLK 0
 
 #endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 4992dbc..e16a764 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -193,6 +193,10 @@ struct sunxi_ccm_reg {
 
 #define AXI_GATE_OFFSET_DRAM   0
 
+#define AHB_GATE_OFFSET_USB_OHCI1  30
+#define AHB_GATE_OFFSET_USB_OHCI0  29
+#define AHB_GATE_OFFSET_USB_EHCI1  27
+#define AHB_GATE_OFFSET_USB_EHCI0  26
 #define AHB_GATE_OFFSET_MCTL   14
 #define AHB_GATE_OFFSET_MMC3   11
 #define AHB_GATE_OFFSET_MMC2   10
@@ -205,6 +209,13 @@ struct sunxi_ccm_reg {
 
 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
 
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+/* There is no global phy clk gate on sun6i, define as 0 */
+#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
+#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+
 #define MDFS_CLK_DEFAULT   0x8102 /* PLL6 / 3 */
 
 #define CCM_DRAMCLK_CFG_DIV0(x)((x - 1) << 8)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h 
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 6550e50..bdee89e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -37,16 +37,24 @@
 #define SUNXI_MMC1_BASE0x01c1
 #define SUNXI_MMC2_BASE0x01c11000
 #define SUNXI_MMC3_BASE0x01c12000
+#ifndef CONFIG_MACH_SUN6I
 #define SUNXI_USB0_BASE0x01c13000
 #define SUNXI_USB1_BASE0x01c14000
+#endif
 #define SUNXI_SS_BASE  0x01c15000
 #define SUNXI_HDMI_BASE0x01c16000
 #define SUNXI_SPI2_BASE0x01c17000
 #define SUNXI_SATA_BASE0x01c18000
+#ifndef CONFIG_MACH_SUN6I
 #define SUNXI_PATA_BASE0x01c19000
 #define SUNXI_ACE_BASE 0x01c1a000
 #define SUNXI_TVE1_BASE0x01c1b000
 #define SUNXI_USB2_BASE0x01c1c000
+#else
+#define SUNXI_USB0_BASE0x01c19000
+#define SUNXI_USB1_BASE0x01c1a000
+#define SUNXI_USB2_BASE0x01c1b000
+#endif
 #define SUNXI_CSI1_BASE0x01c1d000
 #define SUNXI_TZASC_BASE   0x01c1e000
 #define SUNXI_SPI3_BASE0x01c1f000
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index b2beea0..c3f865d 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -200,6 +200,7 @@ config MMC_SUNXI_SLOT_EXTRA
 config USB1_VBUS_PIN
string "Vbus enable pin for usb1 (ehci0)"
default "PH6" if MACH_SUN4I || MACH_SUN7I
+   default "PH27" if MACH_SUN6I
---help---
Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
a string in the format understood by sunxi_name_to_gpio, e.g.
@@ -208,6 +209,7 @@ config USB1_VBUS_PIN
 config USB2_VBUS_PIN
string "Vbus enable pin for usb2 (ehci1)"
default "PH3" if MACH_SUN4I || MACH_SUN7I
+   default "PH24" if MACH_SUN6I
---help---
See USB1_VBUS_PIN help text.
 
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index 3dacb19..f46439f 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
 CONFIG_FDTFILE="sun6i-a31-m9.dtb"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
@@ -13,3 +14,5 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb"
 # HDMI power ?
 +S:CONFIG_AXP221_ALDO2_VOLT=1800
 +S:CONFIG_AXP221_ALDO3_VOLT=3000
+# No Vbus gpio for usb1
++S:CONFIG_USB1_VBUS_PIN=""
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sun

[U-Boot] [PATCH v3 05/11] sun4i: Rename dram files to dram_sun4i.x

[Hans de Goede]

In preparation for adding sun6i dram support.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/Makefile|   6 +-
 arch/arm/cpu/armv7/sunxi/dram.c  | 750 ---
 arch/arm/cpu/armv7/sunxi/dram_sun4i.c| 750 +++
 arch/arm/include/asm/arch-sunxi/dram.h   | 167 +-
 arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 182 +++
 5 files changed, 937 insertions(+), 918 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/sunxi/dram.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun4i.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun4i.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index b3a3601..48cca0b 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -28,9 +28,9 @@ endif
 endif
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_MACH_SUN4I)   += dram.o
-obj-$(CONFIG_MACH_SUN5I)   += dram.o
-obj-$(CONFIG_MACH_SUN7I)   += dram.o
+obj-$(CONFIG_MACH_SUN4I)   += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN5I)   += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN7I)   += dram_sun4i.o
 ifdef CONFIG_SPL_FEL
 obj-y  += start.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
deleted file mode 100644
index dc9fdb9..000
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ /dev/null
@@ -1,750 +0,0 @@
-/*
- * sunxi DRAM controller initialization
- * (C) Copyright 2012 Henrik Nordstrom 
- * (C) Copyright 2013 Luke Kenneth Casson Leighton 
- *
- * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
- * and earlier U-Boot Allwiner A10 SPL work
- *
- * (C) Copyright 2007-2012
- * Allwinner Technology Co., Ltd. 
- * Berg Xing 
- * Tom Cubie 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-/*
- * Unfortunately the only documentation we have on the sun7i DRAM
- * controller is Allwinner boot0 + boot1 code, and that code uses
- * magic numbers & shifts with no explanations. Hence this code is
- * rather undocumented and full of magic.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define CPU_CFG_CHIP_VER(n) ((n) << 6)
-#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
-#define CPU_CFG_CHIP_REV_A 0x0
-#define CPU_CFG_CHIP_REV_C1 0x1
-#define CPU_CFG_CHIP_REV_C2 0x2
-#define CPU_CFG_CHIP_REV_B 0x3
-
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static void await_completion(u32 *reg, u32 mask, u32 val)
-{
-   unsigned long tmo = timer_get_us() + 100;
-
-   while ((readl(reg) & mask) != val) {
-   if (timer_get_us() > tmo)
-   panic("Timeout initialising DRAM\n");
-   }
-}
-
-/*
- * Wait up to 1s for mask to be clear in given reg.
- */
-static inline void await_bits_clear(u32 *reg, u32 mask)
-{
-   await_completion(reg, mask, 0);
-}
-
-/*
- * Wait up to 1s for mask to be set in given reg.
- */
-static inline void await_bits_set(u32 *reg, u32 mask)
-{
-   await_completion(reg, mask, mask);
-}
-
-/*
- * This performs the external DRAM reset by driving the RESET pin low and
- * then high again. According to the DDR3 spec, the RESET pin needs to be
- * kept low for at least 200 us.
- */
-static void mctl_ddr3_reset(void)
-{
-   struct sunxi_dram_reg *dram =
-   (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
-#ifdef CONFIG_MACH_SUN4I
-   struct sunxi_timer_reg *timer =
-   (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
-   u32 reg_val;
-
-   writel(0, &timer->cpu_cfg);
-   reg_val = readl(&timer->cpu_cfg);
-
-   if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
-   CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
-   setbits_le32(&dram->mcr, DRAM_MCR_RESET);
-   udelay(200);
-   clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
-   } else
-#endif
-   {
-   clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
-   udelay(200);
-   setbits_le32(&dram->mcr, DRAM_MCR_RESET);
-   }
-   /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
-* for additional 500 us before driving the CKE pin (Clock Enable)
-* high. The duration of this delay can be configured in the SDR_IDCR
-* (Initialization Delay Configuration Register) and applied
-* automatically by the DRAM controller during the DDR3 initialization
-* step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
-* can't provide sufficient delay at DRAM clock frequencies higher than
-* 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
-* 533 MHz according to the datasheet). Additionally, there is no
-* official documentation for the SDR_IDCR register anywhere, and
-* there is always a chance that we are interpreting it wrong.
-* Better be safe than sorry, so add an explicit delay here. */
-   udelay(500);
-}
-
-static vo

[U-Boot] [PATCH v3 10/11] sunxi: ehci: Add proper Kconfig options to select the usb Vbus gpio-s

[Hans de Goede]

Add proper Kconfig options to select the usb Vbus gpio-s, besides moving to
Kconfig being the right thing to do, an added advantage of this is that it
allows for boards without Vbus gpio-s.

Signed-off-by: Hans de Goede 
---
 board/sunxi/Kconfig| 14 ++
 configs/A10s-OLinuXino-M_defconfig |  3 ++-
 configs/A13-OLinuXinoM_defconfig   |  3 ++-
 configs/A13-OLinuXino_defconfig|  3 ++-
 configs/Auxtek-T004_defconfig  |  3 ++-
 configs/ba10_tv_box_defconfig  |  3 ++-
 configs/r7-tv-dongle_defconfig |  3 ++-
 drivers/usb/host/ehci-sunxi.c  | 35 +--
 include/configs/sun4i.h|  7 ---
 include/configs/sun7i.h|  7 ---
 10 files changed, 51 insertions(+), 30 deletions(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5c3b932..b2beea0 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -197,4 +197,18 @@ config MMC_SUNXI_SLOT_EXTRA
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
 
+config USB1_VBUS_PIN
+   string "Vbus enable pin for usb1 (ehci0)"
+   default "PH6" if MACH_SUN4I || MACH_SUN7I
+   ---help---
+   Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
+   a string in the format understood by sunxi_name_to_gpio, e.g.
+   PH1 for pin 1 of port H.
+
+config USB2_VBUS_PIN
+   string "Vbus enable pin for usb2 (ehci1)"
+   default "PH3" if MACH_SUN4I || MACH_SUN7I
+   ---help---
+   See USB1_VBUS_PIN help text.
+
 endif
diff --git a/configs/A10s-OLinuXino-M_defconfig 
b/configs/A10s-OLinuXino-M_defconfig
index 6475675..94fafa6 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -1,7 +1,8 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_USB1_VBUS_PIN="PB10"
 +S:CONFIG_MMC0_CD_PIN="PG1"
 +S:CONFIG_MMC1_CD_PIN="PG13"
 +S:CONFIG_ARM=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index d8b1239..8517203 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
+CONFIG_USB1_VBUS_PIN="PG11"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN5I=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 91039df..61f5466 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
+CONFIG_USB1_VBUS_PIN="PG11"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN5I=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 5b06ea0..7fe9059 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb"
+CONFIG_USB1_VBUS_PIN="PG13"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN5I=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 0a1abea..6ca7c57 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
 CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
+CONFIG_USB1_VBUS_PIN="PH12"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN4I=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 7dbff40..b9fd59c 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb"
+CONFIG_USB1_VBUS_PIN="PG13"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN5I=y
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 4befd57..193ac43 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -39,7 +39,6 @@ static struct sunxi_ehci_hcd {
{
.usb_rst_mask = CCM_USB_CTRL_PHY1_RST,
.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
-   .g

[U-Boot] [PATCH v3 09/11] sun6i: Add Mele M9 board

[Hans de Goede]

Signed-off-by: Hans de Goede 
---
 board/sunxi/Kconfig   |  4 
 board/sunxi/MAINTAINERS   |  1 +
 configs/Mele_M9_defconfig | 15 +++
 3 files changed, 20 insertions(+)
 create mode 100644 configs/Mele_M9_defconfig

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 6688386..5c3b932 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -112,6 +112,10 @@ config TARGET_MELE_M3
bool "MELE_M3"
depends on MACH_SUN7I
 
+config TARGET_MELE_M9
+   bool "MELE_M9"
+   depends on MACH_SUN6I
+
 config TARGET_MINI_X_1GB
bool "MINI_X_1GB"
depends on MACH_SUN4I
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index b3c77a8..ca03002 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -9,6 +9,7 @@ F:  configs/Cubieboard_defconfig
 F: configs/Mele_A1000_defconfig
 F: configs/Mele_A1000G_defconfig
 F: configs/Mele_M3_defconfig
+F: configs/Mele_M9_defconfig
 F: configs/Mini-X_defconfig
 F: configs/Mini-X-1Gb_defconfig
 F: include/configs/sun5i.h
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
new file mode 100644
index 000..3dacb19
--- /dev/null
+++ b/configs/Mele_M9_defconfig
@@ -0,0 +1,15 @@
+CONFIG_SPL=y
+CONFIG_FDTFILE="sun6i-a31-m9.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_TARGET_MELE_M9=y
+# Ethernet phy power
++S:CONFIG_AXP221_DLDO1_VOLT=3300
+# USB hub power
++S:CONFIG_AXP221_DLDO4_VOLT=3300
+# Wifi power
++S:CONFIG_AXP221_ALDO1_VOLT=3300
+# HDMI power ?
++S:CONFIG_AXP221_ALDO2_VOLT=1800
++S:CONFIG_AXP221_ALDO3_VOLT=3000
-- 
2.1.0

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[U-Boot] [PATCH v3 06/11] sun6i: Add dram initialization code

[Hans de Goede]

Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).

This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/Makefile|   1 +
 arch/arm/cpu/armv7/sunxi/dram_sun6i.c| 436 +++
 arch/arm/include/asm/arch-sunxi/cpu.h|   8 +-
 arch/arm/include/asm/arch-sunxi/dram.h   |   4 +
 arch/arm/include/asm/arch-sunxi/dram_sun6i.h | 359 ++
 5 files changed, 805 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun6i.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun6i.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 48cca0b..3b6ae47 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -30,6 +30,7 @@ endif
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_MACH_SUN4I)   += dram_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)   += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN6I)   += dram_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)   += dram_sun4i.o
 ifdef CONFIG_SPL_FEL
 obj-y  += start.o
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c 
b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
new file mode 100644
index 000..d28a07d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
@@ -0,0 +1,436 @@
+/*
+ * Sun6i platform dram controller init.
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. 
+ * Berg Xing 
+ * Tom Cubie 
+ *
+ * (C) Copyright 2014 Hans de Goede 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */
+#define DRAM_CLK_DEFAULT 31200
+#define DRAM_ZQ_DEFAULT 0x78
+
+struct dram_sun6i_para
+{
+   u8 bus_width;
+   u8 chan;
+   u8 rank;
+   u8 rows;
+   u16 page_size;
+};
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+static void await_completion(u32 *reg, u32 mask, u32 val)
+{
+   unsigned long tmo = timer_get_us() + 100;
+
+   while ((readl(reg) & mask) != val) {
+   if (timer_get_us() > tmo)
+   panic("Timeout initialising DRAM\n");
+   }
+}
+
+static void mctl_sys_init(void)
+{
+   struct sunxi_ccm_reg * const ccm =
+   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+   const int dram_clk_div = 2;
+
+   clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
+
+   clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
+   CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
+   CCM_DRAMCLK_CFG_UPD);
+   await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+   writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
+
+   /* deassert mctl reset */
+   setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+
+   /* enable mctl clock */
+   setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
+{
+   struct sunxi_mctl_phy_reg *mctl_phy;
+
+   if (ch_index == 0)
+   mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+   else
+   mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+
+   /* disable + reset dlls */
+   writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
+   writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
+   writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
+   if (para->bus_width == 32) {
+   writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
+   writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
+   }
+   udelay(2);
+
+   /* enable + reset dlls */
+   writel(0, &mctl_phy->acdllcr);
+   writel(0, &mctl_phy->dx0dllcr);
+   writel(0, &mctl_phy->dx1dllcr);
+   if (para->bus_width == 32) {
+   writel(0, &mctl_phy->dx2dllcr);
+   writel(0, &mctl_phy->dx3dllcr);
+   }
+   udelay(22);
+
+   /* enable and release reset of dlls */
+   writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
+   writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
+   writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
+   if (para->bus_width == 32) {
+   writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
+   writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
+   }
+   udelay(22);
+}
+
+static bool mctl_rank_detect(u32 *gsr0, int rank)
+{
+   const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
+   const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
+
+   await_completion(gsr0, done, done);
+   await_completion(gsr0 + 0x10, done, done);
+
+   return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) 

[U-Boot] [PATCH v3 07/11] sun6i: Poke magic sram controller register to avoid cache issues

[Hans de Goede]

Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/board.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6c812fc..9b3e80c 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,6 +114,11 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
+#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
+   /* Magic (undocmented) value taken from boot0, without this DRAM
+* access gets messed up (seems cache related) */
+   setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
-- 
2.1.0

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[U-Boot] [PATCH v3 03/11] sun6i: Add clock functions needed for SPL / DRAM init

[Hans de Goede]

Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).

Also add some extra clock register constant defines.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 77 +++
 arch/arm/include/asm/arch-sunxi/clock.h   |  1 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 27 +-
 arch/arm/include/asm/arch-sunxi/prcm.h|  1 +
 include/configs/sun6i.h   |  1 +
 5 files changed, 106 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c 
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 1eae976..16ab6f3 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -16,6 +16,33 @@
 #include 
 #include 
 
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+   struct sunxi_ccm_reg * const ccm =
+   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+   struct sunxi_prcm_reg * const prcm =
+   (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+   /* Set PLL ldo voltage without this PLL6 does not work properly */
+   clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
+   PRCM_PLL_CTRL_LDO_KEY);
+   clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
+   PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+   PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+   clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+   clock_set_pll1(40800);
+
+   writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+
+   writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+
+   writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
+   writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+}
+#endif
+
 void clock_init_uart(void)
 {
struct sunxi_ccm_reg *const ccm =
@@ -65,6 +92,56 @@ int clock_twi_onoff(int port, int state)
return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+   struct sunxi_ccm_reg * const ccm =
+   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+   int k = 1;
+   int m = 1;
+
+   if (clk > 115200) {
+   k = 2;
+   } else if (clk > 76800) {
+   k = 3;
+   m = 2;
+   }
+
+   /* Switch to 24MHz clock while changing PLL1 */
+   writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+  ATB_DIV_2 << ATB_DIV_SHIFT |
+  CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+  &ccm->cpu_axi_cfg);
+
+   /* PLL1 rate = 2400 * n * k / m */
+   writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
+  CCM_PLL1_CTRL_N(clk / (2400 * k / m)) |
+  CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
+   sdelay(200);
+
+   /* Switch CPU to PLL1 */
+   writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+  ATB_DIV_2 << ATB_DIV_SHIFT |
+  CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+  &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll5(unsigned int clk)
+{
+   struct sunxi_ccm_reg * const ccm =
+   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+   const int k = 2;
+   const int m = 1;
+
+   /* PLL5 rate = 2400 * n * k / m */
+   writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+  CCM_PLL5_CTRL_N(clk / (2400 * k / m)) |
+  CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
+
+   udelay(5500);
+}
+
 unsigned int clock_get_pll6(void)
 {
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h 
b/arch/arm/include/asm/arch-sunxi/clock.h
index 42382a8..b40c16b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -25,6 +25,7 @@
 int clock_init(void);
 int clock_twi_onoff(int port, int state);
 void clock_set_pll1(unsigned int hz);
+void clock_set_pll5(unsigned int hz);
 unsigned int clock_get_pll5p(void);
 unsigned int clock_get_pll6(void);
 void clock_init_safe(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 1397b35..4992dbc 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -170,7 +170,17 @@ struct sunxi_ccm_reg {
 #define CPU_CLK_SRC_OSC24M 1
 #define CPU_CLK_SRC_PLL1   2
 
-#define PLL1_CFG_DEFAULT   0x90011b21
+#define CCM_PLL1_CTRL_M(n) n) - 1) & 0x3) << 0)
+#define CCM_PLL1_CTRL_K(n) n) - 1) & 0x3) << 4)
+#define CCM_PLL1_CTRL_N(n) n) - 1) & 0x1f) << 8)
+#define CCM_PLL1_CTRL_MAGIC(0x1 << 16)
+#define CCM_PLL1_CTRL_EN   (0x1 << 31)
+
+#define CCM_PLL5_CTRL_M(n) n) - 1) & 0x3) << 0)
+#define CCM_PLL5_CTRL_K(n) n) - 1) & 0x3) << 4)
+#define CCM_PLL5_CTRL_N(n) (

[U-Boot] [PATCH v3 04/11] sun6i: Add cpucfg register definitions

[Hans de Goede]

Not used atm, for future use (e.g. PSCI).

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/psci.S|  4 +-
 arch/arm/include/asm/arch-sunxi/cpu.h  |  3 +-
 arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h | 67 ++
 3 files changed, 71 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 0084c81..b9ea78b 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -87,8 +87,8 @@ psci_cpu_on:
str r2, [r0]
dsb
 
-   movwr0, #(SUNXI_CPUCFG_BASE & 0x)
-   movtr0, #(SUNXI_CPUCFG_BASE >> 16)
+   movwr0, #(SUN7I_CPUCFG_BASE & 0x)
+   movtr0, #(SUN7I_CPUCFG_BASE >> 16)
 
@ CPU mask
and r1, r1, #3  @ only care about first cluster
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h 
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 0de79a0..d34690e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -70,7 +70,7 @@
 
 #define SUNXI_TP_BASE  0x01c25000
 #define SUNXI_PMU_BASE 0x01c25400
-#define SUNXI_CPUCFG_BASE  0x01c25c00
+#define SUN7I_CPUCFG_BASE  0x01c25c00
 
 #define SUNXI_UART0_BASE   0x01c28000
 #define SUNXI_UART1_BASE   0x01c28400
@@ -111,6 +111,7 @@
 #define SUNXI_AVG_BASE 0x01ea
 
 #define SUNXI_PRCM_BASE0x01f01400
+#define SUN6I_CPUCFG_BASE  0x01f01c00
 #define SUNXI_R_UART_BASE  0x01f02800
 #define SUNXI_R_PIO_BASE   0x01f02c00
 #define SUNXI_P2WI_BASE0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
new file mode 100644
index 000..e2a29cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
@@ -0,0 +1,67 @@
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 08/11] sun6i: Enable SPL

[Hans de Goede]

Enable the SPL now that we've all the necessary bits in place.

Signed-off-by: Hans de Goede 
---
 board/sunxi/Kconfig| 1 +
 configs/Colombus_defconfig | 9 +
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5b2d091..6688386 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -16,6 +16,7 @@ config MACH_SUN5I
 config MACH_SUN6I
bool "sun6i (Allwinner A31)"
select CPU_V7
+   select SUPPORT_SPL
 
 config MACH_SUN7I
bool "sun7i (Allwinner A20)"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 89291f9..bef568d 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -1,5 +1,6 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN6I=y
-CONFIG_TARGET_COLOMBUS=y
+CONFIG_SPL=y
 CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_TARGET_COLOMBUS=y
-- 
2.1.0

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[U-Boot] [PATCH v3 01/11] sun6i: Add new p2wi controller driver

[Hans de Goede]

From: Oliver Schinagl 

The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.

Signed-off-by: Oliver Schinagl 
Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/Makefile  |   1 +
 arch/arm/cpu/armv7/sunxi/p2wi.c| 117 +++
 arch/arm/include/asm/arch-sunxi/gpio.h |   3 +
 arch/arm/include/asm/arch-sunxi/p2wi.h | 140 +
 4 files changed, 261 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/p2wi.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/p2wi.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 82dbf76..b3a3601 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += clock.o
 obj-y  += pinmux.o
 obj-$(CONFIG_MACH_SUN6I)   += prcm.o
 obj-$(CONFIG_MACH_SUN8I)   += prcm.o
+obj-$(CONFIG_MACH_SUN6I)   += p2wi.o
 obj-$(CONFIG_MACH_SUN4I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)   += clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c
new file mode 100644
index 000..8d58955
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/p2wi.c
@@ -0,0 +1,117 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl 
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. 
+ * Berg Xing 
+ * Tom Cubie 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void p2wi_init(void)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+   /* Enable p2wi and PIO clk, and de-assert their resets */
+   prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+   sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
+   sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+
+   /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+   writel(P2WI_CTRL_RESET, &p2wi->ctrl);
+   sdelay(0x100);
+   writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+  &p2wi->cc);
+}
+
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+   unsigned long tmo = timer_get_us() + 100;
+
+   writel(P2WI_PM_DEV_ADDR(slave_addr) |
+  P2WI_PM_CTRL_ADDR(ctrl_reg) |
+  P2WI_PM_INIT_DATA(init_data) |
+  P2WI_PM_INIT_SEND,
+  &p2wi->pm);
+
+   while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
+   if (timer_get_us() > tmo)
+   return -EFAULT;
+   }
+
+   return 0;
+}
+
+static int p2wi_await_trans(void)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+   unsigned long tmo = timer_get_us() + 100;
+   int ret;
+   u8 reg;
+
+   while (1) {
+   reg = readl(&p2wi->status);
+   if (reg & P2WI_STAT_TRANS_ERR) {
+   ret = -EIO;
+   break;
+   }
+   if (reg & P2WI_STAT_TRANS_DONE) {
+   ret = 0;
+   break;
+   }
+   if (timer_get_us() > tmo) {
+   ret = -ETIME;
+   break;
+   }
+   }
+   writel(reg, &p2wi->status); /* Clear status bits */
+   return ret;
+}
+
+int p2wi_read(const u8 addr, u8 *data)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+   int ret;
+
+   writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+   writel(P2WI_DATA_NUM_BYTES(1) |
+  P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
+   writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+   writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+   ret = p2wi_await_trans();
+
+   *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
+   return ret;
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+   struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+   writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+   writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
+   writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
+   writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+   writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+   return p2wi_await_trans();
+}
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 437dd35..c734cf0 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h

[U-Boot] [PATCH v3 02/11] sun6i: Add basic axp221 driver

[Hans de Goede]

From: Oliver Schinagl 

The A31 uses the AXP221 pmic for various voltages.

Signed-off-by: Oliver Schinagl 
Signed-off-by: Hans de Goede 
---
 board/sunxi/board.c|  26 +++
 drivers/power/Kconfig  |  47 
 drivers/power/Makefile |   1 +
 drivers/power/axp221.c | 205 +
 include/axp221.h   |  42 ++
 5 files changed, 321 insertions(+)
 create mode 100644 drivers/power/axp221.c
 create mode 100644 include/axp221.h

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 03890c8..e6ec5b8 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -19,6 +19,9 @@
 #ifdef CONFIG_AXP209_POWER
 #include 
 #endif
+#ifdef CONFIG_AXP221_POWER
+#include 
+#endif
 #include 
 #include 
 #include 
@@ -169,6 +172,29 @@ void sunxi_board_init(void)
power_failed |= axp209_set_ldo3(2800);
power_failed |= axp209_set_ldo4(2800);
 #endif
+#ifdef CONFIG_AXP221_POWER
+   power_failed = axp221_init();
+   power_failed |= axp221_set_dcdc1(3000);
+   power_failed |= axp221_set_dcdc2(1200);
+   power_failed |= axp221_set_dcdc3(1200);
+   power_failed |= axp221_set_dcdc4(1200);
+   power_failed |= axp221_set_dcdc5(1500);
+#if CONFIG_AXP221_DLDO1_VOLT != -1
+   power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
+#endif
+#if CONFIG_AXP221_DLDO4_VOLT != -1
+   power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO1_VOLT != -1
+   power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO2_VOLT != -1
+   power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO3_VOLT != -1
+   power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
+#endif
+#endif
 
printf("DRAM:");
ramsize = sunxi_dram_init();
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index e69de29..1ec7c0e 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -0,0 +1,47 @@
+config AXP221_POWER
+   boolean "axp221 pmic support"
+   depends on MACH_SUN6I
+   default y
+   ---help---
+   Say y here to enable support for the axp221 pmic found on most sun6i
+   (A31) boards.
+
+config AXP221_DLDO1_VOLT
+   int "axp221 dldo1 voltage"
+   depends on AXP221_POWER
+   default -1
+   ---help---
+   Set the voltage (mV) to program the axp221 dldo1 at, set to -1 to
+   disable dldo1.
+
+config AXP221_DLDO4_VOLT
+   int "axp221 dldo4 voltage"
+   depends on AXP221_POWER
+   default -1
+   ---help---
+   Set the voltage (mV) to program the axp221 dldo4 at, set to -1 to
+   disable dldo4.
+
+config AXP221_ALDO1_VOLT
+   int "axp221 aldo1 voltage"
+   depends on AXP221_POWER
+   default -1
+   ---help---
+   Set the voltage (mV) to program the axp221 aldo1 at, set to -1 to
+   disable aldo1.
+
+config AXP221_ALDO2_VOLT
+   int "axp221 aldo2 voltage"
+   depends on AXP221_POWER
+   default -1
+   ---help---
+   Set the voltage (mV) to program the axp221 aldo2 at, set to -1 to
+   disable aldo2.
+
+config AXP221_ALDO3_VOLT
+   int "axp221 aldo3 voltage"
+   depends on AXP221_POWER
+   default -1
+   ---help---
+   Set the voltage (mV) to program the axp221 aldo3 at, set to -1 to
+   disable aldo3.
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index dc64e4d..04bd996 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -7,6 +7,7 @@
 
 obj-$(CONFIG_AXP152_POWER) += axp152.o
 obj-$(CONFIG_AXP209_POWER) += axp209.o
+obj-$(CONFIG_AXP221_POWER) += axp221.o
 obj-$(CONFIG_EXYNOS_TMU)   += exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)   += ftpmu010.o
 obj-$(CONFIG_TPS6586X_POWER)   += tps6586x.o
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
new file mode 100644
index 000..f4dc72e
--- /dev/null
+++ b/drivers/power/axp221.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2013 Oliver Schinagl 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+   if (mvolt < min)
+   mvolt = min;
+   else if (mvolt > max)
+   mvolt = max;
+
+   return (mvolt - min) / div;
+}
+
+int axp221_set_dcdc1(unsigned int mvolt)
+{
+   int ret;
+   u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100);
+
+   ret = p2wi_write(AXP221_DCDC1_CTRL, cfg);
+   if (ret)
+   return ret;
+
+   ret = p2wi_read(AXP221_OUTPUT_CTRL2, &cfg);
+   if (ret)
+   return ret;
+
+   cfg |= 1 << 7;
+   return p2wi_write(AXP221_OUTPUT_CTRL2, cfg);
+}
+
+int axp221_set_dcdc2(unsigned int mvolt)
+{
+   u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+   return p2wi_write(AXP221_DCDC2_CTRL, cfg);
+}
+
+int axp221_set_dcdc3(unsigned int mvolt)
+{
+   u8 c

[U-Boot] [PATCH v3 0/11] sun6i: Add dram init and SPL support

[Hans de Goede]

Hi All,

Here is v3 of my A31 dram init & SPL support series, this now includes A31
ehci (usb) support :)

Changes since v2:
-The previous series were based on top of some not yet ready for general
 consumption patches in my tree, which caused conflict when basing them on
 master, rebased the series on top of master
-EHCI support

Changes since v1:
-"sun6i: Add new p2wi controller driver"
 -Rename p2wi_set_pmu_address to p2wi_change_to_p2wi_mode
-"sun6i: Add basic axp221 driver"
 -Add support for all dldo and aldo-s
 -Add Kconfig option to select building AXP221 and to select voltage of
  dldo and aldo-s
-"sun6i: Add cpucfg register definitions"
 -Rename existing SUNXI_CPUCFG_BASE to SUN7I_CPUCFG_BASE, name sun6i one
  SUN6I_CPUCFG_BASE
 -Rename cpucfg.h to cpucfg_sun6i.h
-"sun4i: Rename dram files to dram_sun4i.x"
 -Do not include non existing dram_sun6i.h
-"sun6i: Add Mele M9 board"
 -Add defconfig settings for various ldo-s

Please review.

Regards,

Hans
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Re: [U-Boot] [PATCH 3/4 v4] arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver

[Simon Glass]

On 7 November 2014 04:37, Stefan Roese  wrote:
> Without this alias, DM based probing does not work. So lets add this
> alias to get the bus numbering correct.
>
> Signed-off-by: Stefan Roese 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Simon Glass 
> Cc: Jagannadha Sutradharudu Teki 

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Simon Glass]

Hi Stefan,

On 7 November 2014 05:50, Stefan Roese  wrote:
> This patch adds the driver for the Designware master SPI controller. This
> IP core is integrated on the Altera SoCFPGA. This implementation is a
> driver model (DM) implementation. So multiple SPI drivers can be used.
> Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
> used to connect the SPI NOR flashes. Without DM, using multiple SPI
> driver is not possible.
>
> This driver is very loosly based on the Linux driver. Most of the Linux
> driver is removed. Only the polling loop for the transfer is really used
> from this driver. As we don't support interrupts and DMA right now.
>
> This is tested on the SoCrates SoCFPGA board using the SPI pins on the
> P14 header.
>
> Signed-off-by: Stefan Roese 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Simon Glass 
> Cc: Jagannadha Sutradharudu Teki 

For driver model things:

Reviewed-by: Simon Glass 

Regards,
Simon
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Re: [U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Simon Glass]

Hi Stefan,

On 7 November 2014 04:37, Stefan Roese  wrote:
>
> This driver is cloned from the Altera Rockerboard.org U-Boot
> repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
> modification to support the U-Boot driver model (DM).
>
> As mentioned above, in this new version I ported this driver to the
> new driver model (DM). One big advantage of this move is that now
> multiple SPI drivers can be enabled on one platform. And since the
> SoCFPGA also has the Designware SPI master controller integrated,
> this feature is really needed to support both controllers.
>
> Because of this, this series needs the DT support for SoCFPGA
> to be applied. For DT based probing in the SPI DM.
>
> Signed-off-by: Stefan Roese 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Simon Glass 
> Cc: Jagannadha Sutradharudu Teki 


For the driver model parts:

Reviewed-by: Simon Glass 

(tiny nit below if you reissue)

>
> ---
> v4:
> - Reworked to support driver model (DM)
> - Coding-style changes to make it checkpatch clean
>
> v3:
> - Added SPDX License Indentifier
> - Removed CQSPI_WRITEL / CQSPI_READL
>
>  drivers/spi/Makefile   |   1 +
>  drivers/spi/cadence_qspi.c | 345 
>  drivers/spi/cadence_qspi.h |  76 
>  drivers/spi/cadence_qspi_apb.c | 898 
> +
>  4 files changed, 1320 insertions(+)
>  create mode 100644 drivers/spi/cadence_qspi.c
>  create mode 100644 drivers/spi/cadence_qspi.h
>  create mode 100644 drivers/spi/cadence_qspi_apb.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index eabbf27..964fdc1 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
>  obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
>  obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
> +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
>  obj-$(CONFIG_CF_SPI) += cf_spi.o
>  obj-$(CONFIG_CF_QSPI) += cf_qspi.o
>  obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> new file mode 100644
> index 000..fa95b19
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi.c
> @@ -0,0 +1,345 @@
> +/*
> + * Copyright (C) 2012
> + * Altera Corporation 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "cadence_qspi.h"
> +
> +#define CQSPI_STIG_READ0
> +#define CQSPI_STIG_WRITE   1
> +#define CQSPI_INDIRECT_READ2
> +#define CQSPI_INDIRECT_WRITE   3
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static int cadence_spi_write_speed(struct udevice *bus, uint hz)
> +{
> +   struct cadence_spi_platdata *plat = bus->platdata;
> +   struct cadence_spi_priv *priv = dev_get_priv(bus);
> +
> +   cadence_qspi_apb_config_baudrate_div(priv->regbase,
> +CONFIG_CQSPI_REF_CLK, hz);
> +
> +   /* Reconfigure delay timing if speed is changed. */
> +   cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
> +  plat->tshsl_ns, plat->tsd2d_ns,
> +  plat->tchsh_ns, plat->tslch_ns);
> +
> +   return 0;
> +}
> +
> +/* Calibration sequence to determine the read data capture delay register */
> +static int spi_calibration(struct udevice *bus)
> +{
> +   struct cadence_spi_platdata *plat = bus->platdata;
> +   struct cadence_spi_priv *priv = dev_get_priv(bus);
> +   void *base = priv->regbase;
> +   u8 opcode_rdid = 0x9F;
> +   unsigned int idcode = 0, temp = 0;
> +   int err = 0, i, range_lo = -1, range_hi = -1;
> +
> +   /* start with slowest clock (1 MHz) */
> +   cadence_spi_write_speed(bus, 100);
> +
> +   /* configure the read data capture delay register to 0 */
> +   cadence_qspi_apb_readdata_capture(base, 1, 0);
> +
> +   /* Enable QSPI */
> +   cadence_qspi_apb_controller_enable(base);
> +
> +   /* read the ID which will be our golden value */
> +   err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
> +   3, (u8 *)&idcode);
> +   if (err) {
> +   puts("SF: Calibration failed (read)\n");
> +   return err;
> +   }
> +
> +   /* use back the intended clock and find low range */
> +   cadence_spi_write_speed(bus, plat->max_hz);
> +   for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
> +   /* Disable QSPI */
> +   cadence_qspi_apb_controller_disable(base);
> +
> +   /* reconfigure the read data capture delay register */
> +   cadence_qspi_apb_readdata_capture(base, 1, i);
> +
> +   /* Enable back QSPI */
> +   cadence_qspi_apb_controller_enable(base);
> +
> + 

Re: [U-Boot] verifying & signing

[srinivasan]

Thanks a lot Simon,

Sorry True.. without unknowingly the ticket was duplicated I found out the
issue ie.,

openssl genrsa -F4 -out keys/dev.key 2048
openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt

The above commands was supposed to be executed with sudo permissions as
shown below:

sudo openssl genrsa -F4 -out keys/dev.key 2048
sudo openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt

Once again Many many Thanks for your support so far..

On Fri, Nov 7, 2014 at 10:42 PM, Simon Glass  wrote:

> Hi,
>
>
> On 4 November 2014 03:07, Srinivasan S 
> wrote:
> >
> > Hi Simon,
> >
> > When I was generating the keys ie., Step 4: Create a key pair
> >
> > Am facing one more error while generating private key & certificate
> containing public key used for verification when I execute the below
> openssl commands it is saying can't open  config file:
> >
> > srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
> openssl genrsa -F4 -out keys/dev.key 2048
> > WARNING: can't open config file:
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
> > Generating RSA private key, 2048 bit long modulus
> > +++
> > ...+++
> > e is 65537 (0x10001)
> > srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
> openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
> > WARNING: can't open config file:
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
> > Unable to load config info from
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
> >
> > Could you pls do the needful in resolving this errors cz of which am not
> able to proceed further
>
> This email seems to be a duplicate. Did you make sure the directory exists?
>
> Regards,
> Simon
>
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Re: [U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Stefan Roese]

Hi Simon,

On 07.11.2014 18:21, Simon Glass wrote:

+   qspi: spi@ff705000 {
+   compatible = "cadence,qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0xff705000 0x1000>,
+   <0xffa0 0x1000>;
+   interrupts = <0 151 4>;
+   clocks = <&qspi_clk>;
+   ext-decoder = <0>;  /* external decoder */
+   num-chipselect = <4>;
+   fifo-depth = <128>;
+   bus-num = <2>;
+   status = "disabled";
+   };
+


Is this the same binding as Linux? Can you please bring in the binding
document too? Some of these feel like they should have a
"manufacture," prefix.


Yes, its from Linux. But not from kernel.org but from the Altera 
Rocketboards.org version (v3.16). So the bindings might change if this 
driver would be pushed to mainline Linux.


Sure, I can include the binding document as well. Good idea.

Thanks,
Stefan

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Re: [U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Simon Glass]

Hi Stefan,

On 7 November 2014 04:37, Stefan Roese  wrote:
> This DT node is taken from the Rocketboard.org Linux repsitory. And
> is needed to enable (configure) the Cadence DM SPI driver.
>
> Signed-off-by: Stefan Roese 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Simon Glass 
> Cc: Jagannadha Sutradharudu Teki 
> ---
>  arch/arm/dts/socfpga.dtsi  | 15 +++
>  arch/arm/dts/socfpga_cyclone5_socrates.dts | 20 
>  2 files changed, 35 insertions(+)
>
> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> index 4472fd9..4a789a9 100644
> --- a/arch/arm/dts/socfpga.dtsi
> +++ b/arch/arm/dts/socfpga.dtsi
> @@ -639,6 +639,21 @@
> clock-names = "biu", "ciu";
> };
>
> +   qspi: spi@ff705000 {
> +   compatible = "cadence,qspi";
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +   reg = <0xff705000 0x1000>,
> +   <0xffa0 0x1000>;
> +   interrupts = <0 151 4>;
> +   clocks = <&qspi_clk>;
> +   ext-decoder = <0>;  /* external decoder */
> +   num-chipselect = <4>;
> +   fifo-depth = <128>;
> +   bus-num = <2>;
> +   status = "disabled";
> +   };
> +

Is this the same binding as Linux? Can you please bring in the binding
document too? Some of these feel like they should have a
"manufacture," prefix.


> /* Local timer */
> timer@fffec600 {
> compatible = "arm,cortex-a9-twd-timer";
> diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts 
> b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> index a1814b4..9277174 100644
> --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
> +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> @@ -48,3 +48,23 @@
>  &mmc {
> status = "okay";
>  };
> +
> +&qspi {
> +   status = "okay";
> +
> +   flash0: n25q00@0 {
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   compatible = "n25q00";
> +   reg = <0>;  /* chip select */
> +   spi-max-frequency = <5000>;
> +   m25p,fast-read;
> +   page-size = <256>;
> +   block-size = <16>; /* 2^16, 64KB */
> +   read-delay = <4>;  /* delay value in read data capture 
> register */
> +   tshsl-ns = <50>;
> +   tsd2d-ns = <50>;
> +   tchsh-ns = <4>;
> +   tslch-ns = <4>;
> +   };
> +};
> --
> 2.1.3
>

Regards,
Simon
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Re: [U-Boot] verifying & signing

[Simon Glass]

Hi,


On 4 November 2014 03:07, Srinivasan S  wrote:
>
> Hi Simon,
>
> When I was generating the keys ie., Step 4: Create a key pair
>
> Am facing one more error while generating private key & certificate 
> containing public key used for verification when I execute the below openssl 
> commands it is saying can't open  config file:
>
> srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
>  openssl genrsa -F4 -out keys/dev.key 2048
> WARNING: can't open config file: 
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
> Generating RSA private key, 2048 bit long modulus
> +++
> ...+++
> e is 65537 (0x10001)
> srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
>  openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
> WARNING: can't open config file: 
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
> Unable to load config info from 
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
>
> Could you pls do the needful in resolving this errors cz of which am not able 
> to proceed further

This email seems to be a duplicate. Did you make sure the directory exists?

Regards,
Simon
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Re: [U-Boot] [PATCH] exynos: dts: Correct USB vbus-gpio numbering for Snow

[Simon Glass]

On 6 November 2014 03:44, Sjoerd Simons  wrote:
> The current vbus GPIOs on snow make very little sense, their number is
> far above the maximum. As a result, USB doesn't work on snow.
>
> Correct the GPIO numbering so they match the current scheme for exynos5.
> Tested both EHCI and XHCI to correctly work after this change.
>
> Signed-off-by: Sjoerd Simons 

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 06/39] x86: config: Move common x86 configs to a common file

[Simon Glass]

Hi Bin,

On 7 November 2014 08:05, Bin Meng  wrote:
> Hi Simon,
>
> On Fri, Nov 7, 2014 at 4:19 AM, Simon Glass  wrote:
>> Many of the x86 CONFIG options will be common across different boards. Move
>> them to a common file.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  include/configs/coreboot.h   | 289 
>> ++-
>>  include/configs/x86-common.h | 272 
>>  2 files changed, 285 insertions(+), 276 deletions(-)
>>  create mode 100644 include/configs/x86-common.h
>>
>> diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
>> index fef267f..9ac5306 100644
>> --- a/include/configs/coreboot.h
>> +++ b/include/configs/coreboot.h
>> @@ -6,7 +6,6 @@
>>   * SPDX-License-Identifier:GPL-2.0+
>>   */
>>
>> -#include 
>>  /*
>>   * board/config.h - configuration options, board specific
>>   */
>> @@ -14,27 +13,15 @@
>>  #ifndef __CONFIG_H
>>  #define __CONFIG_H
>>
>> -/*
>> - * High Level Configuration Options
>> - * (easy to change)
>> - */
>> -#define CONFIG_SYS_COREBOOT
>> -#define CONFIG_SHOW_BOOT_PROGRESS
>> -#define CONFIG_LAST_STAGE_INIT
>> -#define CONFIG_SYS_VSNPRINTF
>> -#define CONFIG_ZBOOT_32
>> -#define CONFIG_PHYSMEM
>> -#define CONFIG_SYS_EARLY_PCI_INIT
>> -#define CONFIG_DISPLAY_BOARDINFO_LATE
>> -#define CONFIG_DISPLAY_CPUINFO
>> +#include 
>>
>> -#define CONFIG_DM
>> -#define CONFIG_CMD_DM
>> -#define CONFIG_DM_GPIO
>> -#define CONFIG_DM_SERIAL
>> +#define CONFIG_SYS_CAR_ADDR0x1920
>> +#define CONFIG_SYS_CAR_SIZE(16 * 1024)
>> +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
>>
>> -#define CONFIG_LMB
>> -#define CONFIG_OF_LIBFDT
>> +#define CONFIG_TRACE_EARLY_SIZE(8 << 20)
>> +#define CONFIG_TRACE_EARLY
>> +#define CONFIG_TRACE_EARLY_ADDR0x0140
>>
>>  #define CONFIG_BOOTSTAGE
>>  #define CONFIG_BOOTSTAGE_REPORT
>> @@ -45,278 +32,28 @@
>>  #define CONFIG_BOOTSTAGE_STASH_SIZE0x7fc
>>  #define CONFIG_BOOTSTAGE_USER_COUNT60
>>
>> -#define CONFIG_LZO
>> -#define CONFIG_FIT
>> -#undef CONFIG_ZLIB
>> -#undef CONFIG_GZIP
>> -#define CONFIG_SYS_BOOTM_LEN   (16 << 20)
>> -
>> -/*---
>> - * Watchdog Configuration
>> - */
>> -#undef CONFIG_WATCHDOG
>> -#undef CONFIG_HW_WATCHDOG
>> -
>> -/* SATA AHCI storage */
>> -
>> -#define CONFIG_SCSI_AHCI
>> -
>> -#ifdef CONFIG_SCSI_AHCI
>> -#define CONFIG_LIBATA
>> -#define CONFIG_SYS_64BIT_LBA
>> -#define CONFIG_SATA_INTEL  1
>> -#define CONFIG_SCSI_DEV_LIST   {PCI_VENDOR_ID_INTEL, \
>> -   PCI_DEVICE_ID_INTEL_NM10_AHCI},   \
>> -   {PCI_VENDOR_ID_INTEL,   \
>> -   PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
>> -   {PCI_VENDOR_ID_INTEL, \
>> -   PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
>> -   {PCI_VENDOR_ID_INTEL,   \
>> -   PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
>> -
>> -#define CONFIG_SYS_SCSI_MAX_SCSI_ID2
>> -#define CONFIG_SYS_SCSI_MAX_LUN1
>> -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
>> -CONFIG_SYS_SCSI_MAX_LUN)
>> -#endif
>> -
>> -/* Generic TPM interfaced through LPC bus */
>> -#define CONFIG_TPM
>> -#define CONFIG_TPM_TIS_LPC
>> -#define CONFIG_TPM_TIS_BASE_ADDRESS0xfed4
>> -
>> -/*---
>> - * Real Time Clock Configuration
>> - */
>> -#define CONFIG_RTC_MC146818
>> -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
>> -#define CONFIG_SYS_ISA_IO  CONFIG_SYS_ISA_IO_BASE_ADDRESS
>> -
>> -/*---
>> - * Serial Configuration
>> +/*
>> + * High Level Configuration Options
>> + * (easy to change)
>>   */
>> -#define CONFIG_COREBOOT_SERIAL
>> -#define CONFIG_SYS_NS16550
>> -#define CONFIG_BAUDRATE115200
>> -#define CONFIG_SYS_BAUDRATE_TABLE  {300, 600, 1200, 2400, 4800, \
>> -9600, 19200, 38400, 115200}
>> -#define CONFIG_SYS_NS16550_PORT_MAPPED
>> +#define CONFIG_SYS_COREBOOT
>> +#define CONFIG_LAST_STAGE_INIT
>>
>>  #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
>> "stdout=vga,serial,cbmem\0" \
>> "stderr=vga,serial,cbmem\0"
>>
>> -#define CONFIG_CONSOLE_MUX
>> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
>> -#define CONFIG_SYS_STDIO_DEREGISTER
>>  #define CONFIG_CBMEM_CONSOLE
>>
>> -#define CONFIG_CMDLINE_EDITING
>> -#define CONFIG_COMMAND_HISTORY
>> -#define CONFIG_AUTO_COMPLETE
>> -#define CONFIG_SYS_HUSH_PARSER
>> -
>> -#define CONFIG_SUPPORT_VFAT
>> -/
>> - * ATAPI support (experimental)
>> - **

Re: [U-Boot] [PATCH v2] test: ums: Add sleep before unmount directory

[Lukasz Majewski]

Hi Marek,

> On Friday, November 07, 2014 at 02:05:55 PM, Lukasz Majewski wrote:
> > This change helps to run script on machines with quite long uptime.
> > Without this the following error emerges:
> > 
> > File: ./dat_14M.img
> > umount: /mnt/tmp-ums-test: device is busy.
> > (In some cases useful info about processes that use
> >  the device is found by lsof(8) or fuser(1))
> > TX: md5sum:083d3d22b542d3ecba61b12d17e03f9f
> > mount: /dev/sdd6 already mounted or /mnt/tmp-ums-test busy
> > mount: according to mtab, /dev/sdd6 is already mounted
> > on /mnt/tmp-ums-test
> > 
> > Signed-off-by: Lukasz Majewski 
> 
> Why exactly does mount not block until it can unmount the device
> anyway ?

Has mount or umount expose any blocking behavior? 

As fair as I remember you cannot umount directory when any process
holds reference to it.

Here it looks like process which copy data queues data for writing and
exit from cp.

Presumably, when we call umount there is still some pending data for
write.

Hence the error.

Maybe there is a switch for mount/umount/cp which can correct such
behavior?


> 
> Best regards,
> Marek Vasut


-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] verified boot of beaglebone black

[Simon Glass]

Hi,

On 4 November 2014 00:39, Srinivasan S  wrote:
> Thanks a lot for your replies
> The issue was where at symbol was supposed to be changed to @
>
> +   kernel at 1 {
> +   data = /incbin/("Image.lzo");
> +   type = "kernel";
> +   arch = "arm";
> +   os = "linux";
> +   compression = "lzo";
> +   load = <0x80008000>;
> +   entry = <0x80008000>;
> +   hash at 1 {
> +   algo = "sha1";
> +   };
>
> When I was generating the keys ie., Step 4: Create a key pair
>
> Am facing one more error while generating private key & certificate 
> containing public key used for verification when I execute the below openssl 
> commands it is saying can't open  config file:
>
> srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
>  openssl genrsa -F4 -out keys/dev.key 2048
> WARNING: can't open config file: 
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
> Generating RSA private key, 2048 bit long modulus
> +++
> ...+++
> e is 65537 (0x10001)
> srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
>  openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
> WARNING: can't open config file: 
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
> Unable to load config info from 
> /tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
>

Did you mkdir keys?

Regards,
Simon
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Re: [U-Boot] uboot uImage binary does not boot in Qemu

[Andreas Färber]

Hi,

Am 06.11.2014 um 07:37 schrieb pegasus711:
> I cross compiled u-boot's latest version 2014-10 using buildroot's built-in
> cross compiler and generated uboot.bin. 
> 
> When I try to invoke it like so: 
> 
> 
> it throws an error complaining wrong image format:
> 
> 
> I've checked qemu's sources and as per 'uboot_image.h' , the only valid type
> numbers are from 0 through to 8. I am unable to understand the number 52
> here.
> 
> I've followed many articles on the internet in which u-boot is booted within
> Qemu and I do not see anything different that they are doing. I am confused.

As you can see above, your message is lacking all interesting
information - for QEMU usage, error message as well as what architecture
and board this is about in the first place.

If the error is coming from QEMU, i.e. failing to start executing
U-Boot, you should write to qemu-devel list instead. Depending on
architecture and board, your use case may simply not be supported by
QEMU yet or you have a mismatch between U-Boot and QEMU options.

Regards,
Andreas

-- 
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 21284 AG Nürnberg
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Re: [U-Boot] [PATCH v1 0/6] Update gdsys board support

[Kim Phillips]

On Fri, 7 Nov 2014 13:58:37 +0100
Dirk Eibach  wrote:

> Hi Kim,
> 
> 2014-11-05 11:43 GMT+01:00 Stefan Roese :
> > Hi Dirk,
> >
> > On 05.11.2014 10:45, Dirk Eibach wrote:
> >>
> >> will you look after this series? I ask because there is also some
> >> mpc83xx stuff involved.
> >
> >
> > Yes, I just looked again. Not sure how we should handle this patch series. I
> > can ack the PPC4xx and CFI flash related patches and someone else can pull
> > this series (Kim for mpc83xx. Or Kim ack's the 83xx patch and I'll pull all
> > and push it forward.
> >
> > Comments?
> 
> what way of handling this would you prefer?

not sure what the problem is exactly, but if you repost after
addressing my comments, I can ack the 83xx bits: I just don't like
adding stuff to common/ in a board support patch, so please have
that separated out.

Kim
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Re: [U-Boot] [PATCH 17/39] x86: Add chromebook_link board

[Simon Glass]

Hi Bin,

On 7 November 2014 03:18, Bin Meng  wrote:
>
> Hi Simon,
>
> On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass  wrote:
> > This board is a 'bare' version of the existing 'link 'board. It does not
> > require coreboot to run, but is intended to start directly from the reset
> > vector.
> >
> > This initial commit has place holders for a wide range of features. These
> > will be added in follow-on patches and series. So far it cannot be booted
> > as there is no ROM image produced, but it does build without errors.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> >  arch/x86/Kconfig   |  23 +
> >  arch/x86/cpu/coreboot/coreboot.c   |   8 ++
> >  arch/x86/cpu/cpu.c |  32 --
> >  arch/x86/cpu/ivybridge/Kconfig | 157 
> > +
> >  arch/x86/cpu/ivybridge/Makefile|   9 ++
> >  arch/x86/cpu/ivybridge/car.S   |  20 
> >  arch/x86/cpu/ivybridge/cpu.c   |  41 
> >  arch/x86/cpu/ivybridge/sdram.c |  20 
> >  arch/x86/dts/Makefile  |   1 +
> >  arch/x86/dts/chromebook_link.dts   |   1 +
> >  arch/x86/include/asm/arch-ivybridge/gpio.h |  10 ++
> >  arch/x86/include/asm/processor.h   |  12 +++
> >  board/google/chromebook_link/Kconfig   |  15 +++
> >  board/google/chromebook_link/MAINTAINERS   |   6 ++
> >  board/google/chromebook_link/Makefile  |  15 +++
> >  board/google/chromebook_link/link.c|  17 
> >  configs/chromebook_link_defconfig  |  10 ++
> >  include/configs/chromebook_link.h  |  53 ++
> >  18 files changed, 443 insertions(+), 7 deletions(-)
> >  create mode 100644 arch/x86/cpu/ivybridge/Kconfig
> >  create mode 100644 arch/x86/cpu/ivybridge/Makefile
> >  create mode 100644 arch/x86/cpu/ivybridge/car.S
> >  create mode 100644 arch/x86/cpu/ivybridge/cpu.c
> >  create mode 100644 arch/x86/cpu/ivybridge/sdram.c
> >  create mode 12 arch/x86/dts/chromebook_link.dts
> >  create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
> >  create mode 100644 board/google/chromebook_link/Kconfig
> >  create mode 100644 board/google/chromebook_link/MAINTAINERS
> >  create mode 100644 board/google/chromebook_link/Makefile
> >  create mode 100644 board/google/chromebook_link/link.c
> >  create mode 100644 configs/chromebook_link_defconfig
> >  create mode 100644 include/configs/chromebook_link.h
> >
> > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> > index 0dba8ac..07ff149 100644
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -12,9 +12,32 @@ choice
> >
> >  config TARGET_COREBOOT
> > bool "Support coreboot"
> > +   help
> > + This target is used for running U-Boot on top of Coreboot. In
> > + this case Coreboot does the early inititalisation, and U-Boot
> > + takes over once the RAM, video and CPU are fully running.
> > + U-Boot is loaded as a fallback payload from Coreboot, in
> > + Coreboot terminology. This method was used for the Chromebook
> > + Pixel when launched.
> > +
> > +config TARGET_CHROMEBOOK_LINK
> > +   bool "Support Chromebook link"
> > +   help
> > + This is the Chromebook Pixel released in 2013. It uses an Intel
> > + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
> > + SDRAM. It has a Panther Point peripheral controller hub, PCIe
>
> Intel official name is 'platform controller hub'.


OK I'll update this.

>
>
> > + WiFi and Bluetooth. It also includes a 720p webcam, USB SD
> > + reader, microphone and speakers, display port and 32GB SATA
> > + solid state drive. There is a Chrome OS EC connected on LPC,
> > + and it provides a 2560x1700 high resolution touch-enabled LCD
> > + display.
> >
> >  endchoice
> >
> > +source "arch/x86/cpu/ivybridge/Kconfig"
> > +
> >  source "board/chromebook-x86/coreboot/Kconfig"
>
> Not related to this patch, but do you consider renaming
> 'board/chromebook-x86/' to something like 'board/generic-x86/' since
> this build of U-Boot is supposed to run as a payload from coreboot on
> every board that coreboot supports in theory.

Possibly, although it isn't really generic. Probably we should just
use the name coreboot consistently. Actually I think I had this
discussion with the original author but he wasn't having it...


[snip]

Regards,
Simon
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Re: [U-Boot] [PATCH 5/5] arm: socfpga: Add example UDC config

[Marek Vasut]

On Friday, November 07, 2014 at 03:40:00 PM, Lukasz Majewski wrote:
> Hi Marek,
> 
> > Add example of an USB UDC configuration with DFU and UMS.
> > 
> > Signed-off-by: Marek Vasut 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Vince Bridgers 
> > Cc: Pavel Machek 
> > Cc: Stefan Roese 
> > Cc: Lukasz Majewski 
> > ---
> > 
> >  board/altera/socfpga/socfpga_cyclone5.c | 21 +
> >  include/configs/socfpga_common.h| 30
> > 
> > +- 2 files changed, 50 insertions(+), 1
> > deletion(-)
> > 
> > diff --git a/board/altera/socfpga/socfpga_cyclone5.c
> > b/board/altera/socfpga/socfpga_cyclone5.c index 0f81d89..ce625e5
> > 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c
> > +++ b/board/altera/socfpga/socfpga_cyclone5.c
> > @@ -8,6 +8,10 @@
> > 
> >  #include 
> >  #include 
> > 
> > +#include 
> > +#include 
> > +#include 
> > +
> > 
> >  #include 
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> > 
> > @@ -39,3 +43,20 @@ int board_init(void)
> > 
> > return 0;
> >  
> >  }
> > 
> > +
> > +#ifdef CONFIG_USB_GADGET
> > +struct s3c_plat_otg_data socfpga_otg_data = {
> > +   .regs_otg   = CONFIG_USB_DWC2_REG_ADDR,
> > +   .usb_gusbcfg= 0x1417,
> > +};
> > +
> > +int board_usb_init(int index, enum usb_init_type init)
> > +{
> > +   return s3c_udc_probe(&socfpga_otg_data);
> > +}
> > +
> > +int g_dnl_board_usb_cable_connected(void)
> > +{
> > +   return 1;
> > +}
> > +#endif
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h index 1df886b..9823be6 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -37,7 +37,7 @@
> > 
> >   */
> >  
> >  #define CONFIG_NR_DRAM_BANKS   1
> >  #define PHYS_SDRAM_1   0x0
> > 
> > -#define CONFIG_SYS_MALLOC_LEN  (10 * 1024 * 1024)
> > +#define CONFIG_SYS_MALLOC_LEN  (64 * 1024 * 1024)
> > 
> >  #define CONFIG_SYS_MEMTEST_START   PHYS_SDRAM_1
> >  #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
> > 
> > @@ -191,6 +191,34 @@
> > 
> >  #endif
> >  
> >  /*
> > 
> > + * USB Gadget (DFU, UMS)
> > + */
> > +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
> > +#define CONFIG_USB_GADGET
> > +#define CONFIG_USB_GADGET_S3C_UDC_OTG
> > +#define CONFIG_USB_GADGET_DUALSPEED
> > +#define CONFIG_USB_GADGET_VBUS_DRAW2
> > +
> > +/* USB Composite download gadget - g_dnl */
> > +#define CONFIG_USBDOWNLOAD_GADGET
> > +#define CONFIG_USB_GADGET_MASS_STORAGE
> > +
> > +#define CONFIG_DFU_FUNCTION
> > +#define CONFIG_DFU_MMC
> > +#define CONFIG_SYS_DFU_DATA_BUF_SIZE   (32 * 1024 * 1024)
> > +#define DFU_DEFAULT_POLL_TIMEOUT   300
> > +
> > +/* USB IDs */
> > +#define CONFIG_G_DNL_VENDOR_NUM0x0525  /*
> > NetChip */ +#define CONFIG_G_DNL_PRODUCT_NUM0xA4A5  /*
> > Linux-USB File-backed Storage Gadget */ +#define
> > CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define
> > CONFIG_G_DNL_UMS_PRODUCT_NUMCONFIG_G_DNL_PRODUCT_NUM +#ifndef
> > CONFIG_G_DNL_MANUFACTURER +#define
> > CONFIG_G_DNL_MANUFACTURER   "Altera" +#endif
> > +#endif
> > +
> > +/*
> > 
> >   * U-Boot environment
> >   */
> >  
> >  #define CONFIG_SYS_CONSOLE_IS_IN_ENV
> 
> Reviewed-by: Lukasz Majewski 
> Tested-by: Lukasz Majewski 

Queued for master, thanks!
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Re: [U-Boot] [PATCH 3/5] usb: s3c-otg: Split out PHY control

[Marek Vasut]

On Friday, November 07, 2014 at 03:23:42 PM, Lukasz Majewski wrote:
> Hi Marek,
> 
> > On Friday, November 07, 2014 at 11:08:44 AM, Lukasz Majewski wrote:
> > > Hi Marek,
> > > 
> > > > On Friday, November 07, 2014 at 09:59:25 AM, Lukasz Majewski
> > > > 
> > > > wrote:
> > > > > Hi Marek,
> > > > > 
> > > > > > On Tuesday, November 04, 2014 at 08:34:21 PM, Pavel Machek
> > > > > > 
> > > > > > wrote:
> > > > > > > On Tue 2014-11-04 06:07:32, Marek Vasut wrote:
> > > > > > > > Split the Samsung specific PHY control into a separate
> > > > > > > > file and compile this into the S3C OTG driver only if
> > > > > > > > used on a Samsung system.
> > > > > > > > 
> > > > > > > > Signed-off-by: Marek Vasut 
> > > > > > > > Cc: Chin Liang See 
> > > > > > > > Cc: Dinh Nguyen 
> > > > > > > > Cc: Vince Bridgers 
> > > > > > > 
> > > > > > > Acked-by: Pavel Machek 
> > > > > > > 
> > > > > > > I know you are just moving the code, but...
> > > > > > > 
> > > > > > > > +void otg_phy_init(struct s3c_udc *dev)
> > > > > > > > +{
> > > > > > > > +   unsigned int usb_phy_ctrl =
> > > > > > > > dev->pdata->usb_phy_ctrl;
> > > > > > > > +   struct s3c_usbotg_phy *phy =
> > > > > > > > +   (struct s3c_usbotg_phy
> > > > > > > > *)dev->pdata->regs_phy; +
> > > > > > > > +   dev->pdata->phy_control(1);
> > > > > > > > +
> > > > > > > > +   /*USB PHY0 Enable */
> > > > > > > 
> > > > > > > Wrong comment style.
> > > > > > 
> > > > > > I'll fix this one.
> > > > > > 
> > > > > > > > +   printf("USB PHY0 Enable\n");
> > > > > > > > +
> > > > > > > > +   /* Enable PHY */
> > > > > > > > +   writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0,
> > > > > > > > usb_phy_ctrl);
> > > > > > > 
> > > > > > > We have helpers for setting/clearing bits, right?
> > > > > > 
> > > > > > Yes we do, Lukasz ... ? :)
> > > > > 
> > > > > If you think about set_bit()/ clear_bit() functions
> > > > > from ./arch/arm/include/asm/bitops.h, then I don't mind to
> > > > > replace current code with them.
> > > > > 
> > > > > Feel free to use them for next version of the patch.
> > > > 
> > > > Pavel meant clrsetbits_le32() and friends . Personally, I would
> > > > leave that to subsequent set :)
> > > 
> > > This is up to you. I just would like to avoid changing too many
> > > things at once.
> > 
> > Definitelly. Did adding the missing include fix the issues with this
> > patch ?
> 
> I've took the topic/s3c-otg from u-boot-usb repo.
> 
> Reviewed-by: Lukasz Majewski 
> Tested-by: Lukasz Majewski 

Thanks, I'll queue that up for master then.
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Re: [U-Boot] [PATCH 5/5] arm: socfpga: Add example UDC config

[Marek Vasut]

On Friday, November 07, 2014 at 04:28:10 PM, Lukasz Majewski wrote:
> Hi Marek,
> 
> > On Friday, November 07, 2014 at 03:40:00 PM, Lukasz Majewski wrote:
> > > Hi Marek,
> > 
> > [...]
> > 
> > > > + * USB Gadget (DFU, UMS)
> > > > + */
> > > > +#if defined(CONFIG_CMD_DFU) ||
> > > > defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_USB_GADGET
> > > > +#define CONFIG_USB_GADGET_S3C_UDC_OTG
> > > > +#define CONFIG_USB_GADGET_DUALSPEED
> > > > +#define CONFIG_USB_GADGET_VBUS_DRAW2
> > > > +
> > > > +/* USB Composite download gadget - g_dnl */
> > > > +#define CONFIG_USBDOWNLOAD_GADGET
> > > > +#define CONFIG_USB_GADGET_MASS_STORAGE
> > > > +
> > > > +#define CONFIG_DFU_FUNCTION
> > > > +#define CONFIG_DFU_MMC
> > > > +#define CONFIG_SYS_DFU_DATA_BUF_SIZE   (32 * 1024 * 1024)
> > > > +#define DFU_DEFAULT_POLL_TIMEOUT   300
> > > > +
> > > > +/* USB IDs */
> > > > +#define CONFIG_G_DNL_VENDOR_NUM0x0525  /*
> > > > NetChip */ +#define CONFIG_G_DNL_PRODUCT_NUM
> > > > 0xA4A5  /* Linux-USB File-backed Storage Gadget */ +#define
> > > > CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
> > > > +#define CONFIG_G_DNL_UMS_PRODUCT_NUM
> > > > CONFIG_G_DNL_PRODUCT_NUM +#ifndef CONFIG_G_DNL_MANUFACTURER
> > > > +#define CONFIG_G_DNL_MANUFACTURER  "Altera" +#endif
> > > > +#endif
> > > > +
> > > > +/*
> > > > 
> > > >   * U-Boot environment
> > > >   */
> > > >  
> > > >  #define CONFIG_SYS_CONSOLE_IS_IN_ENV
> > > 
> > > Reviewed-by: Lukasz Majewski 
> > 
> > Thanks!
> > 
> > > Tested-by: Lukasz Majewski 
> > 
> > Wow, do you have an SoCFPGA now ? :)
> 
> Nope, but I've tested the patch to be 100% sure :-) (as it was the last
> one)

Thanks!

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] test: ums: Add sleep before unmount directory

[Marek Vasut]

On Friday, November 07, 2014 at 02:05:55 PM, Lukasz Majewski wrote:
> This change helps to run script on machines with quite long uptime.
> Without this the following error emerges:
> 
> File: ./dat_14M.img
> umount: /mnt/tmp-ums-test: device is busy.
> (In some cases useful info about processes that use
>  the device is found by lsof(8) or fuser(1))
> TX: md5sum:083d3d22b542d3ecba61b12d17e03f9f
> mount: /dev/sdd6 already mounted or /mnt/tmp-ums-test busy
> mount: according to mtab, /dev/sdd6 is already mounted on /mnt/tmp-ums-test
> 
> Signed-off-by: Lukasz Majewski 

Why exactly does mount not block until it can unmount the device anyway ?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 4/5] usb: s3c-otg: Allow custom gusbcfg

[Marek Vasut]

On Friday, November 07, 2014 at 03:33:10 PM, Lukasz Majewski wrote:
> Hi Marek,
> 
> > On Friday, November 07, 2014 at 10:11:35 AM, Lukasz Majewski wrote:
> > > Hi Marek,
> > > 
> > > > On Tuesday, November 04, 2014 at 08:36:57 PM, Pavel Machek wrote:
> > > > > On Tue 2014-11-04 06:07:33, Marek Vasut wrote:
> > > > > > Allow passing in a custom configuration of the gusbcfg
> > > > > > register via platform data.
> > > > > > 
> > > > > > Signed-off-by: Marek Vasut 
> > > > > > Cc: Chin Liang See 
> > > > > > Cc: Dinh Nguyen 
> > > > > > Cc: Vince Bridgers 
> > > > > 
> > > > > Acked-by: Pavel Machek 
> > > > > 
> > > > > > debug("Reseting OTG controller\n");
> > > > > > 
> > > > > > -   writel(0<<15/* PHY Low Power Clock
> > > > > > sel*/
> > > > > > +   dflt_gusbcfg =
> > > > > > +   0<<15   /* PHY Low Power Clock
> > > > > > sel*/
> > > > > > 
> > > > > > |1<<14  /* Non-Periodic TxFIFO
> > > > > > 
> > > > > > Rewind Enable*/ |0x5<<10/* Turnaround time*/
> > > > > > 
> > > > > > |0<<9 | 0<<8/* [0:HNP disable,1:HNP
> > > > > > 
> > > > > > enable][ 0:SRP disable*/
> > > > > > 
> > > > > > @@ -413,8 +415,12 @@ static void reconfig_usbd(void)
> > > > > > 
> > > > > > |0<<6   /* 0: high speed utmi+,
> > > > > > 
> > > > > > 1: full speed serial*/ |0<<4/* 0: utmi+,
> > > > > > 1:ulpi*/
> > > > > > 
> > > > > > |1<<3   /* phy i/f  0:8bit,
> > > > > > 
> > > > > > 1:16bit*/
> > > > > > 
> > > > > > -   |0x7<<0,/* HS/FS Timeout**/
> > > > > > -   ®->gusbcfg);
> > > > > > +   |0x7<<0;/* HS/FS Timeout**/
> > > > > > +
> > > > > 
> > > > > "Interesting" comment style. And I'd remove 0x prefixes from
> > > > > constants <8...
> > > > 
> > > > Lukasz, what do you say to just convert those four boards to use
> > > > the gusbcfg platform data afterward ?
> > > 
> > > +1
> > > 
> > > It is a very good idea since we are using the same dwc2 IP block for
> > > host (./usb/host/dwc2.c) and device (s3c_hsotg).
> > 
> > Yep ... I'm just wondering if we should do that rename in the next MW.
> > If you're fine with this MW though, then I will do just that.
> > 
> > > > btw. you can find the latest version in u-boot-usb:topic/s3c-otg
> > > 
> > > I've read comments from Pavel and tested the code up till first
> > > build error :-).
> > 
> > I rewrote that branch, so feel free to use that as a base for your
> > testing. I will repost the corrected patches once I get feedback from
> > you.
> > 
> > Best regards,
> > Marek Vasut
> 
> Reviewed-by: Lukasz Majewski 
> 
> Tested-by: Lukasz Majewski 
> 
> Test HW: Trats2 (Exynos4412)

Queued for master, thanks!
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[U-Boot] [PATCH V4 1/3] usb: eth: fix Makefile

[Rene Griessl]

fix obj-y term

Signed-off-by: Rene Griessl 
---
 drivers/usb/eth/Makefile | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile
index 94551c4..e6ae9f1 100644
--- a/drivers/usb/eth/Makefile
+++ b/drivers/usb/eth/Makefile
@@ -5,8 +5,6 @@
 
 # new USB host ethernet layer dependencies
 obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
-ifdef CONFIG_USB_ETHER_ASIX
-obj-y += asix.o
-endif
+obj-$(CONFIG_USB_ETHER_ASIX) += asix.o
 obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
 obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
-- 
1.9.1

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[U-Boot] [PATCH V4 3/3] usb: eth: enable AX88179 DRIVER for ARNDALE 5250

[Rene Griessl]

Patch enables AX88179 driver for ARNDALE 5250

Signed-off-by: Rene Griessl 
---
 include/configs/arndale.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index f9ee40f..3c2d010 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_ASIX88179
 
 /* MMC SPL */
 #define CONFIG_EXYNOS_SPL
-- 
1.9.1

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[U-Boot] [PATCH V4 2/3] usb: eth: add ASIX AX88179 DRIVER

[Rene Griessl]

This patch adds driver support for the ASIX AX88179 USB3.0 to GbE network
adapter.

Driver has been tested on the RECS5250 COM module (similar to ARDALE5250).
Testcase was DHCP and PXE boot.

Signed-off-by: Rene Griessl 
---
changes for v4:
-added dynamic RX bulk configuration
changes for v3:
-added all compatible devices from linux driver
 from commit cf8bf7cd13804fcb87b5f9ad026d5b823873e8cc
-fixed issues from review
changes for v2:
-added usb_ether.h to change list
-added 2nd patch to enable driver for arndale board

 drivers/usb/eth/Makefile|   1 +
 drivers/usb/eth/asix88179.c | 700 
 drivers/usb/eth/usb_ether.c |   7 +
 include/usb_ether.h |   6 +
 4 files changed, 714 insertions(+)
 create mode 100644 drivers/usb/eth/asix88179.c

diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile
index e6ae9f1..c92d2b0 100644
--- a/drivers/usb/eth/Makefile
+++ b/drivers/usb/eth/Makefile
@@ -6,5 +6,6 @@
 # new USB host ethernet layer dependencies
 obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
 obj-$(CONFIG_USB_ETHER_ASIX) += asix.o
+obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o
 obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
 obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c
new file mode 100644
index 000..b8ca720
--- /dev/null
+++ b/drivers/usb/eth/asix88179.c
@@ -0,0 +1,700 @@
+/*
+ * Copyright (c) 2014 Rene Griessl 
+ * based on the U-Boot Asix driver as well as information
+ * from the Linux AX88179_178a driver
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include "usb_ether.h"
+#include 
+#include 
+
+/* ASIX AX88179 based USB 3.0 Ethernet Devices */
+#define AX88179_PHY_ID 0x03
+#define AX_EEPROM_LEN  0x100
+#define AX88179_EEPROM_MAGIC   0x17900b95
+#define AX_MCAST_FLTSIZE   8
+#define AX_MAX_MCAST   64
+#define AX_INT_PPLS_LINK   (1 << 16)
+#define AX_RXHDR_L4_TYPE_MASK  0x1c
+#define AX_RXHDR_L4_TYPE_UDP   4
+#define AX_RXHDR_L4_TYPE_TCP   16
+#define AX_RXHDR_L3CSUM_ERR2
+#define AX_RXHDR_L4CSUM_ERR1
+#define AX_RXHDR_CRC_ERR   (1 << 29)
+#define AX_RXHDR_DROP_ERR  (1 << 31)
+#define AX_ENDPOINT_INT0x01
+#define AX_ENDPOINT_IN 0x02
+#define AX_ENDPOINT_OUT0x03
+#define AX_ACCESS_MAC  0x01
+#define AX_ACCESS_PHY  0x02
+#define AX_ACCESS_EEPROM   0x04
+#define AX_ACCESS_EFUS 0x05
+#define AX_PAUSE_WATERLVL_HIGH 0x54
+#define AX_PAUSE_WATERLVL_LOW  0x55
+
+#define PHYSICAL_LINK_STATUS   0x02
+   #define AX_USB_SS   (1 << 2)
+   #define AX_USB_HS   (1 << 1)
+
+#define GENERAL_STATUS 0x03
+   #define AX_SECLD(1 << 2)
+
+#define AX_SROM_ADDR   0x07
+#define AX_SROM_CMD0x0a
+   #define EEP_RD  (1 << 2)
+   #define EEP_BUSY(1 << 4)
+
+#define AX_SROM_DATA_LOW   0x08
+#define AX_SROM_DATA_HIGH  0x09
+
+#define AX_RX_CTL  0x0b
+   #define AX_RX_CTL_DROPCRCERR(1 << 8)
+   #define AX_RX_CTL_IPE   (1 << 9)
+   #define AX_RX_CTL_START (1 << 7)
+   #define AX_RX_CTL_AP(1 << 5)
+   #define AX_RX_CTL_AM(1 << 4)
+   #define AX_RX_CTL_AB(1 << 3)
+   #define AX_RX_CTL_AMALL (1 << 1)
+   #define AX_RX_CTL_PRO   (1 << 0)
+   #define AX_RX_CTL_STOP  0
+
+#define AX_NODE_ID 0x10
+#define AX_MULFLTARY   0x16
+
+#define AX_MEDIUM_STATUS_MODE  0x22
+   #define AX_MEDIUM_GIGAMODE  (1 << 0)
+   #define AX_MEDIUM_FULL_DUPLEX   (1 << 1)
+   #define AX_MEDIUM_EN_125MHZ (1 << 3)
+   #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4)
+   #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5)
+   #define AX_MEDIUM_RECEIVE_EN(1 << 8)
+   #define AX_MEDIUM_PS(1 << 9)
+   #define AX_MEDIUM_JUMBO_EN  0x8040
+
+#define AX_MONITOR_MOD 0x24
+   #define AX_MONITOR_MODE_RWLC(1 << 1)
+   #define AX_MONITOR_MODE_RWMP(1 << 2)
+   #define AX_MONITOR_MODE_PMEPOL  (1 << 5)
+   #define AX_MONITOR_MODE_PMETYPE (1 << 6)
+
+#define AX_GPIO_CTRL   0x25
+   #define AX_GPIO_CTRL_GPIO3EN(1 << 7)
+   #define AX_GPIO_CTRL_GPIO

Re: [U-Boot] [PATCH v2] test: ums: Add sleep before unmount directory

[Stephen Warren]

On 11/07/2014 06:05 AM, Lukasz Majewski wrote:

This change helps to run script on machines with quite long uptime.
Without this the following error emerges:

File: ./dat_14M.img
umount: /mnt/tmp-ums-test: device is busy.
 (In some cases useful info about processes that use
  the device is found by lsof(8) or fuser(1))
TX: md5sum:083d3d22b542d3ecba61b12d17e03f9f
mount: /dev/sdd6 already mounted or /mnt/tmp-ums-test busy
mount: according to mtab, /dev/sdd6 is already mounted on /mnt/tmp-ums-test


Reviewed-by: Stephen Warren 

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Re: [U-Boot] [PATCH 5/5] arm: socfpga: Add example UDC config

[Lukasz Majewski]

Hi Marek,

> On Friday, November 07, 2014 at 03:40:00 PM, Lukasz Majewski wrote:
> > Hi Marek,
> [...]
> > > + * USB Gadget (DFU, UMS)
> > > + */
> > > +#if defined(CONFIG_CMD_DFU) ||
> > > defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_USB_GADGET
> > > +#define CONFIG_USB_GADGET_S3C_UDC_OTG
> > > +#define CONFIG_USB_GADGET_DUALSPEED
> > > +#define CONFIG_USB_GADGET_VBUS_DRAW  2
> > > +
> > > +/* USB Composite download gadget - g_dnl */
> > > +#define CONFIG_USBDOWNLOAD_GADGET
> > > +#define CONFIG_USB_GADGET_MASS_STORAGE
> > > +
> > > +#define CONFIG_DFU_FUNCTION
> > > +#define CONFIG_DFU_MMC
> > > +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
> > > +#define DFU_DEFAULT_POLL_TIMEOUT 300
> > > +
> > > +/* USB IDs */
> > > +#define CONFIG_G_DNL_VENDOR_NUM  0x0525  /*
> > > NetChip */ +#define CONFIG_G_DNL_PRODUCT_NUM
> > > 0xA4A5/* Linux-USB File-backed Storage Gadget */ +#define
> > > CONFIG_G_DNL_UMS_VENDOR_NUM   CONFIG_G_DNL_VENDOR_NUM
> > > +#define CONFIG_G_DNL_UMS_PRODUCT_NUM
> > > CONFIG_G_DNL_PRODUCT_NUM +#ifndef CONFIG_G_DNL_MANUFACTURER
> > > +#define CONFIG_G_DNL_MANUFACTURER"Altera" +#endif
> > > +#endif
> > > +
> > > +/*
> > > 
> > >   * U-Boot environment
> > >   */
> > >  
> > >  #define CONFIG_SYS_CONSOLE_IS_IN_ENV
> > 
> > Reviewed-by: Lukasz Majewski 
> 
> Thanks!
> 
> > Tested-by: Lukasz Majewski 
> 
> Wow, do you have an SoCFPGA now ? :)

Nope, but I've tested the patch to be 100% sure :-) (as it was the last
one)

> 
> Best regards,
> Marek Vasut



-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Stefan Roese]

Hi Dinh, Hi Vince!

a quick question for you:

On 07.11.2014 16:04, Marek Vasut wrote:



>> diff --git a/drivers/spi/cadence_qspi_apb.c
>> b/drivers/spi/cadence_qspi_apb.c new file mode 100644
>> index 000..00a115f
>> --- /dev/null
>> +++ b/drivers/spi/cadence_qspi_apb.c
>> @@ -0,0 +1,898 @@
>> +/*
>> + * Copyright (C) 2012 Altera Corporation 
>> + * All rights reserved.
>> + *
>> + * Redistribution and use in source and binary forms, with or without
>> + * modification, are permitted provided that the following conditions are
>> met: + *  - Redistributions of source code must retain the above copyright
>> + *notice, this list of conditions and the following disclaimer. + *
>> - Redistributions in binary form must reproduce the above copyright + *
>> notice, this list of conditions and the following disclaimer in the + *
>> documentation and/or other materials provided with the distribution. + *
>> - Neither the name of the Altera Corporation nor the
>> + *names of its contributors may be used to endorse or promote products
>> + *derived from this software without specific prior written
>> permission. + *
>> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
>> IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
>> TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
>> PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA
>> CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>> EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO,
>> PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR
>> PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF
>> LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING
>> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS
>> SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */
> 
> This license is kinda iffy. What is this all about please ?

Yes, I was wondering about this as well. And in the Linux kernel (Rocketboards)
this file is dual licensed. Here an extract:

<---
/*
 * Driver for Cadence QSPI Controller
 *
 * Copyright (C) 2012 Altera Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 * Redistribution and use in source and binary forms, with or
 * without modification, are permitted provided that the following
 * conditions are met:
 *
 *  - Redistributions of source code must retain the above
 *copyright notice, this list of conditions and the following
 *disclaimer.
 *
 *  - Redistributions in binary form must reproduce the above
 *copyright notice, this list of conditions and the following
 *disclaimer in the documentation and/or other materials
 *provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */
<--

Could we not just use a "plain" GPL (v2) license here as well. Especially
since the other files in this driver are just normal GPL files.

Comments welcome.

Thanks,
Stefan

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Re: [U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Marek Vasut]

On Friday, November 07, 2014 at 12:37:49 PM, Stefan Roese wrote:

Hi!

> This driver is cloned from the Altera Rockerboard.org U-Boot
> repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
> modification to support the U-Boot driver model (DM).
> 
> As mentioned above, in this new version I ported this driver to the
> new driver model (DM). One big advantage of this move is that now
> multiple SPI drivers can be enabled on one platform. And since the
> SoCFPGA also has the Designware SPI master controller integrated,
> this feature is really needed to support both controllers.
> 
> Because of this, this series needs the DT support for SoCFPGA
> to be applied. For DT based probing in the SPI DM.
> 
> Signed-off-by: Stefan Roese 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Simon Glass 
> Cc: Jagannadha Sutradharudu Teki 

[...]

> diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
> new file mode 100644
> index 000..c9a6142
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi.h
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (C) 2012
> + * Altera Corporation 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef __CADENCE_QSPI_H__
> +#define __CADENCE_QSPI_H__
> +
> +#define CQSPI_IS_ADDR(cmd_len)   (cmd_len > 1 ? 1 : 0)
> +
> +#define CQSPI_NO_DECODER_MAX_CS  4
> +#define CQSPI_DECODER_MAX_CS 16
> +#define CQSPI_READ_CAPTURE_MAX_DELAY 16
> +
> +struct cadence_spi_platdata {
> + unsigned intmax_hz;
> + void*regbase;
> + void*ahbbase;
> +
> + u32 page_size;
> + u32 block_size;
> + u32 tshsl_ns;
> + u32 tsd2d_ns;
> + u32 tchsh_ns;
> + u32 tslch_ns;
> +};
> +
> +struct cadence_spi_priv {
> + void*regbase;
> + void*ahbbase;
> + size_t  cmd_len;
> + u8  cmd_buf[32];
> + size_t  data_len;
> +
> + int qspi_is_init;
> + unsigned intqspi_calibrated_hz;
> + unsigned intqspi_calibrated_cs;
> +};
> +
> +/* Functions call declaration */
> +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
> +void cadence_qspi_apb_controller_enable(void *reg_base_addr);
> +void cadence_qspi_apb_controller_disable(void *reg_base_addr);

Is it really necessary to export all these functions ?

[...]

> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c new file mode 100644
> index 000..00a115f
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -0,0 +1,898 @@
> +/*
> + * Copyright (C) 2012 Altera Corporation 
> + * All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are
> met: + *  - Redistributions of source code must retain the above copyright
> + *notice, this list of conditions and the following disclaimer. + * 
> - Redistributions in binary form must reproduce the above copyright + *   
> notice, this list of conditions and the following disclaimer in the + *   
> documentation and/or other materials provided with the distribution. + * 
> - Neither the name of the Altera Corporation nor the
> + *names of its contributors may be used to endorse or promote products
> + *derived from this software without specific prior written
> permission. + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
> IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
> TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
> PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA
> CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
> EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO,
> PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR
> PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF
> LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING
> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS
> SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */

This license is kinda iffy. What is this all about please ?

> +#include 
> +#include 
> +#include 
> +#include "cadence_qspi.h"
> +
> +#define CQSPI_REG_POLL_US(1) /* 1us */
> +#define CQSPI_REG_RETRY  (1)
> +#define CQSPI_POLL_IDLE_RETRY(3)
> +
> +#define CQSPI_FIFO_WIDTH (4)

These braces around numbers should be fixed, but that's not the current 
pressing 
issue here.
[...]
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Re: [U-Boot] [PATCH v3] arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

[Marek Vasut]

On Friday, November 07, 2014 at 02:10:41 PM, Stefan Roese wrote:
> This patch includes the latest DT sources for socfpga from the current
> Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
> "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
> support.
> 
> Until this patch, the only SoCFPGA U-Boot target in mainline is
> "socfpga_cyclone5". This build target is not (yet) changed to support
> DT. So nothing changes for this target. Even though the long-term
> goal should be to move all SoCFPGA targets over to DT.
> 
> One of the reasons to enable DT support in SoCFPGA is, that I need to
> support multiple different SPI controllers for this platform. This is
> the QSPI Cadence controller and the Designware SPI master controller.
> Both are implemented in the SoCFPGA. And enabling both controllers is
> only possible by using the new driver model (DM). The DM SPI code
> only supports DT based probing. So it was easier to move SoCFPGA to
> DT than to add the (deprecated) platform-data based probing to the
> DM SPI suport.
> 
> Note that the image with the dtb embedded is u-boot-dtb.img. This needs
> to be used now for those DT enabled boards instead of u-boot.img.
> 
> Signed-off-by: Stefan Roese 
> Cc: Marek Vasut 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Albert Aribaud 
> Cc: Pavel Machek 
> Cc: Simon Glass 

Applied, thanks!

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: Add DW master SPI clock to clock_manager.c

[Marek Vasut]

On Friday, November 07, 2014 at 01:50:29 PM, Stefan Roese wrote:
> This function will be needed by the upcoming Designware master SPI
> driver.
> 
> Signed-off-by: Stefan Roese 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Marek Vasut 
> Cc: Pavel Machek 

Awww, was this missing ? Thanks!

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

[Marek Vasut]

On Friday, November 07, 2014 at 12:45:51 PM, Peng Fan wrote:
> 在 11/7/2014 7:09 PM, Marek Vasut 写道:
> > On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:
> > 
> > [...]
> > 
>  @@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct
>  usb_ehci *ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 |
>  USBPHY_CTRL_ENUTMILEVEL3);
>  
>   __raw_writel(val, phy_ctrl);
>  
>  -return val & USBPHY_CTRL_OTG_ID;
>  +return board_usb_phy_mode(index);
> >>> 
> >>> This should be called from ehci_hcd_init() right after
> >>> usb_phy_enable(). Afterall, the mode detection has nothing to do with
> >>> the PHY enabling.
> >> 
> >> This back to what I did in patch v2. right after usb_phy_enable(), just
> >> paste that piece of code here:
> >> 
> >> The weak function:
> >> +int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
> >> +{
> >> +   return 0;
> >> +}
> >> +
> >> 
> >>   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
> >> USB_INIT_HOST;
> >> 
> >> +   board_usb_phy_mode(index, &type);
> >> +
> > 
> > The usb_phy_enable() should not return the PHY mode at all though.
> > It should be the board_usb_phy_mode() which adjusts the PHY type.
> > The usb_phy_enable() should return just a success/failure return
> > value.
> 
> ok. got it.
> 
> >> What need to do is to let board can modify the `type` like following:
> >> +int board_usb_phy_mode(int port, enum usb_init_type *type)
> >> +{
> >> +  if (port == 1)
> >> +   /* port1 works in HOST Mode */
> >> +  *type = USB_INIT_HOST;
> >> +
> >> +   return 0;
> >> +}
> >> +
> >> This is the way that I did in patch v2. If this is fine, I'll resent
> >> this patch set.
> > 
> > It should really explicitly set it, not modify it, see above.
> 
> I have an idea about this patch:
> 1. usb_phy_enable will not be touched.
> 2. replace "type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
> USB_INIT_HOST;" with "usb_phy_enable(index, ehci)".
> 3. right after usb_phy_enable, add this line "type =
> board_usb_phy_mode(index)" or "type = board_usb_phy_mode((struct usb_phy
> *)PHY_ADDRESS)". Here I also think pass phy register definition to board
> level code is not fine just as what we talked about passing ehci struct
> to board level code in patch v2.
> 4. in ehci-mx6.c, implement the weak function "int __weak
> board_usb_phy_mode(xxx)", and it's return value is the mode, HOST or
> DEVICE. If the board code want to implement this function, just return
> what the board want.
> 
> After all, this patch may looks like this:
> In ehci-mx6.c
> +int __weak board_usb_phy_mode(int port)
> +{
> +   void __iomem *phy_reg;
> +   void __iomem *phy_ctrl;
> +   u32 val;
> +
> +   phy_reg = (void __iomem *)phy_bases[port];
> +   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
> +
> +   val = __raw_readl(phy_ctrl);
> +
> +   return val & USBPHY_CTRL_OTG_ID;
> +}
> +
> 
> - type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
> + usb_phy_enable(index, ehci);
> + type = board_usb_phy_mode(index);
> 
> in board code, which is not in this patch, just list here:
> +int board_usb_phy_mode(int port)
> +{
> + if (port == 1)
> + return USB_INIT_HOST;
> + else
> + return USB_INIT_DEVICE;
> +}
> I just want to keep it simple and do not want to touch usb phy register
> in board code.
> 
> Any ideas?

This seems OKish for all but the part where usb_phy_enable() shouldn't be 
touched. The return value of usb_phy_enable() should really be a regular
return code, not the PHY mode.

You can also still implement a function to query a PHY for it's mode, so you 
don't need to explicitly read the USBPHY_CTRL_OTG_ID in the board code.
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Re: [U-Boot] [PATCH 3/4 v4] arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver

[Marek Vasut]

On Friday, November 07, 2014 at 12:37:51 PM, Stefan Roese wrote:
> Without this alias, DM based probing does not work. So lets add this
> alias to get the bus numbering correct.
> 
> Signed-off-by: Stefan Roese 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Simon Glass 
> Cc: Jagannadha Sutradharudu Teki 

Just a really minor nit, while picking those patches into a temporary branch so 
they don't get lost, I see this.

Applying: arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver
/work/U-Boot/upstream/u-boot-socfpga/.git/rebase-apply/patch:13: space before 
tab in indent.
aliases {
/work/U-Boot/upstream/u-boot-socfpga/.git/rebase-apply/patch:15: space before 
tab in indent.
};
warning: 2 lines add whitespace errors.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Marek Vasut]

On Friday, November 07, 2014 at 01:50:31 PM, Stefan Roese wrote:
> This patch adds the driver for the Designware master SPI controller. This
> IP core is integrated on the Altera SoCFPGA. This implementation is a
> driver model (DM) implementation. So multiple SPI drivers can be used.
> Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
> used to connect the SPI NOR flashes. Without DM, using multiple SPI
> driver is not possible.
> 
> This driver is very loosly based on the Linux driver. Most of the Linux
> driver is removed. Only the polling loop for the transfer is really used
> from this driver. As we don't support interrupts and DMA right now.
> 
> This is tested on the SoCrates SoCFPGA board using the SPI pins on the
> P14 header.
> 
> Signed-off-by: Stefan Roese 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Simon Glass 
> Cc: Jagannadha Sutradharudu Teki 

[...]

> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> new file mode 100644
> index 000..1bc0d04
> --- /dev/null
> +++ b/drivers/spi/designware_spi.c
> @@ -0,0 +1,425 @@
> +/*
> + * Designware master SPI core controller driver
> + *
> + * Copyright (C) 2014 Stefan Roese 
> + *
> + * Very loosly based on the Linux driver version which is:
> + * Copyright (c) 2009, Intel Corporation.
> + *
> + * SPDX-License-Identifier:  GPL-2.0

What's the agreement about the licensing now, GPL-2.0 or GPL-2.0+ ?

[...]

> +static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
> +{
> + return __raw_readl(priv->regs + offset);
> +}

Do we really need these wrappers ?

[...]

Thanks!
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Re: [U-Boot] [PATCH 5/5] arm: socfpga: Add example UDC config

[Marek Vasut]

On Friday, November 07, 2014 at 03:40:00 PM, Lukasz Majewski wrote:
> Hi Marek,
[...]
> > + * USB Gadget (DFU, UMS)
> > + */
> > +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
> > +#define CONFIG_USB_GADGET
> > +#define CONFIG_USB_GADGET_S3C_UDC_OTG
> > +#define CONFIG_USB_GADGET_DUALSPEED
> > +#define CONFIG_USB_GADGET_VBUS_DRAW2
> > +
> > +/* USB Composite download gadget - g_dnl */
> > +#define CONFIG_USBDOWNLOAD_GADGET
> > +#define CONFIG_USB_GADGET_MASS_STORAGE
> > +
> > +#define CONFIG_DFU_FUNCTION
> > +#define CONFIG_DFU_MMC
> > +#define CONFIG_SYS_DFU_DATA_BUF_SIZE   (32 * 1024 * 1024)
> > +#define DFU_DEFAULT_POLL_TIMEOUT   300
> > +
> > +/* USB IDs */
> > +#define CONFIG_G_DNL_VENDOR_NUM0x0525  /*
> > NetChip */ +#define CONFIG_G_DNL_PRODUCT_NUM0xA4A5  /*
> > Linux-USB File-backed Storage Gadget */ +#define
> > CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define
> > CONFIG_G_DNL_UMS_PRODUCT_NUMCONFIG_G_DNL_PRODUCT_NUM +#ifndef
> > CONFIG_G_DNL_MANUFACTURER +#define
> > CONFIG_G_DNL_MANUFACTURER   "Altera" +#endif
> > +#endif
> > +
> > +/*
> > 
> >   * U-Boot environment
> >   */
> >  
> >  #define CONFIG_SYS_CONSOLE_IS_IN_ENV
> 
> Reviewed-by: Lukasz Majewski 

Thanks!

> Tested-by: Lukasz Majewski 

Wow, do you have an SoCFPGA now ? :)

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 06/39] x86: config: Move common x86 configs to a common file

[Bin Meng]

Hi Simon,

On Fri, Nov 7, 2014 at 4:19 AM, Simon Glass  wrote:
> Many of the x86 CONFIG options will be common across different boards. Move
> them to a common file.
>
> Signed-off-by: Simon Glass 
> ---
>
>  include/configs/coreboot.h   | 289 
> ++-
>  include/configs/x86-common.h | 272 
>  2 files changed, 285 insertions(+), 276 deletions(-)
>  create mode 100644 include/configs/x86-common.h
>
> diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
> index fef267f..9ac5306 100644
> --- a/include/configs/coreboot.h
> +++ b/include/configs/coreboot.h
> @@ -6,7 +6,6 @@
>   * SPDX-License-Identifier:GPL-2.0+
>   */
>
> -#include 
>  /*
>   * board/config.h - configuration options, board specific
>   */
> @@ -14,27 +13,15 @@
>  #ifndef __CONFIG_H
>  #define __CONFIG_H
>
> -/*
> - * High Level Configuration Options
> - * (easy to change)
> - */
> -#define CONFIG_SYS_COREBOOT
> -#define CONFIG_SHOW_BOOT_PROGRESS
> -#define CONFIG_LAST_STAGE_INIT
> -#define CONFIG_SYS_VSNPRINTF
> -#define CONFIG_ZBOOT_32
> -#define CONFIG_PHYSMEM
> -#define CONFIG_SYS_EARLY_PCI_INIT
> -#define CONFIG_DISPLAY_BOARDINFO_LATE
> -#define CONFIG_DISPLAY_CPUINFO
> +#include 
>
> -#define CONFIG_DM
> -#define CONFIG_CMD_DM
> -#define CONFIG_DM_GPIO
> -#define CONFIG_DM_SERIAL
> +#define CONFIG_SYS_CAR_ADDR0x1920
> +#define CONFIG_SYS_CAR_SIZE(16 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
>
> -#define CONFIG_LMB
> -#define CONFIG_OF_LIBFDT
> +#define CONFIG_TRACE_EARLY_SIZE(8 << 20)
> +#define CONFIG_TRACE_EARLY
> +#define CONFIG_TRACE_EARLY_ADDR0x0140
>
>  #define CONFIG_BOOTSTAGE
>  #define CONFIG_BOOTSTAGE_REPORT
> @@ -45,278 +32,28 @@
>  #define CONFIG_BOOTSTAGE_STASH_SIZE0x7fc
>  #define CONFIG_BOOTSTAGE_USER_COUNT60
>
> -#define CONFIG_LZO
> -#define CONFIG_FIT
> -#undef CONFIG_ZLIB
> -#undef CONFIG_GZIP
> -#define CONFIG_SYS_BOOTM_LEN   (16 << 20)
> -
> -/*---
> - * Watchdog Configuration
> - */
> -#undef CONFIG_WATCHDOG
> -#undef CONFIG_HW_WATCHDOG
> -
> -/* SATA AHCI storage */
> -
> -#define CONFIG_SCSI_AHCI
> -
> -#ifdef CONFIG_SCSI_AHCI
> -#define CONFIG_LIBATA
> -#define CONFIG_SYS_64BIT_LBA
> -#define CONFIG_SATA_INTEL  1
> -#define CONFIG_SCSI_DEV_LIST   {PCI_VENDOR_ID_INTEL, \
> -   PCI_DEVICE_ID_INTEL_NM10_AHCI},   \
> -   {PCI_VENDOR_ID_INTEL,   \
> -   PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
> -   {PCI_VENDOR_ID_INTEL, \
> -   PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
> -   {PCI_VENDOR_ID_INTEL,   \
> -   PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
> -
> -#define CONFIG_SYS_SCSI_MAX_SCSI_ID2
> -#define CONFIG_SYS_SCSI_MAX_LUN1
> -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
> -CONFIG_SYS_SCSI_MAX_LUN)
> -#endif
> -
> -/* Generic TPM interfaced through LPC bus */
> -#define CONFIG_TPM
> -#define CONFIG_TPM_TIS_LPC
> -#define CONFIG_TPM_TIS_BASE_ADDRESS0xfed4
> -
> -/*---
> - * Real Time Clock Configuration
> - */
> -#define CONFIG_RTC_MC146818
> -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
> -#define CONFIG_SYS_ISA_IO  CONFIG_SYS_ISA_IO_BASE_ADDRESS
> -
> -/*---
> - * Serial Configuration
> +/*
> + * High Level Configuration Options
> + * (easy to change)
>   */
> -#define CONFIG_COREBOOT_SERIAL
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_BAUDRATE115200
> -#define CONFIG_SYS_BAUDRATE_TABLE  {300, 600, 1200, 2400, 4800, \
> -9600, 19200, 38400, 115200}
> -#define CONFIG_SYS_NS16550_PORT_MAPPED
> +#define CONFIG_SYS_COREBOOT
> +#define CONFIG_LAST_STAGE_INIT
>
>  #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
> "stdout=vga,serial,cbmem\0" \
> "stderr=vga,serial,cbmem\0"
>
> -#define CONFIG_CONSOLE_MUX
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> -#define CONFIG_SYS_STDIO_DEREGISTER
>  #define CONFIG_CBMEM_CONSOLE
>
> -#define CONFIG_CMDLINE_EDITING
> -#define CONFIG_COMMAND_HISTORY
> -#define CONFIG_AUTO_COMPLETE
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -#define CONFIG_SUPPORT_VFAT
> -/
> - * ATAPI support (experimental)
> - /
> -#define CONFIG_ATAPI
> -
> -/
> - * DISK Partition support
> - **

Re: [U-Boot] [PATCH 21/39] x86: chromebook_link: Implement CAR support (cache as RAM)

[Simon Glass]

Hi Bin,

On 7 November 2014 07:07, Bin Meng  wrote:
> Hi Simon,
>
> On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass  wrote:
>> Add support for CAR so that we have memory to use prior to DRAM init.
>> On link there is a total of 128KB of CAR available, although some is
>> used for the memory reference code.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/Kconfig |  16 
>>  arch/x86/cpu/ivybridge/car.S | 156 
>> ++-
>>  arch/x86/cpu/ivybridge/cpu.c |   2 +
>>  arch/x86/include/asm/mtrr.h  | 121 +++
>>  arch/x86/include/asm/post.h  |  13 ++-
>>  board/google/chromebook_link/Kconfig |  12 +++
>>  6 files changed, 318 insertions(+), 2 deletions(-)
>>  create mode 100644 arch/x86/include/asm/mtrr.h
>>
>> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
>> index d9ce129..73fe8b2 100644
>> --- a/arch/x86/Kconfig
>> +++ b/arch/x86/Kconfig
>> @@ -34,6 +34,22 @@ config TARGET_CHROMEBOOK_LINK
>>
>>  endchoice
>>
>> +config RAMBASE
>> +   hex
>> +   default 0x10
>> +
>> +config RAMTOP
>> +   hex
>> +   default 0x20
>> +
>> +config XIP_ROM_SIZE
>> +   hex
>> +   default 0x1
>> +
>> +config CPU_ADDR_BITS
>> +   int
>> +   default 36
>> +
>>  config ROM_SIZE
>> hex
>> default 0x80
>> diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S
>> index 0480813..391f6df 100644
>> --- a/arch/x86/cpu/ivybridge/car.S
>> +++ b/arch/x86/cpu/ivybridge/car.S
>> @@ -12,9 +12,163 @@
>>   */
>>
>>  #include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
>> +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
>
> Should these macros be all capital?

Yes I'll fix that. I had in mind keeping it similar to where it came
from, but there are lots of changes needed so it's not worth it.

>
>> +#define CACHE_AS_RAM_SIZE  CONFIG_DCACHE_RAM_SIZE
>> +#define CACHE_AS_RAM_BASE  CONFIG_DCACHE_RAM_BASE
>> +
>> +/* Cache 4GB - MRC_SIZE_KB for MRC */
>> +#define CACHE_MRC_BYTES((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
>> +#define CACHE_MRC_BASE (0x - CACHE_MRC_BYTES)
>> +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
>> +
>> +#define CPU_PHYSMASK_HI(1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
>> +
>> +#define NoEvictMod_MSR 0x2e0
>
> Ditto.
>
>> /* Note: ebp must not be touched in this code */
>
> I think mentioning ebp holds the value of BIST would help more?

OK

>
>>  .globl car_init
>>  car_init:
>> -   /* TODO: Add cache-as-RAM init here */
>> +   post_code(POST_CAR_START)
>> +
>> +   /* Send INIT IPI to all excluding ourself */
>> +   movl$0x000C4500, %eax
>> +   movl$0xFEE00300, %esi
>> +   movl%eax, (%esi)
>> +
>> +   /* All CPUs need to be in Wait for SIPI state */
>> +wait_for_sipi:
>> +   movl(%esi), %eax
>> +   bt  $12, %eax
>> +   jc  wait_for_sipi
>
> Is this a must to send INIT IPI before CAR initialization?

I'll test it.

[snip]

Regards,
Simon
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Re: [U-Boot] [PATCH 20/39] x86: Emit post codes in startup code

[Simon Glass]

Hi Bin,

On 7 November 2014 06:37, Bin Meng  wrote:
> Hi Simon,
>
> On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass  wrote:
>> On x86 it is common to use 'post codes' which are 8-bit hex values emitted
>> from the code and visible to the user. Traditionally two 7-segment displays
>> were made available on the motherboard to show the last post code that was
>> emitted. This allows diagnosis of a boot problem since it is possible to
>> see where the code got to before it died.
>>
>> On modern hardware these codes are not normally visible. On Chromebooks
>> they are displayed by the Embedded Controller (EC), so it is useful to emit
>> them. We must enable this feature for the EC to see the codes, so add an
>> option for this.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/cpu/coreboot/coreboot.c |  3 ++-
>>  arch/x86/cpu/start.S | 25 +
>>  arch/x86/include/asm/post.h  | 32 
>>  board/google/chromebook_link/Kconfig |  4 
>>  4 files changed, 63 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/x86/include/asm/post.h
>>
>> diff --git a/arch/x86/cpu/coreboot/coreboot.c 
>> b/arch/x86/cpu/coreboot/coreboot.c
>> index 257faa1..cc7398f 100644
>> --- a/arch/x86/cpu/coreboot/coreboot.c
>> +++ b/arch/x86/cpu/coreboot/coreboot.c
>> @@ -15,6 +15,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -68,7 +69,7 @@ void show_boot_progress(int val)
>> gd->arch.tsc_prev = now;
>> }
>>  #endif
>> -   outb(val, 0x80);
>> +   outb(val, POST_PORT);
>>  }
>>
>>  int last_stage_init(void)
>> diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
>> index 7f41475..f62ffeb 100644
>> --- a/arch/x86/cpu/start.S
>> +++ b/arch/x86/cpu/start.S
>> @@ -13,6 +13,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -60,6 +61,28 @@ _start:
>> movw%ax, %es
>> movw%ax, %ss
>>
>> +   /* Enable post codes to EC */
>> +#ifdef CONFIG_EARLY_POST_CROS_EC
>> +   mov$0x1b, %ecx
>> +   rdmsr
>> +   and$0x100, %eax
>> +   test   %eax, %eax
>> +   je 2f
>> +
>> +   mov$0x8000f8f0, %eax
>> +   mov$0xcf8, %dx
>> +   out%eax, (%dx)
>> +   mov$0xfed1c001, %eax
>> +   mov$0xcfc, %dx
>> +   out%eax, (%dx)
>> +   mov$0xfed1f410, %esp
>> +   mov(%esp), %eax
>> +   and$0xfffb, %eax
>> +   mov%eax, (%esp)
>> +2:
>> +#endif
>
> IMHO the early_board_init() removal should be rolled back, and the
> enable post codes is better to put there.

Yes I was thinking about that, I'll make that change.

>
>> +   post_code(POST_START)
>> +
>> /* Clear the interrupt vectors */
>> lidtblank_idt_ptr
>>
>> @@ -91,6 +114,7 @@ car_init_ret:
>>
>> /* Align global data to 16-byte boundary */
>> andl$0xfff0, %esp
>> +   post_code(POST_START_STACK)
>>
>> /* Zero the global data since it won't happen later */
>> xorl%eax, %eax
>> @@ -126,6 +150,7 @@ car_init_ret:
>> callsetup_gdt
>>
>> /* Set parameter to board_init_f() to boot flags */
>> +   post_code(POST_START_DONE)
>> xorl%eax, %eax
>>
>> /* Enter, U-boot! */
>> diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
>> new file mode 100644
>> index 000..3371185
>> --- /dev/null
>> +++ b/arch/x86/include/asm/post.h
>> @@ -0,0 +1,32 @@
>> +/*
>> + * Copyright (c) 2014 Google, Inc
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#ifndef _post_h
>> +#define _post_h
>> +
>> +/* port to use for post codes */
>> +#define POST_PORT  0x80
>> +
>> +/* post codes which represent various stages of init */
>> +#define POST_START 0x1e
>> +#define POST_CAR_START 0x1f
>> +
>> +#define POST_START_STACK   0x29
>> +#define POST_START_DONE0x2a
>
> Do we follow some specification about post codes values, or are them
> just some random numbers?

Just random - they're all in one place so we can change them pretty easily.

>
>> +/* Output a post code using al - value must be 0 to 0xff */
>> +#ifdef __ASSEMBLY__
>> +#define post_code(value) \
>> +   movb$value, %al; \
>> +   outb%al, $POST_PORT
>> +#else
>> +static inline void post_code(int code)
>> +{
>> +   outb(code, POST_PORT);
>> +}
>> +#endif
>> +
>> +#endif
>> diff --git a/board/google/chromebook_link/Kconfig 
>> b/board/google/chromebook_link/Kconfig
>> index 975d557..9c715ba 100644
>> --- a/board/google/chromebook_link/Kconfig
>> +++ b/board/google/chromebook_link/Kconfig
>> @@ -12,4 +12,8 @@ config SYS_SOC
>>  config SYS_CONFIG_NAME
>> default "chromebook_link"
>>
>> +config EARLY_POST_CROS_EC
>> +   bool "Enable early post to Chrome OS EC"
>> +   default y
>> +
>>  endif
>> --

Re: [U-Boot] [PATCH 5/5] arm: socfpga: Add example UDC config

[Lukasz Majewski]

Hi Marek,

> Add example of an USB UDC configuration with DFU and UMS.
> 
> Signed-off-by: Marek Vasut 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Vince Bridgers 
> Cc: Pavel Machek 
> Cc: Stefan Roese 
> Cc: Lukasz Majewski 
> ---
>  board/altera/socfpga/socfpga_cyclone5.c | 21 +
>  include/configs/socfpga_common.h| 30
> +- 2 files changed, 50 insertions(+), 1
> deletion(-)
> 
> diff --git a/board/altera/socfpga/socfpga_cyclone5.c
> b/board/altera/socfpga/socfpga_cyclone5.c index 0f81d89..ce625e5
> 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c
> +++ b/board/altera/socfpga/socfpga_cyclone5.c
> @@ -8,6 +8,10 @@
>  #include 
>  #include 
>  
> +#include 
> +#include 
> +#include 
> +
>  #include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
> @@ -39,3 +43,20 @@ int board_init(void)
>  
>   return 0;
>  }
> +
> +#ifdef CONFIG_USB_GADGET
> +struct s3c_plat_otg_data socfpga_otg_data = {
> + .regs_otg   = CONFIG_USB_DWC2_REG_ADDR,
> + .usb_gusbcfg= 0x1417,
> +};
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + return s3c_udc_probe(&socfpga_otg_data);
> +}
> +
> +int g_dnl_board_usb_cable_connected(void)
> +{
> + return 1;
> +}
> +#endif
> diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h index 1df886b..9823be6 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -37,7 +37,7 @@
>   */
>  #define CONFIG_NR_DRAM_BANKS 1
>  #define PHYS_SDRAM_1 0x0
> -#define CONFIG_SYS_MALLOC_LEN(10 * 1024 * 1024)
> +#define CONFIG_SYS_MALLOC_LEN(64 * 1024 * 1024)
>  #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
>  #define CONFIG_SYS_MEMTEST_END   PHYS_SDRAM_1_SIZE
>  
> @@ -191,6 +191,34 @@
>  #endif
>  
>  /*
> + * USB Gadget (DFU, UMS)
> + */
> +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_S3C_UDC_OTG
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET_VBUS_DRAW  2
> +
> +/* USB Composite download gadget - g_dnl */
> +#define CONFIG_USBDOWNLOAD_GADGET
> +#define CONFIG_USB_GADGET_MASS_STORAGE
> +
> +#define CONFIG_DFU_FUNCTION
> +#define CONFIG_DFU_MMC
> +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
> +#define DFU_DEFAULT_POLL_TIMEOUT 300
> +
> +/* USB IDs */
> +#define CONFIG_G_DNL_VENDOR_NUM  0x0525  /*
> NetChip */ +#define CONFIG_G_DNL_PRODUCT_NUM  0xA4A5  /*
> Linux-USB File-backed Storage Gadget */ +#define
> CONFIG_G_DNL_UMS_VENDOR_NUM   CONFIG_G_DNL_VENDOR_NUM +#define
> CONFIG_G_DNL_UMS_PRODUCT_NUM  CONFIG_G_DNL_PRODUCT_NUM +#ifndef
> CONFIG_G_DNL_MANUFACTURER +#define
> CONFIG_G_DNL_MANUFACTURER "Altera" +#endif
> +#endif
> +
> +/*
>   * U-Boot environment
>   */
>  #define CONFIG_SYS_CONSOLE_IS_IN_ENV

Reviewed-by: Lukasz Majewski 
Tested-by: Lukasz Majewski 

-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH 4/5] usb: s3c-otg: Allow custom gusbcfg

[Lukasz Majewski]

Hi Marek,

> On Friday, November 07, 2014 at 10:11:35 AM, Lukasz Majewski wrote:
> > Hi Marek,
> > 
> > > On Tuesday, November 04, 2014 at 08:36:57 PM, Pavel Machek wrote:
> > > > On Tue 2014-11-04 06:07:33, Marek Vasut wrote:
> > > > > Allow passing in a custom configuration of the gusbcfg
> > > > > register via platform data.
> > > > > 
> > > > > Signed-off-by: Marek Vasut 
> > > > > Cc: Chin Liang See 
> > > > > Cc: Dinh Nguyen 
> > > > > Cc: Vince Bridgers 
> > > > 
> > > > Acked-by: Pavel Machek 
> > > > 
> > > > >   debug("Reseting OTG controller\n");
> > > > > 
> > > > > - writel(0<<15/* PHY Low Power Clock
> > > > > sel*/
> > > > > + dflt_gusbcfg =
> > > > > + 0<<15   /* PHY Low Power Clock
> > > > > sel*/
> > > > > 
> > > > >   |1<<14  /* Non-Periodic TxFIFO
> > > > > 
> > > > > Rewind Enable*/ |0x5<<10  /* Turnaround time*/
> > > > > 
> > > > >   |0<<9 | 0<<8/* [0:HNP disable,1:HNP
> > > > > 
> > > > > enable][ 0:SRP disable*/
> > > > > 
> > > > > @@ -413,8 +415,12 @@ static void reconfig_usbd(void)
> > > > > 
> > > > >   |0<<6   /* 0: high speed utmi+,
> > > > > 1: full speed serial*/ |0<<4  /* 0: utmi+,
> > > > > 1:ulpi*/
> > > > > 
> > > > >   |1<<3   /* phy i/f  0:8bit,
> > > > > 
> > > > > 1:16bit*/
> > > > > 
> > > > > - |0x7<<0,/* HS/FS Timeout**/
> > > > > - ®->gusbcfg);
> > > > > + |0x7<<0;/* HS/FS Timeout**/
> > > > > +
> > > > 
> > > > "Interesting" comment style. And I'd remove 0x prefixes from
> > > > constants <8...
> > > 
> > > Lukasz, what do you say to just convert those four boards to use
> > > the gusbcfg platform data afterward ?
> > 
> > +1
> > 
> > It is a very good idea since we are using the same dwc2 IP block for
> > host (./usb/host/dwc2.c) and device (s3c_hsotg).
> 
> Yep ... I'm just wondering if we should do that rename in the next MW.
> If you're fine with this MW though, then I will do just that.
> 
> > > btw. you can find the latest version in u-boot-usb:topic/s3c-otg
> > 
> > I've read comments from Pavel and tested the code up till first
> > build error :-).
> 
> I rewrote that branch, so feel free to use that as a base for your
> testing. I will repost the corrected patches once I get feedback from
> you.
> 
> Best regards,
> Marek Vasut

Reviewed-by: Lukasz Majewski 

Tested-by: Lukasz Majewski 

Test HW: Trats2 (Exynos4412)

-- 
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Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH 3/5] usb: s3c-otg: Split out PHY control

[Lukasz Majewski]

Hi Marek,

> On Friday, November 07, 2014 at 11:08:44 AM, Lukasz Majewski wrote:
> > Hi Marek,
> > 
> > > On Friday, November 07, 2014 at 09:59:25 AM, Lukasz Majewski
> > > wrote:
> > > > Hi Marek,
> > > > 
> > > > > On Tuesday, November 04, 2014 at 08:34:21 PM, Pavel Machek
> > > > > wrote:
> > > > > > On Tue 2014-11-04 06:07:32, Marek Vasut wrote:
> > > > > > > Split the Samsung specific PHY control into a separate
> > > > > > > file and compile this into the S3C OTG driver only if
> > > > > > > used on a Samsung system.
> > > > > > > 
> > > > > > > Signed-off-by: Marek Vasut 
> > > > > > > Cc: Chin Liang See 
> > > > > > > Cc: Dinh Nguyen 
> > > > > > > Cc: Vince Bridgers 
> > > > > > 
> > > > > > Acked-by: Pavel Machek 
> > > > > > 
> > > > > > I know you are just moving the code, but...
> > > > > > 
> > > > > > > +void otg_phy_init(struct s3c_udc *dev)
> > > > > > > +{
> > > > > > > + unsigned int usb_phy_ctrl =
> > > > > > > dev->pdata->usb_phy_ctrl;
> > > > > > > + struct s3c_usbotg_phy *phy =
> > > > > > > + (struct s3c_usbotg_phy
> > > > > > > *)dev->pdata->regs_phy; +
> > > > > > > + dev->pdata->phy_control(1);
> > > > > > > +
> > > > > > > + /*USB PHY0 Enable */
> > > > > > 
> > > > > > Wrong comment style.
> > > > > 
> > > > > I'll fix this one.
> > > > > 
> > > > > > > + printf("USB PHY0 Enable\n");
> > > > > > > +
> > > > > > > + /* Enable PHY */
> > > > > > > + writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0,
> > > > > > > usb_phy_ctrl);
> > > > > > 
> > > > > > We have helpers for setting/clearing bits, right?
> > > > > 
> > > > > Yes we do, Lukasz ... ? :)
> > > > 
> > > > If you think about set_bit()/ clear_bit() functions
> > > > from ./arch/arm/include/asm/bitops.h, then I don't mind to
> > > > replace current code with them.
> > > > 
> > > > Feel free to use them for next version of the patch.
> > > 
> > > Pavel meant clrsetbits_le32() and friends . Personally, I would
> > > leave that to subsequent set :)
> > 
> > This is up to you. I just would like to avoid changing too many
> > things at once.
> 
> Definitelly. Did adding the missing include fix the issues with this
> patch ?
> 

I've took the topic/s3c-otg from u-boot-usb repo.

Reviewed-by: Lukasz Majewski 
Tested-by: Lukasz Majewski 

Test HW: Exynos4412 - Trats2.


> Best regards,
> Marek Vasut



-- 
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Lukasz Majewski

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Re: [U-Boot] [PATCH 21/39] x86: chromebook_link: Implement CAR support (cache as RAM)

[Bin Meng]

Hi Simon,

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass  wrote:
> Add support for CAR so that we have memory to use prior to DRAM init.
> On link there is a total of 128KB of CAR available, although some is
> used for the memory reference code.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/Kconfig |  16 
>  arch/x86/cpu/ivybridge/car.S | 156 
> ++-
>  arch/x86/cpu/ivybridge/cpu.c |   2 +
>  arch/x86/include/asm/mtrr.h  | 121 +++
>  arch/x86/include/asm/post.h  |  13 ++-
>  board/google/chromebook_link/Kconfig |  12 +++
>  6 files changed, 318 insertions(+), 2 deletions(-)
>  create mode 100644 arch/x86/include/asm/mtrr.h
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index d9ce129..73fe8b2 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -34,6 +34,22 @@ config TARGET_CHROMEBOOK_LINK
>
>  endchoice
>
> +config RAMBASE
> +   hex
> +   default 0x10
> +
> +config RAMTOP
> +   hex
> +   default 0x20
> +
> +config XIP_ROM_SIZE
> +   hex
> +   default 0x1
> +
> +config CPU_ADDR_BITS
> +   int
> +   default 36
> +
>  config ROM_SIZE
> hex
> default 0x80
> diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S
> index 0480813..391f6df 100644
> --- a/arch/x86/cpu/ivybridge/car.S
> +++ b/arch/x86/cpu/ivybridge/car.S
> @@ -12,9 +12,163 @@
>   */
>
>  #include 
> +#include 
> +#include 
> +#include 
> +
> +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
> +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)

Should these macros be all capital?

> +#define CACHE_AS_RAM_SIZE  CONFIG_DCACHE_RAM_SIZE
> +#define CACHE_AS_RAM_BASE  CONFIG_DCACHE_RAM_BASE
> +
> +/* Cache 4GB - MRC_SIZE_KB for MRC */
> +#define CACHE_MRC_BYTES((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
> +#define CACHE_MRC_BASE (0x - CACHE_MRC_BYTES)
> +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
> +
> +#define CPU_PHYSMASK_HI(1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
> +
> +#define NoEvictMod_MSR 0x2e0

Ditto.

> /* Note: ebp must not be touched in this code */

I think mentioning ebp holds the value of BIST would help more?

>  .globl car_init
>  car_init:
> -   /* TODO: Add cache-as-RAM init here */
> +   post_code(POST_CAR_START)
> +
> +   /* Send INIT IPI to all excluding ourself */
> +   movl$0x000C4500, %eax
> +   movl$0xFEE00300, %esi
> +   movl%eax, (%esi)
> +
> +   /* All CPUs need to be in Wait for SIPI state */
> +wait_for_sipi:
> +   movl(%esi), %eax
> +   bt  $12, %eax
> +   jc  wait_for_sipi

Is this a must to send INIT IPI before CAR initialization?

> +   post_code(POST_CAR_SIPI)
> +   /* Zero out all fixed range and variable range MTRRs */
> +   movl$mtrr_table, %esi
> +   movl$((mtrr_table_end - mtrr_table) / 2), %edi
> +   xorl%eax, %eax
> +   xorl%edx, %edx
> +clear_mtrrs:
> +   movw(%esi), %bx
> +   movzx   %bx, %ecx
> +   wrmsr
> +   add $2, %esi
> +   dec %edi
> +   jnz clear_mtrrs
> +
> +   post_code(POST_CAR_MTRR)
> +   /* Configure the default memory type to uncacheable */
> +   movl$MTRRdefType_MSR, %ecx
> +   rdmsr
> +   andl$(~0x0cff), %eax
> +   wrmsr
> +
> +   post_code(POST_CAR_UNCACHEABLE)
> +   /* Set Cache-as-RAM base address */
> +   movl$(MTRRphysBase_MSR(0)), %ecx
> +   movl$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
> +   xorl%edx, %edx
> +   wrmsr
> +
> +   post_code(POST_CAR_BASE_ADDRESS)
> +   /* Set Cache-as-RAM mask */
> +   movl$(MTRRphysMask_MSR(0)), %ecx
> +   movl$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
> +   movl$CPU_PHYSMASK_HI, %edx
> +   wrmsr
> +
> +   post_code(POST_CAR_MASK)
> +
> +   /* Enable MTRR */
> +   movl$MTRRdefType_MSR, %ecx
> +   rdmsr
> +   orl $MTRRdefTypeEn, %eax
> +   wrmsr
> +
> +   /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
> +movl   %cr0, %eax
> +   andl$(~(X86_CR0_CD | X86_CR0_NW)), %eax
> +   invd
> +   movl%eax, %cr0
> +
> +   /* enable the 'no eviction' mode */
> +   movl$NoEvictMod_MSR, %ecx
> +   rdmsr
> +   orl $1, %eax
> +   andl$~2, %eax
> +   wrmsr
> +
> +   /* Clear the cache memory region. This will also fill up the cache */
> +   movl$CACHE_AS_RAM_BASE, %esi
> +   movl%esi, %edi
> +   movl$(CACHE_AS_RAM_SIZE / 4), %ecx
> +   xorl%eax, %eax
> +   rep stosl
> +
> +   /* enable the 'no eviction run' state */
> +   movl$NoEvictMod_MSR, %ecx
> +   rdmsr
> +   orl $3, %eax
> +   wrmsr
> +
> +   post_code(POST_CAR_FILL)
> +   /* Enable Cache-as-RAM mode by disabling cache */
> +

Re: [U-Boot] [PATCH 20/39] x86: Emit post codes in startup code

[Bin Meng]

Hi Simon,

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass  wrote:
> On x86 it is common to use 'post codes' which are 8-bit hex values emitted
> from the code and visible to the user. Traditionally two 7-segment displays
> were made available on the motherboard to show the last post code that was
> emitted. This allows diagnosis of a boot problem since it is possible to
> see where the code got to before it died.
>
> On modern hardware these codes are not normally visible. On Chromebooks
> they are displayed by the Embedded Controller (EC), so it is useful to emit
> them. We must enable this feature for the EC to see the codes, so add an
> option for this.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/coreboot/coreboot.c |  3 ++-
>  arch/x86/cpu/start.S | 25 +
>  arch/x86/include/asm/post.h  | 32 
>  board/google/chromebook_link/Kconfig |  4 
>  4 files changed, 63 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/include/asm/post.h
>
> diff --git a/arch/x86/cpu/coreboot/coreboot.c 
> b/arch/x86/cpu/coreboot/coreboot.c
> index 257faa1..cc7398f 100644
> --- a/arch/x86/cpu/coreboot/coreboot.c
> +++ b/arch/x86/cpu/coreboot/coreboot.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -68,7 +69,7 @@ void show_boot_progress(int val)
> gd->arch.tsc_prev = now;
> }
>  #endif
> -   outb(val, 0x80);
> +   outb(val, POST_PORT);
>  }
>
>  int last_stage_init(void)
> diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
> index 7f41475..f62ffeb 100644
> --- a/arch/x86/cpu/start.S
> +++ b/arch/x86/cpu/start.S
> @@ -13,6 +13,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -60,6 +61,28 @@ _start:
> movw%ax, %es
> movw%ax, %ss
>
> +   /* Enable post codes to EC */
> +#ifdef CONFIG_EARLY_POST_CROS_EC
> +   mov$0x1b, %ecx
> +   rdmsr
> +   and$0x100, %eax
> +   test   %eax, %eax
> +   je 2f
> +
> +   mov$0x8000f8f0, %eax
> +   mov$0xcf8, %dx
> +   out%eax, (%dx)
> +   mov$0xfed1c001, %eax
> +   mov$0xcfc, %dx
> +   out%eax, (%dx)
> +   mov$0xfed1f410, %esp
> +   mov(%esp), %eax
> +   and$0xfffb, %eax
> +   mov%eax, (%esp)
> +2:
> +#endif

IMHO the early_board_init() removal should be rolled back, and the
enable post codes is better to put there.

> +   post_code(POST_START)
> +
> /* Clear the interrupt vectors */
> lidtblank_idt_ptr
>
> @@ -91,6 +114,7 @@ car_init_ret:
>
> /* Align global data to 16-byte boundary */
> andl$0xfff0, %esp
> +   post_code(POST_START_STACK)
>
> /* Zero the global data since it won't happen later */
> xorl%eax, %eax
> @@ -126,6 +150,7 @@ car_init_ret:
> callsetup_gdt
>
> /* Set parameter to board_init_f() to boot flags */
> +   post_code(POST_START_DONE)
> xorl%eax, %eax
>
> /* Enter, U-boot! */
> diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
> new file mode 100644
> index 000..3371185
> --- /dev/null
> +++ b/arch/x86/include/asm/post.h
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (c) 2014 Google, Inc
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef _post_h
> +#define _post_h
> +
> +/* port to use for post codes */
> +#define POST_PORT  0x80
> +
> +/* post codes which represent various stages of init */
> +#define POST_START 0x1e
> +#define POST_CAR_START 0x1f
> +
> +#define POST_START_STACK   0x29
> +#define POST_START_DONE0x2a

Do we follow some specification about post codes values, or are them
just some random numbers?

> +/* Output a post code using al - value must be 0 to 0xff */
> +#ifdef __ASSEMBLY__
> +#define post_code(value) \
> +   movb$value, %al; \
> +   outb%al, $POST_PORT
> +#else
> +static inline void post_code(int code)
> +{
> +   outb(code, POST_PORT);
> +}
> +#endif
> +
> +#endif
> diff --git a/board/google/chromebook_link/Kconfig 
> b/board/google/chromebook_link/Kconfig
> index 975d557..9c715ba 100644
> --- a/board/google/chromebook_link/Kconfig
> +++ b/board/google/chromebook_link/Kconfig
> @@ -12,4 +12,8 @@ config SYS_SOC
>  config SYS_CONFIG_NAME
> default "chromebook_link"
>
> +config EARLY_POST_CROS_EC
> +   bool "Enable early post to Chrome OS EC"
> +   default y
> +
>  endif
> --

Regards,
Bin
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[U-Boot] [PATCH v3] arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target

[Stefan Roese]

This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.

Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.

One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.

Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.

Signed-off-by: Stefan Roese 
Cc: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Albert Aribaud 
Cc: Pavel Machek 
Cc: Simon Glass 
---
v3:
- Add missing gpio.h (even if empty). This header is needed for
  lib/fdtdec.c to compile.

v2:
- As mentioned in the commit text, this new version does not move
  the default target to DT (yet). It adds support for the SoCrates
  board now based on this DT support as the first example.
  Nothing changes for the current socfpga_cyclone5 target.
  
 arch/arm/dts/Makefile  |   2 +
 arch/arm/dts/socfpga.dtsi  | 755 +
 arch/arm/dts/socfpga_cyclone5.dtsi |  51 ++
 arch/arm/dts/socfpga_cyclone5_socrates.dts |  50 ++
 arch/arm/include/asm/arch-socfpga/gpio.h   |  10 +
 configs/socfpga_socrates_defconfig |   5 +
 include/dt-bindings/reset/altr,rst-mgr.h   |  90 
 7 files changed, 963 insertions(+)
 create mode 100644 arch/arm/dts/socfpga.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates.dts
 create mode 100644 arch/arm/include/asm/arch-socfpga/gpio.h
 create mode 100644 configs/socfpga_socrates_defconfig
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 52f8926..b946abe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -40,6 +40,8 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
+dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
new file mode 100644
index 000..4472fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga.dtsi
@@ -0,0 +1,755 @@
+/*
+ *  Copyright (C) 2012 Altera 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = &gmac0;
+   ethernet1 = &gmac1;
+   serial0 = &uart0;
+   serial1 = &uart1;
+   timer0 = &timer0;
+   timer1 = &timer1;
+   timer2 = &timer2;
+   timer3 = &timer3;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <&L2>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <&L2>;
+   };
+   };
+
+   intc: intc@fffed000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xfffed000 0x1000>,
+ <0xfffec100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   

Re: [U-Boot] [PATCH] ext4: goni: Modify dfu_alt_info's file names to have absolute path

[Robert Baldyga]

On 11/04/2014 05:21 PM, Lukasz Majewski wrote:
> After the clean up performed in the commit 1151b7ac10b81ecbb the DFU
> subsystem requires absolute patch for correct operation.

s/patch/path

> 
> Signed-off-by: Lukasz Majewski 

Acked-by: Robert Baldyga 

> ---
>  include/configs/s5p_goni.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
> index 0c6e9c7..8ae3e64 100644
> --- a/include/configs/s5p_goni.h
> +++ b/include/configs/s5p_goni.h
> @@ -121,8 +121,8 @@
>  
>  #define CONFIG_DFU_ALT \
>   "u-boot raw 0x80 0x400;" \
> - "uImage ext4 0 2;" \
> - "exynos3-goni.dtb ext4 0 2;" \
> + "/uImage ext4 0 2;" \
> + "/exynos3-goni.dtb ext4 0 2;" \
>   ""PARTS_ROOT" part 0 5\0"
>  
>  #define PARTS_DEFAULT \
> 

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[U-Boot] [PATCH v2] test: ums: Add sleep before unmount directory

[Lukasz Majewski]

This change helps to run script on machines with quite long uptime.
Without this the following error emerges:

File: ./dat_14M.img
umount: /mnt/tmp-ums-test: device is busy.
(In some cases useful info about processes that use
 the device is found by lsof(8) or fuser(1))
TX: md5sum:083d3d22b542d3ecba61b12d17e03f9f
mount: /dev/sdd6 already mounted or /mnt/tmp-ums-test busy
mount: according to mtab, /dev/sdd6 is already mounted on /mnt/tmp-ums-test

Signed-off-by: Lukasz Majewski 
---
Changes for v2:
- Check umount return status code and sleep if needed
---
 test/ums/ums_gadget_test.sh | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/test/ums/ums_gadget_test.sh b/test/ums/ums_gadget_test.sh
index 56d4616..9da486b 100755
--- a/test/ums/ums_gadget_test.sh
+++ b/test/ums/ums_gadget_test.sh
@@ -11,6 +11,7 @@ clear
 
 COLOUR_RED="\33[31m"
 COLOUR_GREEN="\33[32m"
+COLOUR_ORANGE="\33[33m"
 COLOUR_DEFAULT="\33[0m"
 
 DIR=./
@@ -59,8 +60,15 @@ ums_test_file () {
 fi
 
 cp ./$1 $MNT_DIR
-umount $MNT_DIR
 
+while true; do
+   umount $MNT_DIR > /dev/null 2>&1
+   if [ $? -eq 0 ]; then
+   break
+   fi
+   printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n"
+   sleep 1
+done
 
 echo -n "TX: "
 calculate_md5sum $1
-- 
2.0.0.rc2

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[U-Boot] loadb problem. Hangs on START_CHAR

[bomellberg]

Hi.

I'm working on getting u-boot running on a custom board. I am using code
from Emcraft as a starting point. The cpu is NXP LPC4337. The board has
external SDRAM and SPIFI flash, but no wired network.

I can boot u-boot fine, and I can perform some memory operations with md and
mw.

I can load the Hello World standalone example using loads and run it with
go.

I cannot use the loadb command though. The transfer hangs at the beginning.
Using some crude printing debugging I found that the START_CHAR is not
received.

>From cmd_load.c:



I never get the "S", so the transfer never starts. I have tried Tera Term on
Windows and C-Kermit on Linux, using the settings mentioned in the DULG. I
have tried two different USB-to-RS232-3.3V dongles.

A search in the archives shows a possible explanation in FIFO byte order,
but I cannot find a place to alter this. Could it be the FIFO byte order for
the UART is important for the kermit transfer, but not for the console?

An oscilloscope picture of the kermit transfer's first bytes:
 
It sure looks like a 0x01 as the first byte. But the code doesn't reach the
"S" debug.

If I send 0x01 using RealTerm, I get the "S" debug. I can't figure this out.

Thankful for any help.

/Bo



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Re: [U-Boot] [PATCH v1 0/6] Update gdsys board support

[Dirk Eibach]

Hi Kim,

2014-11-05 11:43 GMT+01:00 Stefan Roese :
> Hi Dirk,
>
> On 05.11.2014 10:45, Dirk Eibach wrote:
>>
>> will you look after this series? I ask because there is also some
>> mpc83xx stuff involved.
>
>
> Yes, I just looked again. Not sure how we should handle this patch series. I
> can ack the PPC4xx and CFI flash related patches and someone else can pull
> this series (Kim for mpc83xx. Or Kim ack's the 83xx patch and I'll pull all
> and push it forward.
>
> Comments?

what way of handling this would you prefer?

Cheers
Dirk
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Re: [U-Boot] [PATCH v1 6/6] mpc83xx: Add gdsys hrcon board

[Dirk Eibach]

Hi Kim,

2014-11-07 1:18 GMT+01:00 Kim Phillips :
> ...
> sorry for the delay, I bricked a board when going through my queue
> lately, and haven't been able to fully recover since.

no problem, Thanks for the review,  I'm very happy we have some progress now.

>>  arch/powerpc/cpu/mpc83xx/Kconfig |   4 +
>>  board/gdsys/405ep/iocon.c| 190 +--
>>  board/gdsys/common/Makefile  |   3 +-
>>  board/gdsys/common/ihs_mdio.c|  88 +
>>  board/gdsys/common/ihs_mdio.h|  18 ++
>>  board/gdsys/common/phy.c | 280 
>>  board/gdsys/common/phy.h |  14 +
>
> is it me, or should PHY support go under drivers/net/phy/gdsys.c (or
> something like that)?  Even if not immediately ported to the Generic
> PHY Management layer, still, I think it would be a good idea to get
> it in the right vicinity.
>
> Taking a closer look, it looks like at least one of the PHYs
> involved here (the Marvell 88E1518) is already implemented in
> drivers/phy/marvell.c to a certain degree, so it might be helpful to
> define CONFIG_PHY_MARVELL as a first step to migrating to the
> generic PHY subsystem.

The first step was to factor out the common PHY code from iocon.c. The
next step is merging this with the PHY subsystem.
For the moment I would prefer it going in this way and doing a merge
with the PHY subsystem for the next release.
There are more boards coming that use this and I will clean it up alltogether.

>>  board/gdsys/mpc8308/Kconfig  |  12 +
>>  board/gdsys/mpc8308/MAINTAINERS  |   6 +
>>  board/gdsys/mpc8308/Makefile |   9 +
>>  board/gdsys/mpc8308/hrcon.c  | 677 
>> +++
>>  board/gdsys/mpc8308/mpc8308.c| 109 +++
>>  board/gdsys/mpc8308/mpc8308.h|  10 +
>>  board/gdsys/mpc8308/sdram.c  |  82 +
>
>>  common/Makefile  |   1 +
>>  common/cmd_ioloop.c  | 295 +
>
> IDK what this is (FPGA io-endpoint looper/reflector?), but I'm
> guessing since it's in common/, it should be separated from this
> board support patch, otherwise it won't get the intended audience's
> attention.

Since this is very gdsys FPGA specific I should probably move it to
our board directory.

>> +int last_stage_init(void)
>> +{
>> + int slaves;
>> + unsigned int k;
>> + unsigned int mux_ch;
>> + unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
>> + u16 fpga_features;
>> + bool hw_type_cat = pca9698_get_value(0x20, 20);
>> + bool ch0_rgmii2_present = false;
>> +
>> + FPGA_GET_REG(0, fpga_features, &fpga_features);
>> +
>> + /* Turn on Parade DP501 */
>> + pca9698_direction_output(0x20, 10, 1);
>> +
>> + ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
>> +
>> + /* wait for FPGA done */
>> + for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
>> + unsigned int ctr = 0;
>> +
>> + if (i2c_probe(mclink_controllers[k]))
>> + continue;
>> +
>> + while (!(pca953x_get_val(mclink_controllers[k])
>> +& MCFPGA_DONE)) {
>> + udelay(10);
>> + if (ctr++ > 5) {
>> + printf("no done for mclink_controller %d\n", 
>> k);
>> + break;
>> + }
>> + }
>> + }
>> +
>> + if (hw_type_cat) {
>> + miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
>> + bb_miiphy_write);
>> + for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
>> + if ((mux_ch == 1) && !ch0_rgmii2_present)
>> + continue;
>> +
>> + setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
>> + }
>> + }
>> +
>> + /* give slave-PLLs and Parade DP501 some time to be up and running */
>> + udelay(50);
>> +
>> + mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
>> + slaves = mclink_probe();
>> + mclink_fpgacount = 0;
>> +
>> + print_fpga_info(0, ch0_rgmii2_present);
>> + osd_probe(0);
>> + return 0;
>
> unless this was left in from debugging (in which case it should be
> removed), it implies the remaining code in the fn..:

Oops, you are absolutely rigth this is debugcode. Wonder how that crept in...

>> +
>> + if (slaves <= 0)
>> + return 0;
>> +
>> + mclink_fpgacount = slaves;
>> +
>> + for (k = 1; k <= slaves; ++k) {
>> + FPGA_GET_REG(k, fpga_features, &fpga_features);
>> +
>> + print_fpga_info(k, false);
>> + osd_probe(k);
>> + if (hw_type_cat) {
>> + miiphy_register(bb_miiphy_buses[k].name,
>> + bb_miiphy_read, bb_miiphy_write);
>> + setup_88e1514(bb_miiphy_buses[k].name, 0);
>> + }
>> + }
>> +
>> + return 0;
>> +}
>
> ..is dead code, and therefore not welcome he

[U-Boot] [PATCH 2/6] arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

[Stefan Roese]

This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI
driver is enabled.

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
---
 arch/arm/cpu/armv7/socfpga/misc.c | 6 ++
 arch/arm/cpu/armv7/socfpga/reset_manager.c| 9 +
 arch/arm/include/asm/arch-socfpga/reset_manager.h | 3 +++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv7/socfpga/misc.c 
b/arch/arm/cpu/armv7/socfpga/misc.c
index 8c3e5f7..73cffd3 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -202,6 +202,12 @@ int arch_early_init_r(void)
 
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
+
+#ifdef CONFIG_DESIGNWARE_SPI
+   /* Get Designware SPI controller out of reset */
+   socfpga_spim_enable();
+#endif
+
return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c 
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 1d3a95d..af9db85 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable)
 #endif
}
 }
+
+/* SPI Master enable (its held in reset by the preloader) */
+void socfpga_spim_enable(void)
+{
+   const void *reset = &reset_manager_base->per_mod_reset;
+
+   clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+   clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h 
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 1857b80..034135b 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable);
 
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
+void socfpga_spim_enable(void);
 
 struct socfpga_reset_manager {
u32 status;
@@ -35,5 +36,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_PERMODRST_EMAC0_LSB 0
 #define RSTMGR_PERMODRST_EMAC1_LSB 1
 #define RSTMGR_PERMODRST_L4WD0_LSB 6
+#define RSTMGR_PERMODRST_SPIM0_LSB 18
+#define RSTMGR_PERMODRST_SPIM1_LSB 19
 
 #endif /* _RESET_MANAGER_H_ */
-- 
2.1.3

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[U-Boot] [PATCH 1/6] arm: socfpga: Add DW master SPI clock to clock_manager.c

[Stefan Roese]

This function will be needed by the upcoming Designware master SPI
driver.

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
---
 arch/arm/cpu/armv7/socfpga/clock_manager.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c 
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index d869f47..fa3b93a 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
return clock;
 }
 
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+   uint32_t reg, clock = 0;
+
+   clock = cm_get_per_vco_clk_hz();
+
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(&clock_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+
+   return clock;
+}
+
 static void cm_print_clock_quick_summary(void)
 {
printf("MPU   %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
@@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void)
printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
printf("QSPI%8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
printf("UART%8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+   printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
 }
 
 int set_cpu_clk_info(void)
-- 
2.1.3

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[U-Boot] [PATCH 4/6] arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices

[Stefan Roese]

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
---
 arch/arm/dts/socfpga.dtsi | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 4a789a9..9de7ca9 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -654,6 +654,34 @@
status = "disabled";
};
 
+   spi0: spi@fff0 {
+   compatible = "snps,dw-spi-mmio";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0xfff0 0x1000>;
+   interrupts = <0 154 4>;
+   num-chipselect = <4>;
+   bus-num = <0>;
+   tx-dma-channel = <&pdma 16>;
+   rx-dma-channel = <&pdma 17>;
+   clocks = <&per_base_clk>;
+   status = "disabled";
+   };
+
+   spi1: spi@fff01000 {
+   compatible = "snps,dw-spi-mmio";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0xfff01000 0x1000>;
+   interrupts = <0 156 4>;
+   num-chipselect = <4>;
+   bus-num = <1>;
+   tx-dma-channel = <&pdma 20>;
+   rx-dma-channel = <&pdma 21>;
+   clocks = <&per_base_clk>;
+   status = "disabled";
+   };
+
/* Local timer */
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";
-- 
2.1.3

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[U-Boot] [PATCH 3/6] spi: Add designware master SPI DM driver used on SoCFPGA

[Stefan Roese]

This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
driver is not possible.

This driver is very loosly based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver. As we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
Cc: Simon Glass 
Cc: Jagannadha Sutradharudu Teki 
---
 drivers/spi/Makefile |   1 +
 drivers/spi/designware_spi.c | 425 +++
 2 files changed, 426 insertions(+)
 create mode 100644 drivers/spi/designware_spi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 964fdc1..edbd520 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o 
cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
new file mode 100644
index 000..1bc0d04
--- /dev/null
+++ b/drivers/spi/designware_spi.c
@@ -0,0 +1,425 @@
+/*
+ * Designware master SPI core controller driver
+ *
+ * Copyright (C) 2014 Stefan Roese 
+ *
+ * Very loosly based on the Linux driver version which is:
+ * Copyright (c) 2009, Intel Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register offsets */
+#define DW_SPI_CTRL0   0x00
+#define DW_SPI_CTRL1   0x04
+#define DW_SPI_SSIENR  0x08
+#define DW_SPI_MWCR0x0c
+#define DW_SPI_SER 0x10
+#define DW_SPI_BAUDR   0x14
+#define DW_SPI_TXFLTR  0x18
+#define DW_SPI_RXFLTR  0x1c
+#define DW_SPI_TXFLR   0x20
+#define DW_SPI_RXFLR   0x24
+#define DW_SPI_SR  0x28
+#define DW_SPI_IMR 0x2c
+#define DW_SPI_ISR 0x30
+#define DW_SPI_RISR0x34
+#define DW_SPI_TXOICR  0x38
+#define DW_SPI_RXOICR  0x3c
+#define DW_SPI_RXUICR  0x40
+#define DW_SPI_MSTICR  0x44
+#define DW_SPI_ICR 0x48
+#define DW_SPI_DMACR   0x4c
+#define DW_SPI_DMATDLR 0x50
+#define DW_SPI_DMARDLR 0x54
+#define DW_SPI_IDR 0x58
+#define DW_SPI_VERSION 0x5c
+#define DW_SPI_DR  0x60
+
+/* Bit fields in CTRLR0 */
+#define SPI_DFS_OFFSET 0
+
+#define SPI_FRF_OFFSET 4
+#define SPI_FRF_SPI0x0
+#define SPI_FRF_SSP0x1
+#define SPI_FRF_MICROWIRE  0x2
+#define SPI_FRF_RESV   0x3
+
+#define SPI_MODE_OFFSET6
+#define SPI_SCPH_OFFSET6
+#define SPI_SCOL_OFFSET7
+
+#define SPI_TMOD_OFFSET8
+#define SPI_TMOD_MASK  (0x3 << SPI_TMOD_OFFSET)
+#defineSPI_TMOD_TR 0x0 /* xmit & recv 
*/
+#define SPI_TMOD_TO0x1 /* xmit only */
+#define SPI_TMOD_RO0x2 /* recv only */
+#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
+
+#define SPI_SLVOE_OFFSET   10
+#define SPI_SRL_OFFSET 11
+#define SPI_CFS_OFFSET 12
+
+/* Bit fields in SR, 7 bits */
+#define SR_MASK0x7f/* cover 7 bits 
*/
+#define SR_BUSY(1 << 0)
+#define SR_TF_NOT_FULL (1 << 1)
+#define SR_TF_EMPT (1 << 2)
+#define SR_RF_NOT_EMPT (1 << 3)
+#define SR_RF_FULL (1 << 4)
+#define SR_TX_ERR  (1 << 5)
+#define SR_DCOL(1 << 6)
+
+#define RX_TIMEOUT 1000
+
+struct dw_spi_platdata {
+   s32 frequency;  /* Default clock frequency, -1 for none */
+   void __iomem *regs;
+};
+
+struct dw_spi_priv {
+   void __iomem *regs;
+   unsigned 

[U-Boot] [PATCH 5/6] arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing

[Stefan Roese]

Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct for the Designware SPI
controllers.

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
---
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts 
b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 02bb8b3..4f0bfab 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -27,6 +27,8 @@
 
aliases {
spi0 = "/spi@ff705000"; /* QSPI */
+   spi1 = "/spi@fff0";
+   spi2 = "/spi@fff01000";
};
 
memory {
-- 
2.1.3

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[U-Boot] [PATCH 0/6] arm: socfpga: Add Designware SPI support

[Stefan Roese]

Hi!

This patchset adds the driver for the Designware master SPI controller.
This IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
driver is not possible.

As mentioned above, this patchset depends on the SoCFPGA DT support. And
its also done on-top of the Cadence QSPI support I posted a short while
ago. But it doesn't depend on it. Its just that the patch series will
most likely generate merge conflicts if not applied in this sequence.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.

Thanks,
Stefan

Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
Cc: Simon Glass 
Cc: Jagannadha Sutradharudu Teki 
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[U-Boot] [PATCH 6/6] arm: socfpga: Add Designware (DW) SPI support to config header

[Stefan Roese]

Enable support for the DW master SPI controller in the config header
for the SoCFPGA. This controller can only be enabled, if DT support
is enabled.

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
---
 include/configs/socfpga_common.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 9fc4212..830b956 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CMD_SF
 #endif
 
+#ifdef CONFIG_OF_CONTROL   /* DW SPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DESIGNWARE_SPI
+#ifndef __ASSEMBLY__
+unsigned int cm_get_spi_controller_clk_hz(void);
+#define CONFIG_DW_SPI_REF_CLK  cm_get_spi_controller_clk_hz()
+#endif
+#define CONFIG_CMD_SPI
+#endif
+
 /*
  * Serial Driver
  */
-- 
2.1.3

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[U-Boot] [PATCH] powerpc: remove orphaned boards mcc200 and prs200

[Nikita Kiryanov]

mcc200 and prs200 are old and have no maintainer. Remove the boards.

This also removes the mcc200 specific 1bpp BMP support from
common/lcd.c

Cc: Wolfgang Denk 
Cc: Anatolij Gustschin 
Cc: Masahiro Yamada 
Signed-off-by: Nikita Kiryanov 
---
 arch/powerpc/cpu/mpc5xxx/Kconfig  |   4 -
 board/mcc200/Kconfig  |   9 -
 board/mcc200/MAINTAINERS  |  17 -
 board/mcc200/Makefile |   8 -
 board/mcc200/auto_update.c| 521 --
 board/mcc200/lcd.c| 200 --
 board/mcc200/mcc200.c | 314 
 board/mcc200/mt46v16m16-75.h  |  16 -
 board/mcc200/mt48lc16m16a2-75.h   |  14 -
 board/mcc200/mt48lc16m32s2-75.h   |  14 -
 board/mcc200/mt48lc8m32b2-6-7.h   |  12 -
 common/lcd.c  |  24 +-
 configs/mcc200_COM12_SDRAM_defconfig  |   4 -
 configs/mcc200_COM12_defconfig|   4 -
 configs/mcc200_COM12_highboot_SDRAM_defconfig |   4 -
 configs/mcc200_COM12_highboot_defconfig   |   4 -
 configs/mcc200_SDRAM_defconfig|   4 -
 configs/mcc200_defconfig  |   3 -
 configs/mcc200_highboot_SDRAM_defconfig   |   4 -
 configs/mcc200_highboot_defconfig |   4 -
 configs/prs200_DDR_defconfig  |   4 -
 configs/prs200_defconfig  |   4 -
 configs/prs200_highboot_DDR_defconfig |   4 -
 configs/prs200_highboot_defconfig |   4 -
 doc/README.scrapyard  |   2 +
 include/configs/mcc200.h  | 397 
 include/lcd.h |   2 +-
 27 files changed, 4 insertions(+), 1597 deletions(-)
 delete mode 100644 board/mcc200/Kconfig
 delete mode 100644 board/mcc200/MAINTAINERS
 delete mode 100644 board/mcc200/Makefile
 delete mode 100644 board/mcc200/auto_update.c
 delete mode 100644 board/mcc200/lcd.c
 delete mode 100644 board/mcc200/mcc200.c
 delete mode 100644 board/mcc200/mt46v16m16-75.h
 delete mode 100644 board/mcc200/mt48lc16m16a2-75.h
 delete mode 100644 board/mcc200/mt48lc16m32s2-75.h
 delete mode 100644 board/mcc200/mt48lc8m32b2-6-7.h
 delete mode 100644 configs/mcc200_COM12_SDRAM_defconfig
 delete mode 100644 configs/mcc200_COM12_defconfig
 delete mode 100644 configs/mcc200_COM12_highboot_SDRAM_defconfig
 delete mode 100644 configs/mcc200_COM12_highboot_defconfig
 delete mode 100644 configs/mcc200_SDRAM_defconfig
 delete mode 100644 configs/mcc200_defconfig
 delete mode 100644 configs/mcc200_highboot_SDRAM_defconfig
 delete mode 100644 configs/mcc200_highboot_defconfig
 delete mode 100644 configs/prs200_DDR_defconfig
 delete mode 100644 configs/prs200_defconfig
 delete mode 100644 configs/prs200_highboot_DDR_defconfig
 delete mode 100644 configs/prs200_highboot_defconfig
 delete mode 100644 include/configs/mcc200.h

diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index c1fb92a..bd64ea6 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -38,9 +38,6 @@ config TARGET_IPEK01
 config TARGET_JUPITER
bool "Support jupiter"
 
-config TARGET_MCC200
-   bool "Support mcc200"
-
 config TARGET_MOTIONPRO
bool "Support motionpro"
 
@@ -130,7 +127,6 @@ source "board/jupiter/Kconfig"
 source "board/manroland/hmi1001/Kconfig"
 source "board/manroland/mucmc52/Kconfig"
 source "board/manroland/uc101/Kconfig"
-source "board/mcc200/Kconfig"
 source "board/motionpro/Kconfig"
 source "board/munices/Kconfig"
 source "board/phytec/pcm030/Kconfig"
diff --git a/board/mcc200/Kconfig b/board/mcc200/Kconfig
deleted file mode 100644
index 3b27eeb..000
--- a/board/mcc200/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MCC200
-
-config SYS_BOARD
-   default "mcc200"
-
-config SYS_CONFIG_NAME
-   default "mcc200"
-
-endif
diff --git a/board/mcc200/MAINTAINERS b/board/mcc200/MAINTAINERS
deleted file mode 100644
index a59a498..000
--- a/board/mcc200/MAINTAINERS
+++ /dev/null
@@ -1,17 +0,0 @@
-MCC200 BOARD
-#M:-
-S: Maintained
-F: board/mcc200/
-F: include/configs/mcc200.h
-F: configs/mcc200_defconfig
-F: configs/mcc200_COM12_defconfig
-F: configs/mcc200_COM12_highboot_defconfig
-F: configs/mcc200_COM12_highboot_SDRAM_defconfig
-F: configs/mcc200_COM12_SDRAM_defconfig
-F: configs/mcc200_highboot_defconfig
-F: configs/mcc200_highboot_SDRAM_defconfig
-F: configs/mcc200_SDRAM_defconfig
-F: configs/prs200_defconfig
-F: configs/prs200_DDR_defconfig
-F: configs/prs200_highboot_defconfig
-F: configs/prs200_highboot_DDR_defconfig
diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
deleted file mode 100644
index db3b396..000
--- a/board/mcc200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX

[U-Boot] [PATCH 1/2] ARM: UniPhier: add set_pinsel macro for use in assembly code

[Masahiro Yamada]

The function sg_set_pinsel is useful for switching I/O pins
but it can be only used in C code.  This commit adds a simple
macro that is available in asm code.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/include/asm/arch-uniphier/sg-regs.h | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h 
b/arch/arm/include/asm/arch-uniphier/sg-regs.h
index 79d7ec7..fa5e6ae 100644
--- a/arch/arm/include/asm/arch-uniphier/sg-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h
@@ -88,7 +88,18 @@
 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ(0x2 << 16)
 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A  (0x3 << 16)
 
-#ifndef __ASSEMBLY__
+#ifdef __ASSEMBLY__
+
+   .macro  set_pinsel, n, value, ra, rd
+   ldr \ra, =SG_PINSEL_ADDR(\n)
+   ldr \rd, [\ra]
+   and \rd, \rd, #SG_PINSEL_MASK(\n)
+   orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
+   str \rd, [\ra]
+   .endm
+
+#else
+
 #include 
 #include 
 
-- 
1.9.1

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[U-Boot] [PATCH 0/2] Utilize low-level debug for UniPhier platform

[Masahiro Yamada]

Masahiro Yamada (2):
  ARM: UniPhier: add set_pinsel macro for use in assembly code
  ARM: UniPhier: add UART initialization routine for low-level debug

 arch/arm/cpu/armv7/uniphier/lowlevel_init.S|  4 +++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile   |  1 +
 .../cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S| 29 
 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile  |  1 +
 .../cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S   | 39 ++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile  |  1 +
 .../cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S   | 29 
 arch/arm/include/asm/arch-uniphier/debug-uart.S| 24 +
 arch/arm/include/asm/arch-uniphier/sg-regs.h   | 13 +++-
 9 files changed, 140 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S
 create mode 100644 arch/arm/include/asm/arch-uniphier/debug-uart.S

-- 
1.9.1

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[U-Boot] [PATCH 2/2] ARM: UniPhier: add UART initialization routine for low-level debug

[Masahiro Yamada]

The low-level debugging functions are very useful to debug the early
boot stage where the full UART driver is not available.

UniPhier SoCs need to initialize the UART port 0 to use this feature.
The initialization routine is called the very entry of the
lowlevel_init().

Signed-off-by: Masahiro Yamada 
---

 arch/arm/cpu/armv7/uniphier/lowlevel_init.S|  4 +++
 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile   |  1 +
 .../cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S| 29 
 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile  |  1 +
 .../cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S   | 39 ++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile  |  1 +
 .../cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S   | 29 
 arch/arm/include/asm/arch-uniphier/debug-uart.S| 24 +
 8 files changed, 128 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S
 create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S
 create mode 100644 arch/arm/include/asm/arch-uniphier/debug-uart.S

diff --git a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S 
b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
index 0ea12d3..c208ab6 100644
--- a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
@@ -26,6 +26,10 @@ ENTRY(lowlevel_init)
orr r0, r0, #(CR_C | CR_M)  @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
 
+#ifdef CONFIG_DEBUG_LL
+   bl  setup_lowlevel_debug
+#endif
+
/*
 * Now we are using the page table embedded in the Boot ROM.
 * It is not handy since it is not a straight mapped table for sLD3.
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile 
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index 781b511..040f49d 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-y += platdevice.o
 obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
 obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S 
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S
new file mode 100644
index 000..c0778a0
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S
@@ -0,0 +1,29 @@
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#define UART_CLK   36864000
+#include 
+
+ENTRY(setup_lowlevel_debug)
+   init_debug_uart r0, r1, r2
+
+   /* UART Port 0 */
+   set_pinsel  85, 1, r0, r1
+   set_pinsel  88, 1, r0, r1
+
+   ldr r0, =SG_IECTRL
+   ldr r1, [r0]
+   orr r1, r1, #1
+   str r1, [r0]
+
+   mov pc, lr
+ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile 
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index e11f4f6..6f657c0 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-y += platdevice.o
 obj-y += boot-mode.o
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
sg_init.o pll_init.o clkrst_init.o pinctrl.o
 obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S 
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S
new file mode 100644
index 000..a793b7c
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S
@@ -0,0 +1,39 @@
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+#define UART_CLK   73728000
+#include 
+
+ENTRY(setup_lowlevel_debug)
+   ldr r0, =SC_CLKCTRL
+   ldr r1, [r0]
+   orr r1, r1, #SC_CLKCTRL_CLK_PERI
+   str r1, [r0]
+
+   init_debug_uart r0, r1, r2
+
+   /* UART Port 0 */
+   set_pinsel  127, 0, r0, r1
+   set_pinsel  128, 0, r0, r1
+
+   ldr r0, =SG_LOADPINCTRL
+   mov r1, #1
+   str r1, [r0]
+
+ 

Re: [U-Boot] [PATCH v3 3/3] imx:mx6slevk add board level support for usb

[Peng Fan]

在 11/7/2014 7:10 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:08:03 PM, Peng Fan wrote:

在 11/7/2014 4:26 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 02:08:14 AM, Peng Fan wrote:

Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return 0 to let
ehci-mx6.c driver decide otg2 core to works in host mode.

Signed-off-by: Peng Fan 
Signed-off-by: Ye Li 
---


[...]


@@ -150,6 +151,63 @@ static int setup_fec(void)

   }
   #endif

+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define USBPHY_CTRL0x30
+#define UCTRL_PWR_POL  (1 << 9)
+#define USBPHY_CTRL_OTG_ID 0x0800


This looks like an duplication. Aren't those bits defined somewhere in
generic code already ?


If this way 'int board_usb_phy_mode(int port, enum usb_init_type *type)'
can be accpeted, these bits are not needed and I'll move these bits in
the seperate PHY register struct access patch. Anyway, after the board
level usb support patch.


What about abstracting that stuff into a function which returns the PHY's
idea of the current mode instead. That way, you can determine the PHY's
idea of the mode from both board code and the driver code.

struct phy register is good, but I prefer not to include this in board 
level code, see my reply in this patch "usb:ehci-mx6 add 
board_usb_phy_mode function" just as "board_ehci_power" and 
"board_ehci_hcd_init" do. I think it is good to make it a seperate patch.

Best regards,
Marek Vasut


Regards,
Peng.
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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

[Peng Fan]

在 11/7/2014 7:09 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:

[...]


@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct usb_ehci
*ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);

__raw_writel(val, phy_ctrl);

-   return val & USBPHY_CTRL_OTG_ID;
+   return board_usb_phy_mode(index);


This should be called from ehci_hcd_init() right after usb_phy_enable().
Afterall, the mode detection has nothing to do with the PHY enabling.


This back to what I did in patch v2. right after usb_phy_enable(), just
paste that piece of code here:

The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+

  type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;

+   board_usb_phy_mode(index, &type);
+


The usb_phy_enable() should not return the PHY mode at all though.
It should be the board_usb_phy_mode() which adjusts the PHY type.
The usb_phy_enable() should return just a success/failure return
value.


ok. got it.

What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+   if (port == 1)
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent
this patch set.


It should really explicitly set it, not modify it, see above.


I have an idea about this patch:
1. usb_phy_enable will not be touched.
2. replace "type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : 
USB_INIT_HOST;" with "usb_phy_enable(index, ehci)".
3. right after usb_phy_enable, add this line "type = 
board_usb_phy_mode(index)" or "type = board_usb_phy_mode((struct usb_phy 
*)PHY_ADDRESS)". Here I also think pass phy register definition to board 
level code is not fine just as what we talked about passing ehci struct 
to board level code in patch v2.
4. in ehci-mx6.c, implement the weak function "int __weak 
board_usb_phy_mode(xxx)", and it's return value is the mode, HOST or 
DEVICE. If the board code want to implement this function, just return 
what the board want.


After all, this patch may looks like this:
In ehci-mx6.c
+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val & USBPHY_CTRL_OTG_ID;
+}
+

- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);

in board code, which is not in this patch, just list here:
+int board_usb_phy_mode(int port)
+{
+   if (port == 1)
+   return USB_INIT_HOST;
+   else
+   return USB_INIT_DEVICE;
+}
I just want to keep it simple and do not want to touch usb phy register 
in board code.


Any ideas?

[...]


Regards,
Peng.
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[U-Boot] [PATCH 4/4 v4] arm: socfpga: Add Cadence QSPI support to config header

[Stefan Roese]

With this driver enabled for SoCFPGA, access to SPI NOR flash is
supported.

The configuration (page size, timing info) will be taken from the
DT. See socrates as an example.

This QSPI supports depends on DT. So QSPI is only enabled if
CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig).

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
Cc: Simon Glass 
Cc: Jagannadha Sutradharudu Teki 
---
v4:
- Some config parameters (page-size and timing are now removed
  and will be read from the DT instead)

 include/configs/socfpga_common.h | 25 -
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f7b314d..9fc4212 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -141,7 +141,7 @@
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256 /* FIXME -- SPL only? */
 #endif
 
- /*
+/*
  * I2C support
  */
 #define CONFIG_SYS_I2C
@@ -169,6 +169,29 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 #define CONFIG_CMD_I2C
 
 /*
+ * QSPI support
+ */
+#ifdef CONFIG_OF_CONTROL   /* QSPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_CADENCE_QSPI
+/* Enable multiple SPI NOR flash manufacturers */
+#define CONFIG_SPI_FLASH   /* SPI flash subsystem */
+#define CONFIG_SPI_FLASH_STMICRO   /* Micron/Numonyx flash */
+#define CONFIG_SPI_FLASH_SPANSION  /* Spansion flash */
+#define CONFIG_SPI_FLASH_MTD
+/* QSPI reference clock */
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK   cm_get_qspi_controller_clk_hz()
+#endif
+#define CONFIG_CQSPI_DECODER   0
+#define CONFIG_CMD_SF
+#endif
+
+/*
  * Serial Driver
  */
 #define CONFIG_SYS_NS16550
-- 
2.1.3

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[U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi

[Stefan Roese]

This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
Cc: Simon Glass 
Cc: Jagannadha Sutradharudu Teki 
---
 arch/arm/dts/socfpga.dtsi  | 15 +++
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 20 
 2 files changed, 35 insertions(+)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 4472fd9..4a789a9 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -639,6 +639,21 @@
clock-names = "biu", "ciu";
};
 
+   qspi: spi@ff705000 {
+   compatible = "cadence,qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0xff705000 0x1000>,
+   <0xffa0 0x1000>;
+   interrupts = <0 151 4>;
+   clocks = <&qspi_clk>;
+   ext-decoder = <0>;  /* external decoder */
+   num-chipselect = <4>;
+   fifo-depth = <128>;
+   bus-num = <2>;
+   status = "disabled";
+   };
+
/* Local timer */
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts 
b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index a1814b4..9277174 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -48,3 +48,23 @@
 &mmc {
status = "okay";
 };
+
+&qspi {
+   status = "okay";
+
+   flash0: n25q00@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "n25q00";
+   reg = <0>;  /* chip select */
+   spi-max-frequency = <5000>;
+   m25p,fast-read;
+   page-size = <256>;
+   block-size = <16>; /* 2^16, 64KB */
+   read-delay = <4>;  /* delay value in read data capture register 
*/
+   tshsl-ns = <50>;
+   tsd2d-ns = <50>;
+   tchsh-ns = <4>;
+   tslch-ns = <4>;
+   };
+};
-- 
2.1.3

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[U-Boot] [PATCH 3/4 v4] arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver

[Stefan Roese]

Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct.

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
Cc: Simon Glass 
Cc: Jagannadha Sutradharudu Teki 
---
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts 
b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 9277174..02bb8b3 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -25,6 +25,10 @@
bootargs = "console=ttyS0,115200";
};
 
+   aliases {
+   spi0 = "/spi@ff705000"; /* QSPI */
+   };
+
memory {
name = "memory";
device_type = "memory";
-- 
2.1.3

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[U-Boot] [PATCH 0/4 v4] arm: socfpga: Add Cadence QSPI support

[Stefan Roese]

Hi!

So this is my 4th posting regarding the Candence SPI driver on SoCFPGA.

Again, SPI NOR flash is working. At least on SoCrates and on another
custom SoCFPGA based board. The main change in this version is, that
the Cadence driver now is a driver model (DM) based driver. And this
needs the DT support which I posted just before.

One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.

Note that I have patches to support the Designware SPI master
controller also via DM in the queue. I'll post them shortly.

Thanks,
Stefan

Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
Cc: Simon Glass 
Cc: Jagannadha Sutradharudu Teki 
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[U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA

[Stefan Roese]

This driver is cloned from the Altera Rockerboard.org U-Boot
repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
modification to support the U-Boot driver model (DM).

As mentioned above, in this new version I ported this driver to the
new driver model (DM). One big advantage of this move is that now
multiple SPI drivers can be enabled on one platform. And since the
SoCFPGA also has the Designware SPI master controller integrated,
this feature is really needed to support both controllers.

Because of this, this series needs the DT support for SoCFPGA
to be applied. For DT based probing in the SPI DM.

Signed-off-by: Stefan Roese 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Vince Bridgers 
Cc: Marek Vasut 
Cc: Pavel Machek 
Cc: Simon Glass 
Cc: Jagannadha Sutradharudu Teki 
---
v4:
- Reworked to support driver model (DM)
- Coding-style changes to make it checkpatch clean

v3:
- Added SPDX License Indentifier
- Removed CQSPI_WRITEL / CQSPI_READL

 drivers/spi/Makefile   |   1 +
 drivers/spi/cadence_qspi.c | 345 
 drivers/spi/cadence_qspi.h |  76 
 drivers/spi/cadence_qspi_apb.c | 898 +
 4 files changed, 1320 insertions(+)
 create mode 100644 drivers/spi/cadence_qspi.c
 create mode 100644 drivers/spi/cadence_qspi.h
 create mode 100644 drivers/spi/cadence_qspi_apb.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index eabbf27..964fdc1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
 obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
new file mode 100644
index 000..fa95b19
--- /dev/null
+++ b/drivers/spi/cadence_qspi.c
@@ -0,0 +1,345 @@
+/*
+ * Copyright (C) 2012
+ * Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "cadence_qspi.h"
+
+#define CQSPI_STIG_READ0
+#define CQSPI_STIG_WRITE   1
+#define CQSPI_INDIRECT_READ2
+#define CQSPI_INDIRECT_WRITE   3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int cadence_spi_write_speed(struct udevice *bus, uint hz)
+{
+   struct cadence_spi_platdata *plat = bus->platdata;
+   struct cadence_spi_priv *priv = dev_get_priv(bus);
+
+   cadence_qspi_apb_config_baudrate_div(priv->regbase,
+CONFIG_CQSPI_REF_CLK, hz);
+
+   /* Reconfigure delay timing if speed is changed. */
+   cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
+  plat->tshsl_ns, plat->tsd2d_ns,
+  plat->tchsh_ns, plat->tslch_ns);
+
+   return 0;
+}
+
+/* Calibration sequence to determine the read data capture delay register */
+static int spi_calibration(struct udevice *bus)
+{
+   struct cadence_spi_platdata *plat = bus->platdata;
+   struct cadence_spi_priv *priv = dev_get_priv(bus);
+   void *base = priv->regbase;
+   u8 opcode_rdid = 0x9F;
+   unsigned int idcode = 0, temp = 0;
+   int err = 0, i, range_lo = -1, range_hi = -1;
+
+   /* start with slowest clock (1 MHz) */
+   cadence_spi_write_speed(bus, 100);
+
+   /* configure the read data capture delay register to 0 */
+   cadence_qspi_apb_readdata_capture(base, 1, 0);
+
+   /* Enable QSPI */
+   cadence_qspi_apb_controller_enable(base);
+
+   /* read the ID which will be our golden value */
+   err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+   3, (u8 *)&idcode);
+   if (err) {
+   puts("SF: Calibration failed (read)\n");
+   return err;
+   }
+
+   /* use back the intended clock and find low range */
+   cadence_spi_write_speed(bus, plat->max_hz);
+   for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
+   /* Disable QSPI */
+   cadence_qspi_apb_controller_disable(base);
+
+   /* reconfigure the read data capture delay register */
+   cadence_qspi_apb_readdata_capture(base, 1, i);
+
+   /* Enable back QSPI */
+   cadence_qspi_apb_controller_enable(base);
+
+   /* issue a RDID to get the ID value */
+   err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+   3, (u8 *)&temp);
+   if (err) {
+   puts("SF: Calibration failed (read)\n");
+   return err;
+   }
+
+   /* search for range lo */
+   if (range_lo == -1 && temp == idcode) {
+