On Thu, Nov 06, 2014 at 02:03:01PM +0100, Wolfgang Denk wrote:
This file got corrupted by the automatic editin of commit 1a45966 Add
GPL-2.0+ SPDX-License-Identifier to source files; restore the
opiginal content and manually insert the SPDX ID.
The bug was detected by running cppcheck,
On Thu, Nov 06, 2014 at 02:03:04PM +0100, Wolfgang Denk wrote:
cppcheck reports:
[arch/arm/cpu/arm926ejs/mxs/timer.c:96]: (error) Uninitialized
variable: now
Signed-off-by: Wolfgang Denk w...@denx.de
Cc: Marek Vasut ma...@denx.de
Cc: Stefano Babic sba...@denx.de
Applied to
On Fri, Nov 07, 2014 at 03:32:07AM +0900, Masahiro Yamada wrote:
Commit 0f605c1501f6 (Start the deprecation process for generic board)
added a run-time warning message. Let's be noisier for non-generic
boards to inform the dead line of the conversion.
This commit intentionally outputs a
On Thu, Nov 06, 2014 at 02:03:02PM +0100, Wolfgang Denk wrote:
Fix error detected by cppcheck:
[board/matrix_vision/mvblx/sys_eeprom.c:353]: (error) Buffer is
accessed out of bounds.
Signed-off-by: Wolfgang Denk w...@denx.de
cc: Michael Jones michael.jo...@matrix-vision.de
Acked-by:
On Sat, Nov 08, 2014 at 01:07:56AM +0100, Albert ARIBAUD wrote:
Hello Tom,
The following changes since commit 5b3ee386fde82a1ba42ff09b95247842c9a1585e:
kbuild: clear VENDOR variable to fix build error on tcsh (2014-10-23
16:35:12 -0400)
are available in the git repository at:
On Mon, Nov 10, 2014 at 12:42:46PM +0800, Sonic Zhang wrote:
Hi Tom,
Please pull the following patches for Blackfin from u-boot-blackfin
into your tree.
Thanks
Sonic Zhang
The following changes since commit 11ada9225a16ed2d8ddbf0715a2416245a777cbc:
Merge branch 'rmobile' of
On Fri, Nov 07, 2014 at 10:08:35AM +0900, Jorgen Lundman wrote:
In a message from Wolfgang Denk highlighting warnings from cppcheck,
the patch will address those that are correctly diagnosed. Some are
false-positives:
[fs/zfs/zfs.c:937]: (error) Memory leak: l
dmu_read() allocates l if
On Thu, Aug 28, 2014 at 11:17:17AM +, Dominik Muth wrote:
From 4877c78a6b11ebf90fe25376f1362b12d233797a Mon Sep 17 00:00:00 2001
From: Dominik Muth dominik.m...@bkvibro.com
Date: Thu, 28 Aug 2014 12:25:27 +0200
Subject: [PATCH] Added support for comments in input to mkenvimage.
This
On Tue, Oct 21, 2014 at 10:31:26PM +0200, Anatolij Gustschin wrote:
Signed-off-by: Anatolij Gustschin ag...@denx.de
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
On Wed, Nov 05, 2014 at 04:33:24PM -0500, Tom Rini wrote:
Hi me,
The following changes since commit d5325eff10922acb11c39efece6d5f24de5b1998:
Merge git://www.denx.de/git/u-boot-sunxi (2014-11-05 07:23:32 -0500)
are available in the git repository at:
On Mon, Nov 10, 2014 at 08:41:00AM +0100, Heiko Schocher wrote:
Hello Tom,
please pull from u-boot-i2c.git
The following changes since commit 11ada9225a16ed2d8ddbf0715a2416245a777cbc:
Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh (2014-11-05
13:11:18 -0500)
are
On Sat, Oct 11, 2014 at 06:42:58PM +0200, Marek Vasut wrote:
Make sure to keep the MAC address programmed in the SMC911x ADDRH
and ADDRL registers. Linux can read those registers to determine
the MAC address on EEPROM-less configurations.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Joe
On Tue, Sep 09, 2014 at 03:16:10PM +0200, Pavel Machek wrote:
Sort drivers/mmc makefile, as requested by wd.
Signed-off-by: Pavel Machek pa...@denx.de
Acked-by: Chin Liang See cl...@altera.com
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 464cee1..461d7d8 100644
On Mon, Nov 10, 2014 at 02:02:44PM -0600, Felipe Balbi wrote:
BeagleBoard-X15 is the next generation Open Source
Hardware BeagleBoard based on TI's AM5728 SoC
featuring dual core 1.5GHZ A15 processor. The
platform features 2GB DDR3L (w/dual 32bit busses),
eSATA, 3 USB3.0 ports, integrated
Hey all,
I've pushed v2015.01-rc1 out to the repository and tarballs should exist
soon.
The merge window is now closed. Per both the min-summit and the follow
up emails, I'm going to try and get into the every 2 week RC tagging
groove. And, I'm going to be relying on everyones best judgement
+Albert
Hi Tom,
On 16 September 2014 18:47, Tom Rini tr...@ti.com wrote:
On Tue, Sep 16, 2014 at 08:27:23PM -0400, Tom Rini wrote:
At the high level, the problem is that we set gd multiple times (and
still do, even after the commit we're reverting). We set important
parts of gd to the
So I am having another issue probably more related to computer science
fundamentals.
I have a global variable boot_dev defined in my board file like so...
I define boot_device in arch/arm/include/asm/arch-mx5/sys_proto.h like this…
Now, boot_dev returns the correct value in checkboard(), but
Hi!
Is there a way i can set my bootarg variable form the command line while
building u-boot?
We have implemented a two-stage u-boot process for our products. The main
idea is that we should be able to see which u-boot version (a software
partnumber) we are running from the kernel /proc/cmdline.
Now that driver model operations prior to relocation, the remaining
area where it does not work is SPL. This series enables this.
Since SPL is quite memory-constrained, code and data size need to be
kept as small as possible. This series includes a few changes to help
with this:
- Small and
Since we currently don't have device tree available in SPL, add platform
data so the uart works.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/serial/serial_tegra.c | 16
1 file changed, 16 insertions(+)
diff --git
This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
arch/arm/lib/spl.c
When enabled, set up driver model for SPL. This allows SPL to use the same
drivers as the main U-Boot.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Tom Rini tr...@ti.com
---
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 5 +
scripts/Makefile.spl | 1 +
2 files
For SPL it is sometimes useful to have a simple malloc() just to permit
driver model to work, in the cases where the full malloc() is not made
available by the board config.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
arch/arm/lib/crt0.S | 2 +-
1
For SPL we don't expect to need to remove a device. Save some code space
by dropping this feature. The board config can define
CONFIG_DM_DEVICE_REMOVE if this is in fact needed.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/core/Makefile
The simple malloc() implementation is used when memory is tight. It provides
a simple buffer with an incrementing pointer.
At present the implementation is inside dlmalloc. Move it into its own file
so that it is easier to find.
Rather than using relocation as a signal that the full malloc() is
Add platform data for the GPIO driver. It doesn't need to contain anything
since the GPIO driver will actually use information from the CONFIGs for
now. This merely serves to ensure that the GPIO driver is bound.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
Set up the simple malloc() implementation when requested, in preference to
the full malloc().
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git
Provide a CONFIG_DM_STDIO option to enable registering a serial device
with the stdio library. This is seldom useful in SPL, so disable it by
default when building for SPL.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Tom Rini tr...@ti.com
---
Changes in v3:
- Add #ifdef around
Since this function can use up quite a bit of space for its strings, disable
it by default in SPL. Use CONFIG_DM_WARN to re-enable it.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Tom Rini tr...@ti.com
---
Changes in v3: None
Changes in v2: None
include/config_defaults.h | 1 +
The faster functions are not actually available in SPL and the code size
likely isn't worth it. Use the normal memcpy() in SPL.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Add new patch to avoid using arch-specific memcpy() in SPL
Changes in v2: None
Hi Bin,
On 9 November 2014 19:50, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.
Signed-off-by:
Hi Bin,
On 9 November 2014 19:54, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.
Signed-off-by: Simon Glass
Use the full driver model GPIO and serial drivers in SPL now that these are
supported. Since device tree is not available they will use platform data.
Remove the special SPL GPIO function as it is no longer needed.
This is all in one commit to maintain bisectability.
Signed-off-by: Simon Glass
The linker lists feature is useful in SPL as it holds the driver model
platform data. So don't throw away the lists.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Tom Rini tr...@ti.com
---
Changes in v3: None
Changes in v2: None
arch/arm/cpu/u-boot-spl.lds | 7 +++
1 file
Add documentation for the various driver model options that are now
available.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Rebase to master
Changes in v2:
- Rebase to master
README | 119
Hi Bin,
On 9 November 2014 20:02, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.
(The license needs to be
Hi Bin,
On 9 November 2014 23:36, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
Hi Bin,
On 9 November 2014 23:49, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree.
Hi Wolfgang,
On 6 November 2014 04:58, Wolfgang Denk w...@denx.de wrote:
Dear Simon,
cppcheck reports:
[arch/sandbox/cpu/start.c:132]: (error) Uninitialized variable: err
And also:
[arch/sandbox/cpu/os.c:371]: (error) Memory leak: fname
Could you please have a look?
Yes will take a
Enable PCI so we can access devices that need to be set up before relocation.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c | 6
arch/x86/cpu/ivybridge/pci.c | 63
At present U-Boot's x86 support requires Coreboot to run first, starting
up the CPU and then setting up SDRAM and video among other tasks. U-Boot
then runs as a payload. Notably U-Boot does not handle the ACPI fun on
x86 where the kernel can call back into the 'BIOS' to perform certain tasks.
For board IDs a common approach is to set aside several GPIOs for use in
determining the board ID. This can provide information about board features
and the revision.
Add a function that turns a list of GPIOs into an integer by assigning
each GPIO to a single bit.
Signed-off-by: Simon Glass
Sometimes an array can be of variable size up to a maximum. Add a helper
function to decode this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
include/fdtdec.h | 16
lib/fdtdec.c | 20
2 files changed, 36 insertions(+)
diff
These are no-longer needed so drop them.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove definition of find_fdt() also
- Remove prepare_fdt() also
arch/x86/include/asm/init_helpers.h | 2 --
arch/x86/lib/init_helpers.c | 27 ---
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.
Newer Intel chips require a Management Engine which requires a particular
format for the SPI flash that contains the boot loader. Add a tool that
supports creating and modifying these ROM images.
This tool is from Chrome OS but has been cleaned up to use U-Boot style
and to add comments. A few
Add a function to get the stack pointer and another to halt the CPU.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove the cpuid functions since they were already added in another patch
arch/x86/include/asm/processor.h | 19 +++
1 file changed, 19
It is convenient to be able to adjust MSRs with a structure that splits the
two 32-bit halves into separate fields, as they are often dealt with
separately. Add a few functions to support this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/include/asm/msr.h | 19
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI
These are available on other architectures. Make them available on x86 also.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/include/asm/io.h | 49 +++
1 file changed, 49 insertions(+)
diff --git
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Split out new patch to support use fo PCI before relocation
arch/x86/cpu/pci.c | 20
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.
In this implementation, board files
We can use an MSR to obtain the time base. Add this back in and consolidate
the code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to tidy up timer code for Intel core architecture
arch/x86/cpu/interrupts.c | 28
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/coreboot/coreboot.c | 4 ++--
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Expand the comment about preserving ebp
- Move SIPI
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.
Note: SPDX submission has been done. If this license is approved I will
convert the files to use SPDX.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Change commit
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c | 141
In general we can't store things in the data section until we have inited
SDRAM. Some platforms allow this (e.g. those with SPL) but some don't. Move
the pointer to global_data so that it will work on all platforms.
Without this fix the serial port will not work prior to relocation with
driver
Many of the x86 CONFIG options will be common across different boards. Move
them to a common file.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Move some features out of the common file
include/configs/coreboot.h | 265 ++-
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Fix mangled cros_ec reg property
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be
Enable GPIO support and provide the required GPIO setup information to
the driver.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/dts/link.dts | 3 +
board/google/chromebook_link/link.c | 107
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 16
1 file changed, 16 insertions(+)
diff --git
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c| 5 +
Set up the flex ratio (controls speed versus heat output) and a few other
very early things.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 130 ++
arch/x86/include/asm/arch-ivybridge/model_206ax.h |
This function can probably be used on all x86 boards, so move it into the
common file.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/coreboot/coreboot.c | 24
arch/x86/cpu/cpu.c | 24
2 files
Rename this vendor since it is intended to be used on any platform where
coreboot runs at reset and then loads U-Boot.
So far it is only tested on link. When other boards are supported it is
likely that we will need to move to multiple board names, all under the
'coreboot' vendor. So while it
For some CPUs, having malloc() available very early is useful. There is no
reason to delay this since early malloc is allocated before board_init_f()
is called.
Move early malloc() init nearer to the start of the init sequence.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.
SDRAM init works by setting
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to replace fill_processor_name() with cpu_get_name()
arch/x86/cpu/cpu.c | 22
The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 3 ++
Here is a patch to apply the same fix on OMAP4 boards as on OMAP3, in
order to prevent ns16550 hanging during SPL boot,
Grégoire
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8f05191..a1d3781 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@
The commands fatls/ext4ls give negative values when dealing with files
greater than 2GB.
The commands fatsize/ext4size do not update the variable filesize for
these files.
To deal with this, the fs functions have been modified to take an additional
parameter of type * loff_t which is then
Deep sleep for generic board is supported now,
and it use CONFIG_FSL_DEEP_SLEEP instead of CONFIG_DEEP_SLEEP,
so modify it for qe.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git
Dear Nikita,
In message 5460e6d9.10...@compulab.co.il you wrote:
TOP5200 powerpc mpc5200- -
Reinhard Meyer reinhard.me...@emk-elektronik.de
TOP860powerpc mpc860 - -
Reinhard Meyer
Deep sleep for generic board is supported now,
and it use CONFIG_FSL_DEEP_SLEEP instead of CONFIG_DEEP_SLEEP,
so modify it for qe.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff
101 - 178 of 178 matches
Mail list logo
