On Wednesday, April 15, 2015 at 10:49:11 PM, Dinh Nguyen wrote:
On 04/02/2015 08:54 PM, Marek Vasut wrote:
On Tuesday, March 31, 2015 at 12:01:16 AM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
This sets the CPU clocks to 925MHz and DDR to
On Wednesday, April 15, 2015 at 11:14:50 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Hello,
The following 2 patches adds the DDR controller driver that is in the
Altera SoCFPGA platform. This driver is needed for the SPL on the
platform.
On Wednesday, April 15, 2015 at 11:44:30 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Hello,
The following 3 patches are updates to SPL patches that Marek has already
applied to his tree. I have split out the DDR driver patches into a
On 2015-04-15 12:54, Sanchayan Maity wrote:
This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.
- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
- for VF50, use PLL2 as memory clock (synchronous mode)
- for VF61, use PLL1 as memory clock (asynchronous mode)
-
Hello Vitaly,
On Thu, 5 Feb 2015 11:24:46 -0500, Vitaly Andrianov vita...@ti.com
wrote:
This commit copies implementation of the find_next_zero_bit() from
git://git.denx.de/u-boot.git/arch/mips/include/asm/bitops.h. v2014.07
The function is required to enable MCAST_TFTP support for ARM
On Thursday, April 16, 2015 at 11:41:30 AM, Michal Simek wrote:
Hi,
On 04/16/2015 11:31 AM, Marek Vasut wrote:
On Thursday, April 16, 2015 at 10:38:34 AM, Michal Simek wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Dont perform reset at the end of thor download
Hello Tom,
On Tue, 3 Feb 2015 15:21:53 -0500, Tom Rini tr...@ti.com wrote:
- Move the obj- lines for memset.S/memcpy.S to outside of an SPL check
so that SPL can use them as well.
- Make sure memset() / memcpy() end up in a text.fn section for garbage
collection in SPL.
- Update
Hello,
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
breaks beagle_x15 build:
Building current source for 1 boards (1 thread, 8 jobs per thread)
arm: + beagle_x15
+board/ti/beagle_x15/board.c: In function 'board_usb_init':
Hi,
On 04/16/2015 11:31 AM, Marek Vasut wrote:
On Thursday, April 16, 2015 at 10:38:34 AM, Michal Simek wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Dont perform reset at the end of thor download
if configured to do reset off.
Reset may not be required in all cases
Hi,
On 15-04-15 21:57, Ian Campbell wrote:
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
For unknown reasons the A33 needs the end of the memory we report to the
kernel to be aligned to a multiple of 4 MiB.
Do you really mean the A33 needs (as in the processor itself) or do
you
Hello Tom,
On Mon, 13 Apr 2015 13:20:47 -0400, Tom Rini tr...@ti.com wrote:
Hey all,
I've pushed v2015.04 out to the repository and tarballs should exist
soon.
The Kconfig migration is moving along nicely as is the DM work. This
has been a good all-around nice set of updates, bug fixes
On Thu, 2015-04-16 at 09:27 +0200, Hans de Goede wrote:
Hi,
On 15-04-15 21:56, Ian Campbell wrote:
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
From: Vishnu Patekar vishnupatekar0...@gmail.com
Based on Allwinner dram init code from the a33 bsp:
Hello Masahiro,
Your patch clashes with Pavel's already committed
break-if-private-libgcc-and-thumb, causing many boards to fail building.
I am putting your patch in 'under review' state until I can have a look
at what happens with private libgcc and thumb.
Amicalement,
--
Albert.
Hi,
On 15-04-15 21:47, Ian Campbell wrote:
On Wed, 2015-04-15 at 10:45 +0200, Michal Suchanek wrote:
It is not obvious which MACH_SUN?I are ARCH_SUN6I derived. So if you
can come up with a descriptive name for 'a number of things in common,
such as having separate ahb reset registers in the
Hi Fabio,
On 15/04/2015 22:57, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add the initial SPL support for HummingBoard-i2eX, which is based on a
MX6 Dual.
For more information about HummingBoard, please check:
http://www.solid-run.com/products/hummingboard/
Hi Tim,
I have no problem with the whole series, I will start to apply. Just a
couple of questions:
On 08/04/2015 21:54, Tim Harvey wrote:
Certain older kernels in use by some customers erroneously define a uart3
for GW54xx with a pinmux that conflicts with NAND. This will remove
that node to
Hi,
On 15-04-15 21:49, Ian Campbell wrote:
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
This is a preparation patch for adding A33 support, which will have a mach
name of sun8i-a33.
And, presumably, differs substantially from sun8i-a23, to the extent it
should likely have been a
Hi,
On 15-04-15 22:00, Ian Campbell wrote:
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
From: Vishnu Patekar vishnupatekar0...@gmail.com
A quick comment on what basic here means, i.e. prcm, rsb, clocks as
per sun6i, etc would be good.
Actually the Basic is misleading here, since
Hello Simon,
On 16-04-15 03:14, Simon Glass wrote:
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong board_init_f_mem(ulong top)
+{
+ /* TODO(s...@chromium.org): Figure out how x86 can use this */
+#ifndef CONFIG_X86
+ /* Leave space for the stack we are running with now */
+ top -= 0x40;
On Thursday, April 16, 2015 at 10:38:34 AM, Michal Simek wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Dont perform reset at the end of thor download
if configured to do reset off.
Reset may not be required in all cases and hence
provided an option to do so.
The
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Dont perform reset at the end of thor download
if configured to do reset off.
Reset may not be required in all cases and hence
provided an option to do so.
The case would be to download the images to DDR instead
of flash device.
Hi,
On 15-04-15 21:56, Ian Campbell wrote:
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
From: Vishnu Patekar vishnupatekar0...@gmail.com
Based on Allwinner dram init code from the a33 bsp:
Hello feng...@phytium.com.cn,
On Mon, 2 Mar 2015 15:29:34 +0800, feng...@phytium.com.cn
feng...@phytium.com.cn wrote:
From: David Feng feng...@phytium.com.cn
Linux-arm64 require that CNTVOFF_EL2 should be programmed with
a consistent value on all cpus. Initializing CNTVOFF_EL2 at state
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Fix wrong timer calculation in get_timer_masked incase of
overflow.
This fixes the issue of getting wrong time from get_timer()
calls.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek
Hi Fabio,
On 04/16/2015 04:27 AM, Fabio Estevam wrote:
Hi Nikolay,
On Wed, Apr 15, 2015 at 10:24 PM, Nikolay Dimitrov picmas...@mail.bg wrote:
imx6 supports up to 528 MHz DDR3 clock as per datasheet, which makes
1058 MT/s data rate. Unfortunately such comments (like above) in the
code
On Thu, Apr 16, 2015 at 06:17:59AM +0100, Siva Durga Prasad Paladugu wrote:
Hi Mark.
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: Wednesday, April 15, 2015 6:41 PM
To: Michal Simek
Cc: u-boot@lists.denx.de; Tom Rini; Siva Durga Prasad Paladugu;
Hello Vladimir,
On Fri, 20 Mar 2015 18:16:17 +0300, Vladimir Barinov
vladimir.bari...@cogentembedded.com wrote:
From: Valentine Barshak valentine.bars...@cogentembedded.com
This enables ARMv7 barrier operations support when
march=armv7-a is enabled.
Using CP15 barriers causes U-Boot
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
the two dwc3
Hello Thierry,
I assume there will be a v2 series?
(asking so that I can mark the series Changes Requested)
Amicalement,
--
Albert.
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Hello Axel,
On Tue, 14 Apr 2015 14:55:24 +0800, Axel Lin axel@ingics.com
wrote:
The LPC32XX GPIO driver platdata currently contains GPIO state information,
which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
On Wed, Apr 15, 2015 at 05:57:55PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add the initial SPL support for HummingBoard-i2eX, which is based on a
MX6 Dual.
For more information about HummingBoard, please check:
Hello Michal,
Michal Simek wrote on 2015-04-16:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Fix wrong timer calculation in get_timer_masked incase of overflow. This
fixes the issue of getting wrong time from get_timer() calls.
Signed-off-by: Siva Durga Prasad Paladugu
On Wed, Apr 15, 2015 at 05:57:55PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add the initial SPL support for HummingBoard-i2eX, which is based on a
MX6 Dual.
For more information about HummingBoard, please check:
Hello Alexander,
On Thu, 19 Mar 2015 18:37:19 +0100, Alexander Merkle
alexander.mer...@lauterbach.com wrote:
Signed-off-by: Alexander Merkle alexander.mer...@lauterbach.com
---
drivers/serial/arm_dcc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Hello Alexander,
On Thu, 19 Mar 2015 18:37:20 +0100, Alexander Merkle
alexander.mer...@lauterbach.com wrote:
Signed-off-by: Alexander Merkle alexander.mer...@lauterbach.com
---
include/configs/zynq-common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/zynq-common.h
From: Dinh Nguyen dingu...@opensource.altera.com
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen
On Thu, Apr 16, 2015 at 12:46 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
I have no problem with the whole series, I will start to apply. Just a
couple of questions:
On 08/04/2015 21:54, Tim Harvey wrote:
Certain older kernels in use by some customers erroneously define a uart3
for
Hello Matt,
On Tue, 14 Apr 2015 14:07:17 -0400, Matt Porter mpor...@konsulko.com
wrote:
common/image.c currently implicitly depends on CONFIG_NR_DRAM_BANKS
when CONFIG_ARM is enabled. Make this requirement explicit.
Signed-off-by: Matt Porter mpor...@konsulko.com
---
common/image.c | 2 +-
On Thu, Apr 16, 2015 at 03:52:16PM +0200, Albert ARIBAUD wrote:
Hello Matt,
On Tue, 14 Apr 2015 14:07:17 -0400, Matt Porter mpor...@konsulko.com
wrote:
common/image.c currently implicitly depends on CONFIG_NR_DRAM_BANKS
when CONFIG_ARM is enabled. Make this requirement explicit.
On Thu, Apr 16, 2015 at 03:53:56PM +0200, Albert ARIBAUD wrote:
Hello Matt,
On Tue, 14 Apr 2015 14:07:18 -0400, Matt Porter mpor...@konsulko.com
wrote:
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1
On Tue, Apr 14, 2015 at 09:50:47PM +0200, Marcel Ziswiler wrote:
From: Max Krummenacher max.krummenac...@toradex.com
Without this, when CONFIG_ENV_VARS_UBOOT_CONFIG is active we get
a compile time error when doing 'make env'.
In file included from tools/env/fw_env.c:117:0:
On Thursday, April 16, 2015 at 03:41:49 PM, Dinh Nguyen wrote:
On 4/16/15 1:32 AM, Marek Vasut wrote:
On Wednesday, April 15, 2015 at 11:14:50 PM,
dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Hello,
The following 2 patches adds the
Hello Bryan,
On Tue, 24 Mar 2015 11:25:12 -0500, Bryan Brinsko
bryan.brin...@rockwellcollins.com wrote:
The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those
Hello Matt,
On Tue, 14 Apr 2015 14:07:18 -0400, Matt Porter mpor...@konsulko.com
wrote:
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.
This should be done for all targets which build
From: Dinh Nguyen dingu...@opensource.altera.com
Hi,
This is a resend of the patch series that adds the DDR controller driver for
Altera's SoCFPGA platform. This resend contains a new patch:
arm: socfpga: enable the Altera SDRAM controller driver
This new patch is necessary for the driver to
From: Dinh Nguyen dingu...@opensource.altera.com
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_common.h
Hi Tom,
On 15 April 2015 at 12:16, Marek Vasut ma...@denx.de wrote:
On Wednesday, April 15, 2015 at 03:43:37 PM, Tom Rini wrote:
On Wed, Apr 15, 2015 at 07:29:41AM -0600, Simon Glass wrote:
Hi Tom,
On 15 April 2015 at 07:08, Tom Rini tr...@konsulko.com wrote:
On Tue, Apr 14, 2015 at
On Thu, Apr 16, 2015 at 08:32:03AM +0100, Hans de Goede wrote:
Hi,
On 15-04-15 21:57, Ian Campbell wrote:
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
For unknown reasons the A33 needs the end of the memory we report to the
kernel to be aligned to a multiple of 4 MiB.
Do
On Tue, Apr 14, 2015 at 12:11:00PM -0600, Simon Glass wrote:
Hi Tom,
Here are the driver model changes that have been queued up on
u-boot-dm/next. The main changes are:
- Ethernet driver model support
- USB driver model support
- PCI driver model support
- Network cosmetic changes
-
On Tue, Apr 14, 2015 at 05:50:50AM +0200, Marek Vasut wrote:
The following changes since commit f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35:
Prepare v2015.04 (2015-04-13 10:53:03 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git HEAD
for you to fetch
On 03/27/2015 12:48 AM, Shengzhou Liu wrote:
T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC.
T1023RDB board Overview
---
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions
On Wednesday, April 15, 2015 at 09:27:23 AM, Jörg Krause wrote:
Calculating the ECC strength dynamically to be aligned with the mxs NAND
driver and the Linux Kernel.
Signed-off-by: Jörg Krause joerg.krause@embedded.rocks
Reviewed-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
On Wednesday, April 15, 2015 at 09:27:22 AM, Jörg Krause wrote:
Signed-off-by: Jörg Krause joerg.krause@embedded.rocks
---
Changes for v3:
- Replace space with tab for macro definition
Changes for v2:
- New patch
---
Reviewed-by: Marek Vasut ma...@denx.de
Best regards,
Marek Vasut
On 03/24/2015 02:27 AM, Zhuoyu Zhang wrote:
For ls1021a, Reserve secure code in to memory in case OCRAM
is needed by other usage.
Signed-off-by: Zhuoyu Zhang zhuoyu.zh...@freescale.com
---
include/configs/ls1021aqds.h | 1 -
include/configs/ls1021atwr.h | 1 -
2 files changed, 2
On Thu, Apr 16, 2015 at 05:17:00PM +0530, Kishon Vijay Abraham I wrote:
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to
On Wed, Apr 15, 2015 at 05:05:02PM +0200, Hans de Goede wrote:
Hi Tom,
Please pull u-boot-sunxi/master into master for the first series of sunxi
patches for v2015.07. This consists of a mix of bug-fixes, improvements
and new boards.
The following changes since commit
Shengzhou,
On 03/31/2015 11:45 PM, Shengzhou Liu wrote:
T2080RDB RevC uses new SODIMM 1867MT/s instead of previous 1600MT/s.
So update RCW to support new DDR frequency i.e 1867MT/s
This patch updates RCW. The subject is not clear.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
On 03/25/2015 07:46 AM, Vijay Rai wrote:
snip
diff --git a/configs/T1040D4RDB_NAND_defconfig
b/configs/T1040D4RDB_NAND_defconfig
new file mode 100644
index 000..8212b34
--- /dev/null
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
On 03/25/2015 10:52 PM, Yangbo Lu wrote:
snip
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 313fa1e..5462b4c 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -16,6 +16,10 @@
/* needed for the mmc_cfg definition */
#include mmc.h
+#ifdef
On Wednesday, April 15, 2015 at 12:54:28 PM, Sanchayan Maity wrote:
Enable USB support on Toradex Colibri Vybrid Modules.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
board/toradex/colibri_vf/colibri_vf.c | 25 +--
include/configs/colibri_vf.h |
On 04/14/2015 05:46 AM, Stefan Roese wrote:
This patch series adds support for the Marvell Armada A38x SoC's. Specifically
the 88F6820 / 88F6828.
Basic support for the DB-88F6820-GP evaluation board is added. Supporting the
following interfaces:
- UART
- SPI (including SPI NOR flash)
- I2C
Hi,
On 16-04-15 19:35, Mark Rutland wrote:
On Thu, Apr 16, 2015 at 08:32:03AM +0100, Hans de Goede wrote:
Hi,
On 15-04-15 21:57, Ian Campbell wrote:
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
For unknown reasons the A33 needs the end of the memory we report to the
kernel to be
Hi Sören,
2015-04-15 1:03 GMT+09:00 Sören Brinkmann soren.brinkm...@xilinx.com:
On Tue, 2015-04-14 at 04:50PM +0900, Masahiro Yamada wrote:
Separate CONFIG_TARGET_ZYNQ_{ZC702,ZC706} which is necessary
for the next commit. Adjust doc/README.zynq too.
Signed-off-by: Masahiro Yamada
Enable eSDHC adapter card type identification and this will do
some corresponding operations and set 'adapter-type' property
for device tree according SDHC Card ID.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun york...@freescale.com
---
include/configs/T208xQDS.h | 1 +
1 file
Add adapter card type identification support by reading
FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
define CONFIG_FSL_ESDHC_ADAPTER_IDENT.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun york...@freescale.com
---
Changes for v2:
- Document
Enable eSDHC peripheral clock support for kernel, and linux will
use SD clock generated by peripheral clock instead of platform
clock.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun york...@freescale.com
---
include/configs/T208xQDS.h | 1 +
1 file changed, 1 insertion(+)
diff
Hi Mark,
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: Thursday, April 16, 2015 3:29 PM
To: Siva Durga Prasad Paladugu
Cc: Michal Simek; u-boot@lists.denx.de; Tom Rini; Varun Sethi; Arnab Basu;
York Sun
Subject: Re: [U-Boot] [PATCH 1/2] armv8: caches:
The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for kernel for T1024/T1040/T2080. To enable it,
define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun
On 04/16/2015 08:13 PM, Jagan Teki wrote:
On 15 April 2015 at 19:03, Michal Simek michal.si...@xilinx.com wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Added the SPI driver support for ZynqMP
The controller is same as zynq SPI controller
Signed-off-by: Siva Durga
This commit adds functions issuing calls to firmware. This allows
to use services such as PSCI provided by firmware, e.g. ATF
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
arch/arm/cpu/armv8/Makefile | 1 +
This commit adds basic Cavium ThunderX 88xx board definitions and support.
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
arch/arm/Kconfig | 4 +
board/cavium/thunderx/Kconfig| 19 +
This commit adds the psci.h header file from Linux kernel
which contains definitions related to the PSCI interface provided
by firmware
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
include/linux/psci.h | 90
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of
This patch series adds support for Cavium ThunderX 88xx SoC family
(http://www.cavium.com/ThunderX_ARM_Processors.html).
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On some systems, UART initialization is performed before running U-Boot.
This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
drivers/serial/serial_pl01x.c
On Thu, Apr 16, 2015 at 7:36 PM, Nikolay Dimitrov picmas...@mail.bg wrote:
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible
Hi Tom,
On 16 April 2015 at 11:43, Tom Rini tr...@konsulko.com wrote:
On Tue, Apr 14, 2015 at 12:11:00PM -0600, Simon Glass wrote:
Hi Tom,
Here are the driver model changes that have been queued up on
u-boot-dm/next. The main changes are:
- Ethernet driver model support
- USB driver
Hi Jagan,
On Fri, Apr 17, 2015 at 2:09 AM, Jagan Teki jagannadh.t...@gmail.com wrote:
Hi Bin,
I think you have a different interpretation of sector size here-
/* The size listed here is what works with SPINOR_OP_SE, which isn't
* necessarily called a sector by the vendor.
*/
Say for
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses
Change the dram_init() function on ThunderXto query ATF services for
the real installed DRAM size
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
board/cavium/thunderx/Makefile | 2 +-
This commit adds functions issuing calls to the product-specific ATF
services
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
board/cavium/thunderx/Makefile | 2 +-
board/cavium/thunderx/atf.c | 312
From: Fabio Estevam fabio.este...@freescale.com
mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus
and 2GiB, so fix the width and density fields accordingly.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/freescale/mx6sabresd/mx6sabresd.c | 9 +
From: Fabio Estevam fabio.este...@freescale.com
RTT_NOM_120OHM is not defined, so remove its ifdef.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/freescale/mx6sabresd/mx6sabresd.c | 4
1 file changed, 4 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
Licenses/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Licenses/README b/Licenses/README
index fe6dadc..9b9a462 100644
--- a/Licenses/README
+++ b/Licenses/README
@@ -47,7 +47,7 @@ used under the terms
From: Fabio Estevam fabio.este...@freescale.com
Add the initial SPL support for HummingBoard-i2eX, which is based on a
MX6 Dual.
For more information about HummingBoard, please check:
http://www.solid-run.com/products/hummingboard/
Based on the work from Jon Nettleton and Rabeeh Khoury.
Hi Tom,
As mentioned I reverted this patch as it conflicted with the dm tree
and I suspect it might be buggy:
cd749658 usb_storage : scan all interfaces to find a storage device
Assuming this is OK and applies successfully I will rebase and resend
this patch, then reply with some comments I
Hi Bin,
I think you have a different interpretation of sector size here-
/* The size listed here is what works with SPINOR_OP_SE, which isn't
* necessarily called a sector by the vendor.
*/
Say for example SST25VF040B has 8 sectors of which each sector size is
64 * 1024 out of this we can use
On 15 April 2015 at 19:03, Michal Simek michal.si...@xilinx.com wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Added the SPI driver support for ZynqMP
The controller is same as zynq SPI controller
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com
---
include/configs/nitrogen6x.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 8ef4b73..0ca02e9 100644
--- a/include/configs/nitrogen6x.h
+++
On 9 February 2015 at 04:57, Michael Walle mich...@walle.cc wrote:
Hi there,
I stumbled across a situation where the SPI flash on my board was write
protected and i could not unlock it in the bootloader. This is especially
unfortunate because the recovery mechanism relies on the bootloader to
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