Hi Mingkai,
On Mon, Aug 17, 2015 at 2:49 PM, Mingkai Hu mingkai...@freescale.com wrote:
Please add a commit message on this change.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/e1000.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Hi Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Monday, August 17, 2015 2:42 PM
To: Siva Durga Prasad Paladugu
Cc: Stefan Roese; u-boot@lists.denx.de; Hou Zhiqiang; York Sun
Subject: Re: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte address
On Mon, Aug 17, 2015 at 4:59 PM, Masahiro Yamada
yamada.masah...@socionext.com wrote:
2015-08-17 17:44 GMT+09:00 Przemyslaw Marczak p.marc...@samsung.com:
Hi Masahiro,
On 08/17/2015 08:51 AM, Masahiro Yamada wrote:
This file was accidentally added by commit 181bd9dc61d2 (kconfig:
add config
Bootlog:
U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 33024000 Hz, block size 512
reading u-boot.img
reading u-boot.img
Hi,
On 17-08-15 10:19, Ian Campbell wrote:
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value currently being written is
actual wrong, the ecc sits at column +
This patch adds flag status register reading support to
spi_flash_cmd_wait_ready.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Simon Glass s...@chromium.org
Cc: Marek Vasut ma...@denx.de
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
Cc: Stefan
On 17 August 2015 at 08:33, Hou Zhiqiang b48...@freescale.com wrote:
Hello Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: 2015年8月16日 16:50
To: u-boot@lists.denx.de; Hou Zhiqiang-B48286; Sun York-R58495
Cc: Jagan Teki
Subject: Re: [PATCH 0/6] sf:
DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.
For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE
Hi Simon,
On Sat, Aug 15, 2015 at 3:07 PM, Bin Meng bmeng...@gmail.com wrote:
With driver model pci conversion, the call to FspNotify was dropped.
Now add this call back as this is required by the FSP spec.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/tnc.c | 8
Hi Tom,
I resynchronize the master branch this morning,
and only patch 7/7 of the series appear in u-boot/master;
Is it possible that patch 1/7 to 6/7 were not applied?
For your convenience this is a list of links to patchwork:
* http://patchwork.ozlabs.org/patch/500510/
*
On Mon, Aug 17, 2015 at 11:34:59AM +, LEMIEUX, SYLVAIN wrote:
Hi Tom,
I resynchronize the master branch this morning,
and only patch 7/7 of the series appear in u-boot/master;
Is it possible that patch 1/7 to 6/7 were not applied?
For your convenience this is a list of links to
On 17/08/2015 10:12, Peng Fan wrote:
Enable CONFIG_SPL_FAT_SUPPORT to load u-boot.img from FAT partition.
Signed-off-by: Peng Fan peng@freescale.com
---
include/configs/mx6sxsabresd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/mx6sxsabresd.h
From: Tang Yuantian yuantian.t...@freescale.com
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian
Hi Roy,
On Mon, 17 Aug 2015 09:30:38 +0100
Roy Spliet se...@nimrod-online.com wrote:
Hello,
Reply in-line
Op 17-08-15 om 08:34 schreef Boris Brezillon:
Hi Oliver,
Sorry for the late reply (I was in vacation for the last 2 weeks)
On Tue, 11 Aug 2015 14:16:52 +0200
Olliver
On 17 August 2015 at 14:26, Siva Durga Prasad Paladugu
siva.durga.palad...@xilinx.com wrote:
Hi Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Monday, August 17, 2015 1:43 PM
To: Siva Durga Prasad Paladugu
Cc: Hou Zhiqiang; Stefan Roese; nofooter; York
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.
Signed-off-by: Vignesh R vigne...@ti.com
Reviewed-by: Jagan Teki jt...@openedev.com
---
* Added a TODO comment
drivers/spi/ti_qspi.c | 25 +
1 file changed, 25
On 17 August 2015 at 10:48, Bin Meng bmeng...@gmail.com wrote:
Hi Igor,
On Mon, Aug 17, 2015 at 3:10 PM, Stoppa, Igor igor.sto...@intel.com wrote:
[...]
One other thing that I haven't fully investigated yet (so maybe it's
already explained elsewhere) is: after the application/payload is
On 17 August 2015 at 12:48, Stoppa, Igor igor.sto...@intel.com wrote:
I'm referring to this:
http://www.denx.de/wiki/view/DULG/UBootEnvVariables
I thought it would become a partition, but maybe I've assumed too much
and it is implemented in some other way?
ah, I see now that I should use
Add spi_flash_read_bar function for reading bar and discovering
bar commands at probe time.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
drivers/mtd/spi/sf_probe.c | 54
Current flash wait_ready logic is not modular to add new
register status check, hence few of the logic is used from
Linux spi-nor framework.
Below are the sf speed runs with 'sf update' on whole flash, 16MiB.
= sf update 0x100 0x0 0x100
device 0 whole chip
16777216 bytes written, 0 bytes
- Removed unneeded inclusion of header files
- Add Xilinx on license text
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
drivers/spi/zynq_spi.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
Optimized spi-flash bar writing code and also removed
unnecessary bank_sel in read_ops.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
drivers/mtd/spi/sf_ops.c | 41
If computed bank_sel is same as flash-bank_curr which is
computed at probe time, then return the bank_sel instead of zero.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
drivers/mtd/spi/sf_ops.c | 2 +-
BAR and spi_flash_cmd_wait_ready are updated to make more
module to add new status checks.
Changes for v2:
- Update bank_sel for non-bar case.
- split the spi_flash_cmd_wait_ready logic into SR and FSR patches.
Clone spi-nor branch u-boot-spi.git repo for changes
Use the flash-flags for generic usage, not only for dm-spi-flash,
this will be used for future flag additions.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Bin Meng bmeng...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 4
drivers/mtd/spi/sf_probe.c| 6 ++
include/spi_flash.h
+Wolfgang
Hi Wolfgang,
On Sat, Aug 15, 2015 at 9:44 AM, Bin Meng bmeng...@gmail.com wrote:
Hi,
I noticed that this morning when I do git fetch it always fails with
Connection reset by peer message.
$ git fetch x86
fatal: read error: Connection reset by peer
Also patchwork is not
On 17 August 2015 at 14:44, Siva Durga Prasad Paladugu
siva.durga.palad...@xilinx.com wrote:
Hi Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Monday, August 17, 2015 2:42 PM
To: Siva Durga Prasad Paladugu
Cc: Stefan Roese; u-boot@lists.denx.de; Hou
Hi,
On 17-08-15 10:27, Ian Campbell wrote:
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
We currently only use the spl nand code to get u-boot itself, which
_always_ is located on a syndrome partition. Once we figure out how
we are going to store the u-boot env on nand, we may need
From: Tang Yuantian yuantian.t...@freescale.com
Freescale ARM-based Layerscape LS2085A contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2085aqds and ls2085ardb boards.
Signed-off-by: Tang Yuantian
Hi Simon,
On Sat, Aug 15, 2015 at 3:07 PM, Bin Meng bmeng...@gmail.com wrote:
This adds a new driver to support National Semiconductor 16550
compatible UART device with PCI interface. The initial support
only adds device IDs for Intel Topcliff chipset UART devices.
Signed-off-by: Bin Meng
Hi Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Monday, August 17, 2015 1:43 PM
To: Siva Durga Prasad Paladugu
Cc: Hou Zhiqiang; Stefan Roese; nofooter; York Sun; u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into
2015-08-17 17:44 GMT+09:00 Przemyslaw Marczak p.marc...@samsung.com:
Hi Masahiro,
On 08/17/2015 08:51 AM, Masahiro Yamada wrote:
This file was accidentally added by commit 181bd9dc61d2 (kconfig:
add config option for shell prompt).
Signed-off-by: Masahiro Yamada
This commit cleans up the existing i8042 driver by:
- Reorder those static function so that their declarations can be removed
- Remove unused routines i8042_flush() and i8042_disable()
- Remove unused CONFIG_USE_CPCIDVI wrapped codes
- Remove __weak board_i8042_skip()
- Rename CamelCase variables
Add an api to enable and configure the integrated keyboard controller
on SMSC LPC47m superio chipset. It also adds several macros to help
future extension.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/include/asm/ibmpc.h | 3 +++
drivers/misc/smsc_lpc47m.c | 11 +++
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.
In order to make PS/2 keyboard work
So far if CONFIG_VGA_AS_SINGLE_DEVICE is not defined, the VGA device
will try to initialize a keyboard device (for x86, it is i8042). But
if i8042 controller initialization fails (eg: there is no keyboard
connected to the PS/2 port), drv_video_init() just simply returns.
This kills the opportunity
The existing i8042 keyboard controller driver has some issues.
First of all, it does not issue a self-test command (0xaa) to the
controller at the very beginning. Without this, the controller
does not respond any command at all. Secondly, it initializes
the configuration byte reigster to turn on
On Mon, 2015-08-17 at 10:59 +0200, Hans de Goede wrote:
Hi,
On 17-08-15 10:19, Ian Campbell wrote:
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
In syndrome mode we set the NFC_SEQ bit in the command register,
so the
spare-area register is not used. Also the value
Hi Dave,
On 08/15/2015 10:45 AM, Dave Williams wrote:
I am trying to build Uboot for Nios2.
I do the following on Linux bash.
git clone git://git.denx.de/u-boot-nios.git
cd u-boot-nios/
make menuconfig
Sorry that the u-boot-nios.git is used for upstreaming to u-boot.git
only, and is not
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected
boards.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Joe Hershberger joe.hershber...@ni.com
---
Changes in v4:
- Rebase to master
Changes in v3:
- Add CONFIG_NETDEVICES where needed
- Add required changes to the
On 17 August 2015 at 07:30, Jagan Teki jt...@openedev.com wrote:
Add Zynq QSPI controller Kconfig entry.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. But we won't
bind all devices found during the enumeration. Only devices whose
driver with DM_FLAG_PRE_RELOC
Hi Bin,
On 17 August 2015 at 05:08, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Aug 15, 2015 at 3:07 PM, Bin Meng bmeng...@gmail.com wrote:
With driver model pci conversion, the call to FspNotify was dropped.
Now add this call back as this is required by the FSP spec.
On 17 August 2015 at 07:30, Jagan Teki jt...@openedev.com wrote:
Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.
= sf probe
SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total
16 MiB
= mw.b 0x100
Hi Hans,
On 17 August 2015 at 10:08, Hans de Goede hdego...@redhat.com wrote:
Before this patch malloc_simple would always allocate a chunk of RAM from
the stack. This commit adds a CONFIG_SYS_MALLOC_F_BASE define, which when
set directly specifies the memory address to use for the heap with
On 16 August 2015 at 15:27, Simon Glass s...@chromium.org wrote:
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
With recent EFI support, the entry point address of coreboot payload
was changed. Now we update the address to use _x86boot_start, which
is the same one for EFI.
On 16 August 2015 at 19:22, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Mon, Aug 17, 2015 at 5:27 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
coreboot has some extensions (type 6 16) to the E820 types.
When we detect
On 16 August 2015 at 15:27, Simon Glass s...@chromium.org wrote:
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
When booting as a coreboot payload, we don't need write any
configuration tables as coreboot does that for us.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
On 16 August 2015 at 15:27, Simon Glass s...@chromium.org wrote:
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.
Signed-off-by: Bin Meng
On 16 August 2015 at 15:27, Simon Glass s...@chromium.org wrote:
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
Some platforms may have =4GiB memory, so we need make U-Boot report
such configuration correctly when booting as the coreboot payload.
Signed-off-by: Bin Meng
Hi Simon,
On Tue, Aug 18, 2015 at 10:00 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
After fsp_init() returns, the stack has already been switched to a
place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
Hi Bin,
On 17 August 2015 at 20:02, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Aug 18, 2015 at 10:00 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
To further limit the memory space, we only allow serial device
to
On Tue, Aug 18, 2015 at 10:00 AM, Simon Glass s...@chromium.org wrote:
+Anatolij
Hi Bin,
On 17 August 2015 at 04:45, Bin Meng bmeng...@gmail.com wrote:
So far if CONFIG_VGA_AS_SINGLE_DEVICE is not defined, the VGA device
will try to initialize a keyboard device (for x86, it is i8042). But
Simon,
2015-08-18 11:19 GMT+09:00 Simon Glass s...@chromium.org:
Hi,
FYI, next time you might want to do git format-patch -D to keep
the patch smaller :)
Acked-by: Marek Vasut ma...@denx.de
I use Patman to send patches.
Patman generates smaller patches for file move (with format-patch
Update this driver to support driver model.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Joe Hershberger joe.hershber...@ni.com
Tested-by: Marcel Ziswiler marcel.ziswi...@toradex.com
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
---
Changes in v4: None
Changes in v3:
- Add a
Add Kconfig options in preparation for moving boards to use Kconfig.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3:
- Drop CONFIG_E1000_FALLBACK_MAC option
Changes in v2:
- Move the Kconfig additions to a new patch
drivers/net/Kconfig | 32
We cannot currently include any header files in the C files since common.h
needs to be included first, and it is in the header file. Move it.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
Acked-by: Joe Hershberger joe.hershber...@ni.com
Tested-by: Marcel
Hey all,
I've pushed v2015.10-rc2 out and it should be everywhere soon.
I've made an initial push through my backlog of stuff and I can see more
stuff I need to pick up. But please feel free to poke me here or
off-list if you own something that you think should be in v2015.10 but
hasn't been
Hi Simon,
On Tue, Aug 18, 2015 at 10:18 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
After fsp_init() returns, the stack has already been switched to a
place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
This patch rewrites MMU translation table entries. To start, all table
entries are written as invalid, then device-ngnrnr and normal are
written to the entries to enable access to specific addresses.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: York Sun
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.
Drop the unneeded code and adjust the hooks in board_f.c to cope.
Signed-off-by: Simon Glass
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.
Drop the unneeded code and adjust the hooks in board_f.c to cope.
Signed-off-by: Simon Glass
On 17 August 2015 at 20:30, Masahiro Yamada
yamada.masah...@socionext.com wrote:
This allows Patman to generate smaller patches for file removal.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
tools/patman/gitutil.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Update this driver to support driver model.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Joe Hershberger joe.hershber...@ni.com
Tested-by: Marcel Ziswiler marcel.ziswi...@toradex.com
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
---
Changes in v5:
- Correct compatible string
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
ACPI(Advanced Configuration and Power Interface), is a Power Management and
configuration standard allowing the operating system to control the amount of
power each device is given (allowing it to put
Hi Bin,
On 17 August 2015 at 04:45, Bin Meng bmeng...@gmail.com wrote:
Add an api to enable and configure the integrated keyboard controller
on SMSC LPC47m superio chipset. It also adds several macros to help
future extension.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Hi Bin,
On 17 August 2015 at 18:20, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Aug 18, 2015 at 6:14 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
This adds a new driver to support National Semiconductor 16550
On 17 August 2015 at 04:45, Bin Meng bmeng...@gmail.com wrote:
This commit cleans up the existing i8042 driver by:
- Reorder those static function so that their declarations can be removed
- Remove unused routines i8042_flush() and i8042_disable()
- Remove unused CONFIG_USE_CPCIDVI wrapped
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
After fsp_init() returns, the stack has already been switched to a
place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
Enlarge the size of malloc() pool before relocation since we have
plenty of memory now.
+Anatolij
Hi Bin,
On 17 August 2015 at 04:45, Bin Meng bmeng...@gmail.com wrote:
So far if CONFIG_VGA_AS_SINGLE_DEVICE is not defined, the VGA device
will try to initialize a keyboard device (for x86, it is i8042). But
if i8042 controller initialization fails (eg: there is no keyboard
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
Move x86_fsp_init() call after initf_malloc() so that we can fix up
the gd-malloc_limit later.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
common/board_f.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
On 17 August 2015 at 04:45, Bin Meng bmeng...@gmail.com wrote:
The existing i8042 keyboard controller driver has some issues.
First of all, it does not issue a self-test command (0xaa) to the
controller at the very beginning. Without this, the controller
does not respond any command at all.
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
To further limit the memory space, we only allow serial device
to be bound before relocation.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/pci/pci-uclass.c | 6 +-
1 file changed, 5 insertions(+), 1
On 17 August 2015 at 04:45, Bin Meng bmeng...@gmail.com wrote:
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can
Hi Simon,
On Tue, Aug 18, 2015 at 10:00 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
To further limit the memory space, we only allow serial device
to be bound before relocation.
Signed-off-by: Bin Meng bmeng...@gmail.com
Dear Tom,
The following changes since commit 632093b566569329bc6e5b0893bdca01de905314:
Merge git://git.denx.de/u-boot-x86 (2015-08-14 16:27:16 -0400)
are available in the git repository at:
http://git.denx.de/u-boot-samsung
for you to fetch changes up to
Several files are out of order. This means that when the moveconfig tool
moves CONFIG options to Kconfig it generates a large diff. To avoid this,
reorder the files first.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4:
- Rebase to master
Changes in v3: None
Changes in v2:
- Add
Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid
using it in the driver unless necessary. Most of the time it is better to
pass the private driver pointer anyway.
Also refactor the code so that code that the driver model implementation
will share are available in functions
This little series updates the e1000 Ethernet driver to support driver
model. It also moves the configuration to Kconfig and adjusts all boards
using Masahiro's excellent moveconfig tool.
To avoid a large patch which mixes irrelevant changes this series includes a
patch to reorder the defconfig
Hi Simon,
On Tue, Aug 18, 2015 at 6:14 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
This adds a new driver to support National Semiconductor 16550
compatible UART device with PCI interface. The initial support
only adds
2015-08-17 13:59 GMT+09:00 Heiko Schocher h...@denx.de:
Hello Masahiro,
Am 16.08.2015 um 11:59 schrieb Masahiro Yamada:
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada
Hi Marek,
CCing Simon,
2015-08-18 10:56 GMT+09:00 Marek Vasut ma...@denx.de:
On Sunday, August 16, 2015 at 11:59:50 AM, Masahiro Yamada wrote:
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada
Hi Simon,
On Tue, Aug 18, 2015 at 9:59 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 17 August 2015 at 05:08, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Aug 15, 2015 at 3:07 PM, Bin Meng bmeng...@gmail.com wrote:
With driver model pci conversion, the call to FspNotify was
This allows Patman to generate smaller patches for file removal.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
tools/patman/gitutil.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index 9e739d8..67b086b
Hi Peter,
On 30 July 2015 at 11:55, Peter Griffin peter.grif...@linaro.org wrote:
To help others with compiling and flashing ATF and u-boot add
a README for this board.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
board/hisilicon/hikey/README | 160
The doc has a misleading 'make menuconfig' when building the EFI
application and payload. Clarify this and also update information
on test with QEMU.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3:
- further changes to clarify efi app vs
On Sunday, August 16, 2015 at 11:59:50 AM, Masahiro Yamada wrote:
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Cc: Heiko Schocher h...@denx.de
---
Hi Simon,
On Tue, Aug 18, 2015 at 10:00 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 17 August 2015 at 04:45, Bin Meng bmeng...@gmail.com wrote:
Add an api to enable and configure the integrated keyboard controller
on SMSC LPC47m superio chipset. It also adds several macros to help
Hi Simon,
On Tue, Aug 18, 2015 at 10:00 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 17 August 2015 at 18:20, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Aug 18, 2015 at 6:14 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng
Hi Hans,
On 6 August 2015 at 12:13, Hans de Goede hdego...@redhat.com wrote:
sun6i and later have a couple of io-blocks which are shared between the
main CPU core and the R cpu which is small embedded cpu which can be
active while the main system is suspended.
These gpio banks sit at a
Hi Bin,
On 15 August 2015 at 01:07, Bin Meng bmeng...@gmail.com wrote:
This adds a new driver to support National Semiconductor 16550
compatible UART device with PCI interface. The initial support
only adds device IDs for Intel Topcliff chipset UART devices.
Signed-off-by: Bin Meng
Hi Marcel,
On 16 August 2015 at 15:34, Marcel Ziswiler mar...@ziswiler.com wrote:
On Sun, 2015-08-16 at 15:26 -0600, Simon Glass wrote:
Says who? I was only aware that common.h needs to go on top, the
local
stuff (e.g. in double quotes) on the bottom and the rest I assumed
can
go
On 14 August 2015 at 19:44, Bin Meng bmeng...@gmail.com wrote:
The doc has a misleading 'make menuconfig' when building the EFI
application and payload. Clarify this and also update information
on test with QEMU.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- incorporate
Hi,
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
This series adds some improvment to the existing coreboot support,
like =4GiB memory support, correct E820 table report, don't bother
configure system tables in Kconfig and support booting Linux kernel
with a working graphics
On 16 August 2015 at 15:27, Simon Glass s...@chromium.org wrote:
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
Increase lib_sysinfo memrange entry number to 32 to sync with coreboot.
This allows a complete E820 table to be reported to the kernel, as on
some platforms (eg:
Hi Simon,
On Tue, Aug 18, 2015 at 10:00 AM, Simon Glass s...@chromium.org wrote:
On 17 August 2015 at 04:45, Bin Meng bmeng...@gmail.com wrote:
This commit cleans up the existing i8042 driver by:
- Reorder those static function so that their declarations can be removed
- Remove unused
From: Hou Zhiqiang b48...@freescale.com
It doesn't make sense to compare a 'u8' element with Zero.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
drivers/mtd/spi/sf_ops.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c
On 16 August 2015 at 15:27, Simon Glass s...@chromium.org wrote:
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
Instead of hiding each menu entries under System tables for EFI,
hide the main menu completely.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/Kconfig |
On 16 August 2015 at 19:25, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Mon, Aug 17, 2015 at 5:27 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
When running U-Boot bare-metal, the cbfs command is useless.
Signed-off-by:
On 16 August 2015 at 15:27, Simon Glass s...@chromium.org wrote:
On 13 August 2015 at 01:29, Bin Meng bmeng...@gmail.com wrote:
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng bmeng...@gmail.com
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