On Saturday, January 16, 2016 01:26 PM, Marek Vasut wrote:
On Monday, January 04, 2016 at 12:06:17 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot,
at the present moment it's just available for ar933x and qca953x chip.
Changes in v6:
- Remove
Hi Stefan,
On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese wrote:
> Hi Simon, Hi Bin!
>
> I'm currently busy with porting U-Boot to a Bay Trail board.
> Equipped with an Intel Atom E3845 and additionally the
> Nuvoton / Winbond W83627DHG Super IO chip.
>
> My staring point for this
Hi Miao,
On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan wrote:
> This patch adds the ability to load and link ACPI tables provided by QEMU.
> QEMU tells guests how to load and patch ACPI tables through its fw_cfg
> interface, by adding a firmware file 'etc/table-loader'.
Hi Miao,
On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan wrote:
> Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)
>
> Signed-off-by: Miao Yan
> ---
> arch/x86/cpu/qemu/qemu.c| 39
>
Hi Miao,
On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan wrote:
> Re-write the logic in qemu_fwcfg_list_firmware(), add a function
> qemu_cfg_read_firmware_list() to handle reading firmware list.
qemu_fwcfg_read_firmware_list()
>
> Signed-off-by: Miao Yan
Hi Miao,
On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan wrote:
> If CONFIG_GENERATE_ACPI_TABLE is not defined, then use ACPI table created
> by QEMU.
>
> Signed-off-by: Miao Yan
> ---
> arch/x86/lib/tables.c | 5 -
> 1 file changed, 4
As Thomas Petazzoni pointed out in [1] this issue is already fixed by
commit 69bf2d2fafe64349be3c3ef1256e3c68f812bb25 [2].
I fixed 2015.10 for me and ported the patch forward to 2016.01 without
further verification if it is still needed and not fixed otherwise.
Regards,
Gerhard
[1]
Hi Bin,
On 21 December 2015 at 02:16, Bin Meng wrote:
> Hi Simon,
>
> On Sun, Dec 20, 2015 at 6:42 AM, Simon Glass wrote:
>> A Platform Controller Hub is an Intel concept - it is like the peripherals
>> on an SoC and is often in a separate chip from the
Hi Bin,
On 21 December 2015 at 02:16, Bin Meng wrote:
> Hi Simon,
>
> On Sun, Dec 20, 2015 at 6:42 AM, Simon Glass wrote:
>> At some point we may need to distinguish between different types of PCHs,
>> but for existing supported platforms we only need to
Hi Simon
As mentioned before I noticed Ethernet (on-module USB ASIX chip) to be
broken on master while it still worked fine in v2016.01. I kind of
remember having once noticed something along those lines when testing
some of your early dm stuff but could not find our discussion about it
anymore
Tom,
This patch is a bug-fix
and still keeping me from using bootm_low on my boards.
Please apply!
--
Best Regards
Masahiro Yamada
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
We need to use %lx not %x to describe a fdt_addr_t
Cc: Simon Glass
Signed-off-by: Tom Rini
---
drivers/spi/rk_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 5e0c6ad..242a83b
Add support for loading from UBI volumes on the top of NAND.
Signed-off-by: Ladislav Michl
---
common/spl/Makefile | 3 +++
common/spl/spl.c | 4
common/spl/spl_ubi.c | 68
include/spl.h| 4
4
From: Thomas Gleixner
Booting a payload out of NAND FLASH from the SPL is a crux today, as
it requires hard partioned FLASH. Not a brilliant idea with the
reliability of todays NAND FLASH chips.
The upstream UBI + UBI fastmap implementation which is about to
brought to
Other payload than uImage is currently considered to be raw U-Boot
image. Check also for zImage in Falcon mode.
Signed-off-by: Ladislav Michl
---
arch/arm/lib/Makefile | 2 ++
arch/arm/lib/bootm.c | 32
arch/arm/lib/zimage.c | 40
From: Thomas Gleixner
To support UBI in SPL we need a simple NAND read function. Add one to
nand_spl_simple and keep it as simple as it goes.
Signed-off-by: Thomas Gleixner
Signed-off-by: Ladislav Michl
Acked-by: Scott Wood
Convert IGEP board to use UBI volumes for U-Boot, its environment and
kernel. With exception of first four sectors read by SoC boot
ROM whole NAND is UBI managed. As code is too big now, drop
CONFIG_SPL_EXT_SUPPORT to make it fit.
Signed-off-by: Ladislav Michl
---
Implement spl_start_uboot to let Falcon mode work.
Signed-off-by: Ladislav Michl
---
board/isee/igep00x0/igep00x0.c | 12
1 file changed, 12 insertions(+)
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index e2fce50..92811d8
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot,
at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on
With gcc-5.3 we get a warning for using switch() on a bool type.
Rewrite these sections as if/else and update the one section that was
using 1/0 instead of true/false.
Cc: Simon Glass
Cc: Przemyslaw Marczak
Signed-off-by: Tom Rini
Split the movement of data between CPU and Host Controller from the
status handling and tracking of transfer progress.
This will also simplify adding of SPLIT transaction support.
Signed-off-by: Stefan Brüns
---
drivers/usb/host/dwc2.c | 112
The first patch fixes an out-of-bounds access, and makes the calculation of
maximum transfer size more straightforward. It also makes overriding the
maximum transfer size easier for split transactions
2nd and 3rd patch cleanup and restructure the current code in preparation
for the split support.
Hi,
yet another update of ubispl support. Please note, that igep00x0 specific
part depends on yet unapplied "[PATCHv2 0/5] igep00x0: Minor cleanup"
series
---
README |4
arch/arm/lib/Makefile |2
arch/arm/lib/bootm.c | 32 -
Hi Simon
On Thu, 2016-01-14 at 11:28 -0700, Simon Glass wrote:
> This series moves these two drivers over to use driver model for
> video.
>
> This involves the following steps:
> - Sync up some device tree files with Linux
> - Implement a proper PWM driver
> - Clean up and unify the driver code
On Fri, Jan 15, 2016 at 6:12 PM, Oscar Curero wrote:
> That way the FS can also be ext2/3/4
>
> Signed-off-by: Oscar Curero
Acked-by: Fabio Estevam
___
U-Boot mailing list
On Saturday 16 January 2016 09:33 PM, Mugunthan V N wrote:
> Adding timer init function in timer-uclass driver to create and
> initialize the timer device on platforms where u-boot,dm-pre-reloc
> is not used. Since there will be multiple timer devices in the
> system, adding a tick-timer node in
On Saturday, January 09, 2016 10:30 PM, Daniel Schwierzeck wrote:
Am Samstag, den 09.01.2016, 18:46 +0800 schrieb Wills Wang:
On 01/09/2016 12:23 AM, Daniel Schwierzeck wrote:
Am Montag, den 04.01.2016, 19:14 +0800 schrieb Wills Wang:
MIPS archtecture have no
Hi Mugunthan,
On 16 January 2016 at 09:08, Mugunthan V N wrote:
> On Saturday 16 January 2016 09:33 PM, Mugunthan V N wrote:
>> Adding timer init function in timer-uclass driver to create and
>> initialize the timer device on platforms where u-boot,dm-pre-reloc
>> is not
Am Sonntag, den 17.01.2016, 00:15 +0800 schrieb Wills Wang:
>
> On Saturday, January 09, 2016 10:30 PM, Daniel Schwierzeck wrote:
> > Am Samstag, den 09.01.2016, 18:46 +0800 schrieb Wills Wang:
> > > On 01/09/2016 12:23 AM, Daniel Schwierzeck wrote:
> > > > Am Montag, den 04.01.2016, 19:14 +0800
On Saturday 16 January 2016 10:11 PM, Simon Glass wrote:
> Hi Mugunthan,
>
> On 16 January 2016 at 09:08, Mugunthan V N wrote:
>> On Saturday 16 January 2016 09:33 PM, Mugunthan V N wrote:
>>> Adding timer init function in timer-uclass driver to create and
>>> initialize the
Hi Marcel,
On 15 January 2016 at 19:36, Marcel Ziswiler
wrote:
> Hi Simon
>
> On Thu, 2016-01-14 at 11:28 -0700, Simon Glass wrote:
>> This series moves these two drivers over to use driver model for
>> video.
>>
>> This involves the following steps:
>> - Sync up
On Sat, Jan 16, 2016 at 10:50 PM, Tom Rini wrote:
> With gcc-5.x we get:
> drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios':
> drivers/pci/pci_rom.c:352:3: warning: 'ram' may be used uninitialized in
> this function [-Wmaybe-uninitialized]
>
> While unconvinced that
Adding timer init function in timer-uclass driver to create and
initialize the timer device on platforms where u-boot,dm-pre-reloc
is not used. Since there will be multiple timer devices in the
system, adding a tick-timer node in chosen node to know which
timer device to be used as tick timer in
Signed-off-by: Wills Wang
---
Changes in v7:
- Use KSEG1 address for debug port in ap143
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/mips/dts/Makefile| 1 +
arch/mips/dts/ap143.dts | 43
On Saturday, January 16, 2016 at 02:15:27 PM, Wills Wang wrote:
> On Saturday, January 16, 2016 01:26 PM, Marek Vasut wrote:
> > On Monday, January 04, 2016 at 12:06:17 PM, Wills Wang wrote:
> >> These series of patch add support for atheros ath79 based SOCs in
> >> u-boot, at the present moment
On Saturday, January 16, 2016 11:33 PM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 02:15:27 PM, Wills Wang wrote:
On Saturday, January 16, 2016 01:26 PM, Marek Vasut wrote:
On Monday, January 04, 2016 at 12:06:17 PM, Wills Wang wrote:
These series of patch add support for atheros
Rename timer_init() to dm_timer_init() and remove dm_timer_init()
in lib/time.c as
* timer_init is called from board_f.c or board_r.c on different
architectures which may result causes timer devices to be
probed twice.
* lib/time.c dm_timer_init() does nothing other than calling
Signed-off-by: Wills Wang
---
Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers
Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early
This patch enable work for ar933x SOC.
Signed-off-by: Wills Wang
---
Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for ar933x
Changes in v6:
- Remove board.c
- Define magic value in ddr.c
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
Signed-off-by: Wills Wang
---
Changes in v7:
- Use KSEG1 address for debug port in ap121
Changes in v6:
- Convert SZ_XXX into hex in ap121.h
- Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
- Add board_early_init_f for DDR and pin initialization
- Select UART and SPI
This patch enable work for qca953x SOC.
Signed-off-by: Wills Wang
---
Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953x
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/mips/mach-ath79/Kconfig
Reviewed-by: Thomas Chou
Signed-off-by: Wills Wang
---
Changes in v7:
- remove map_physmem for debug port
Changes in v6:
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR
Changes in v5:
- remove ar933x_serial_platdata
-
Reviewed-by: Thomas Chou
Signed-off-by: Wills Wang
---
Changes in v7:
- Define spi_cs_activate/spi_cs_deactivate
- Rename MHZ to ATH79_SPI_MHZ
- Use clrsetbits_32
Changes in v6:
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove
With gcc-5.x we get:
drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios':
drivers/pci/pci_rom.c:352:3: warning: 'ram' may be used uninitialized in
this function [-Wmaybe-uninitialized]
While unconvinced that this can happen in practice (if we malloc we set
alloced to true, it will be false
On Sat, Jan 16, 2016 at 07:09:37AM +0100, Marek Vasut wrote:
> The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2:
>
> Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500)
>
> are available in the git repository at:
>
>
On Sat, Jan 16, 2016 at 07:08:30AM +0100, Marek Vasut wrote:
> The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2:
>
> Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500)
>
> are available in the git repository at:
>
>
Hi Simon,
Please find in this serie one bug fix and a typo cleanup.
Best Regards
Christophe
Christophe Ricard (2):
tpm: Fix fault in case CONFIG_DM_TPM is set without any TPM
tpm: tpm_tis_lpc: fix typo
common/cmd_tpm.c| 2 +-
drivers/tpm/Kconfig | 2 +-
lib/tpm.c | 2 +-
Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Reviewed-by: Thomas Chou
>
> Signed-off-by: Wills Wang
Reviewed-by: Daniel Schwierzeck
nits below
> ---
>
> Changes in v7:
> - remove map_physmem for debug
Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Reviewed-by: Thomas Chou
>
> Signed-off-by: Wills Wang
Reviewed-by: Daniel Schwierzeck
nits below
> ---
>
> Changes in v7:
> - Define
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
> These series of patch add support for atheros ath79 based SOCs in u-boot,
> at the present moment it's just available for ar933x and qca953x chip.
>
> This patch serises is based on mips_io_v4 branch on u-boot-mips repository
> [1]
On Saturday, January 16, 2016 at 07:13:47 PM, Wills Wang wrote:
Commit message is missing.
> Signed-off-by: Wills Wang
> ---
>
> Changes in v7:
> - Use setbits_32
> - Fix include path for SoC specific headers
>
> Changes in v6:
> - Move ar933x as separate patch
> - Add
Hi Simon,
After a first tentative in August 2015:
http://lists.denx.de/pipermail/u-boot/2015-August/222596.html
I finally found some spare time for a new round to send a new patchset version
bringing support for ST33ZP24 TPM 1.2 with i2c and spi support.
I have been able to follow all your
Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Signed-off-by: Wills Wang
my comments in patch 6/7 apply to this patch too
> ---
>
> Changes in v7:
> - Use KSEG1 address for debug port in ap143
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
Hi Tom,
please pull the first bunch of MIPS updates.
There is a possible merge conflict in dts/Makefile due to my patch [1]
in this PR and Thomas' patch [2] waiting in u-boot-fdt tree.
[1] http://patchwork.ozlabs.org/patch/566695/
[2] http://patchwork.ozlabs.org/patch/563669/
The following
Add support for TPM ST33ZP24 family with i2c.
For i2c we are relying only on DM_I2C.
Signed-off-by: Christophe Ricard
---
README | 7 +
drivers/tpm/Kconfig| 9 +
drivers/tpm/Makefile | 1 +
Add support for TPM ST33ZP24 spi.
The ST33ZP24 does have a spi interface.
The transport protocol is proprietary.
For spi we are relying only on DM_SPI.
Signed-off-by: Christophe Ricard
---
README | 4 +
drivers/tpm/Kconfig
I2C protocol is not standardize for TPM 1.2.
TIS prococol is define by the Trusted Computing Group and potentially
available on several TPMs.
tpm_tis_infineon.h header is not generic enough.
Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific
defines/variables to tpm_tis_infineon.c
TPM_TIS_LPC is connected to the LPC bus, not I2C.
Signed-off-by: Christophe Ricard
---
drivers/tpm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 31b35f7..5a75f85 100644
---
In case CONFIG_DM_TPM was set without any TPM chipset configured a fault
was generated (NULL pointer access).
Signed-off-by: Christophe Ricard
---
common/cmd_tpm.c | 2 +-
lib/tpm.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
On Saturday, January 16, 2016 at 05:08:37 PM, Wills Wang wrote:
> On Saturday, January 16, 2016 11:33 PM, Marek Vasut wrote:
> > On Saturday, January 16, 2016 at 02:15:27 PM, Wills Wang wrote:
> >> On Saturday, January 16, 2016 01:26 PM, Marek Vasut wrote:
> >>> On Monday, January 04, 2016 at
On Saturday, January 16, 2016 at 07:13:49 PM, Wills Wang wrote:
> This patch enable work for qca953x SOC.
>
> Signed-off-by: Wills Wang
> ---
>
> Changes in v7:
> - Use CKSEGxADDR instead of KSEGxADDR for qca953x
>
> Changes in v6: None
> Changes in v5: None
> Changes in
On Saturday, January 16, 2016 at 07:13:48 PM, Wills Wang wrote:
> This patch enable work for ar933x SOC.
And it adds DDR code and clock code ... which is missing from the commit
message.
> Signed-off-by: Wills Wang
> ---
[...]
> +void ddr_init(void)
> +{
> + void
Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Signed-off-by: Wills Wang
> ---
>
> Changes in v7:
> - Use KSEG1 address for debug port in ap121
>
> Changes in v6:
> - Convert SZ_XXX into hex in ap121.h
> - Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
>
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.
Signed-off-by: Simon Glass
---
Changes in v4:
- Correct BIOS_CTRL address for
This function is only available for compatibility with old code. Avoid
using it in the uclass.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
This function should not be used by driver-model code, so move it to the
compatibility portion.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add more detail to the function comment
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH9.
Signed-off-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Add a driver-model version of the pci_write_bar32 function so that this is
supported in the new API.
Signed-off-by: Simon Glass
---
Changes in v4:
- Tidy up mentions on control bits in the header file
Changes in v3: None
Changes in v2:
- Rename the last parameter to 'addr'
-
The trace is seldom useful for basic debugging. Allow it to be enabled
separately so that it is easier to see the more important init and error
debug messages.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v4: None
Changes in v3:
- Add a
This is a small series to move the ICH driver over to use the driver model
PCI API. It involves creating PCH drivers which the ICH driver can use to
find out its base address.
At present irq-router is the 'PCH' node in most device tree files. This is
not really correct since the router is just
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.
We have a very simple uclass to support PCHs. Add a few operations, such as
setting
Hi Simon
On Sat, 2016-01-16 at 10:14 -0700, Simon Glass wrote:
> > I wanted to give that patch set a shot but could not figure out
> > against
> > what to get it cleanly applied. Could you reveal its baseline or
> > better
> > yet a git branch ready for testing?
>
> Yes, this plus the next
On Thu, 2016-01-14 at 11:28 -0700, Simon Glass wrote:
> Move this option to Kconfig and clean up the header files. Adjust the
> only
> user (the LCD driver) to work with the new driver.
>
> Signed-off-by: Simon Glass
> ---
>
> configs/colibri_t20_defconfig | 8 +---
>
On Sat, Jan 16, 2016 at 09:45:19PM +0100, Daniel Schwierzeck wrote:
> Hi Tom,
>
> please pull the first bunch of MIPS updates.
>
> There is a possible merge conflict in dts/Makefile due to my patch [1]
> in this PR and Thomas' patch [2] waiting in u-boot-fdt tree.
>
> [1]
CSPLITs for INTERRUPT transactions have to be scheduled in each microframe
following the SSPLIT. INTERRUPT transfers are executed in the next even/
odd microframe depending on the HCCHAR_ODDFRM flag.
As there are no handshakes for INTERRUPT SSPLITs the SSPLIT may have
failed (transport error)
Signed-off-by: Ladislav Michl
Reviewed-by: Tom Rini
---
drivers/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/Makefile b/drivers/Makefile
index 00da40b..1b9f8d6 100644
--- a/drivers/Makefile
+++
The split register setting is used for both SSPLIT and CSPLIT transactions,
the bit for CSPLIT has to be set seperately.
Signed-off-by: Stefan Brüns
---
drivers/usb/host/dwc2.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git
In contrast to non-SPLIT transfers each transaction has to be submitted
as an individual chunk.
The transaction state machine proceeds from SSPLIT to CSPLIT if the ACK
flag is set. CSPLIT has to be repeated while NYET is set.
Signed-off-by: Stefan Brüns
---
A transfer is completed if the XFERCOMP flag is set, irrespective of the
ACK flag. BULK OUT transfers to some HS devices complete without having
the ACK flag set, which signal the devices has responded with an NYET
to the transfer (PING protocol).
The new behaviour matches the Linux kernel minus
Fix two errors in transfer len calculation, move loop invariant code out
of loop.
If xfer_len is equal to CONFIG_DWC2_MAX_TRANSFER_SIZE (or slightly
smaller), the xfer_len will be to large, e.g.:
xfer_len = MAX_TRANSFER_SIZE = 65535
max packet size = 512
=> num_packets = 128
=> IN
Masahiro Yamada (4):
ARM: uniphier: refactor outer cache operation slightly
ARM: uniphier: factor out outer cache sync as a helper function
ARM: uniphier: fix range invalidate for outer cache
ARM: uniphier: set active ways to really enable outer cache
If invalidate operation is invoked against a cache-unaliged region,
the both ends of the region should be flushed, not invalidated.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/cache_uniphier.c | 23 +++
1 file changed, 23
Improve readability without changing the behavior.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/cache_uniphier.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-uniphier/cache_uniphier.c
Avoid repeating the same code.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/cache_uniphier.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-uniphier/cache_uniphier.c
Each way must be unlocked to make it effective.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/cache_uniphier.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-uniphier/cache_uniphier.c
b/arch/arm/mach-uniphier/cache_uniphier.c
Hi Bin,
On 16.01.2016 15:08, Bin Meng wrote:
On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese wrote:
Hi Simon, Hi Bin!
I'm currently busy with porting U-Boot to a Bay Trail board.
Equipped with an Intel Atom E3845 and additionally the
Nuvoton / Winbond W83627DHG Super IO chip.
The umc-proxstream2.c defiens the same macros as in umc-regs.h.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/dram/umc-proxstream2.c | 49 +--
arch/arm/mach-uniphier/dram/umc-regs.h| 26 ++
2 files changed,
These series of patch add support for atheros ath79 based SOCs in u-boot,
at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository
[1] and tested on ar933x and qca953x board.
[1]
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