Re: [U-Boot] [PATCH v3 00/45] Kconfig: Move CONFIG_SPL_..._SUPPORT to Kconfig

[Heiko Schocher]

Hello Simon,

Am 13.09.2016 um 15:08 schrieb Simon Glass:

Hi Heiko,

On 13 September 2016 at 00:02, Heiko Schocher  wrote:

Hello Simon,


Am 13.09.2016 um 07:18 schrieb Simon Glass:


This series moves all the CONFIG_SPL_..._SUPPORT options to Kconfig and
fixes up existing boards to continue to build.

It also adds a few small but useful features to moveconfig.

There is existing work going on in this area, so some of these patches may
be superseded. It has taken me a while to get this building cleanly. But I
have run out of time so want to get this out.

As mentioned on a recent thread [1] there is some confusion about whether
an
option means enabling driver support or media support. Andrew's recent
series seems like a good vehicle to tidy that up. But I hope this series
will make it easier.

NOTE: in the v2 series I have tried to use common things in Kconfig to
reduce the diffs in the defconfig files. This has helped a fair bit. But
it
is very error-prone and time consuming. Also I have had to add some
exceptions (disabling an option in specific board configs). Overall it was
not a pleasant experience :-(

There are a few strange features of this conversion. The main difficulty
is
that some PowerPC boards do things like this in their board config file:

This means that TPL reuses the SPL options. We can't support this in
Kconfig
so I have added a small number of CONFIG_TPL_xxx_SUPPORT options to cope
with this. This made the conversion more painful than it should have been.

A related issue is boards using a common header file and setting options
only
for SPL:

This is not noticed by moveconfig so we have to clean it up manually. Also
there are a few incorrect things where Kconfig options are set with
#define:

Finally, many defconfig files are not ordered correctly, resulting in
larger
patches than we might like. It would be great to have a solution for this,
perhaps with buildman providing a warning. But it might slow down
development.

The series is fully build-tested (for bisectability) and causes no
failures
for the boards that already pass. The following boards fail for me at
present on mainline (which I have not yet looked at):

01: buildman
blackfin:  +   cm-bf527 bf609-ezkit bf537-stamp
   sparc:  +   grsim grsim_leon2 gr_cpci_ax2000 gr_xc3s_1500 gr_ep2s60
   nios2:  +   10m50 3c120
microblaze:  +   microblaze-generic
openrisc:  +   openrisc-generic

[1] https://patchwork.ozlabs.org/patch/661511/

Changes in v3:
- Move SPL_NET_VCI_STRING into the SPL Kconfig file also
- Rebase on master

Changes in v2:
- Add some notes on this option to moveconfig.py
- Improve the commit message and add one for resyncing with savedefconfig
- Add some notes on this option to moveconfig.py
- Add new patch to convert CONFIG_SPL_NET_VCI_STRING
- Drop CONFIG_SPL_PINCTRL_SUPPORT
- Lots of work to make use of common values across multiple boards
- Added a patch to change 'spear' CONFIGs to upper case

Simon Glass (45):
Correct defconfigs using savedefconfig
moveconfig: Add an option to skip prompts
moveconfig: Add an option to commit changes
Kconfig: Move SPL settings into their own file
arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILD
Drop CONFIG_SPL_RAM_SUPPORT
Use separate options for TPL support
Kconfig: spl: Add SPL support options to Kconfig
Kconfig: tpl: Add some TPL support options to Kconfig
Move existing use of CONFIG_SPL_DM to Kconfig
Move existing use of CONFIG_SPL_RSA to Kconfig
spear: Use upper case for CONFIG options
Convert CONFIG_SPL_CRYPTO_SUPPORT to Kconfig
Convert CONFIG_SPL_HASH_SUPPORT to Kconfig
Convert CONFIG_SPL_DMA_SUPPORT to Kconfig
Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to Kconfig
Convert CONFIG_SPL_ENV_SUPPORT to Kconfig
Convert CONFIG_SPL_ETH_SUPPORT to Kconfig
Convert CONFIG_SPL_EXT_SUPPORT to Kconfig
Convert CONFIG_SPL_FAT_SUPPORT to Kconfig
Convert CONFIG_SPL_GPIO_SUPPORT to Kconfig
Convert CONFIG_SPL_I2C_SUPPORT to Kconfig
Convert CONFIG_SPL_LIBCOMMON_SUPPORT to Kconfig
Convert CONFIG_SPL_LIBDISK_SUPPORT to Kconfig
Convert CONFIG_SPL_LIBGENERIC_SUPPORT to Kconfig
Convert CONFIG_SPL_MMC_SUPPORT to Kconfig
Convert CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT to Kconfig
Convert CONFIG_SPL_MTD_SUPPORT to Kconfig
Convert CONFIG_SPL_MUSB_NEW_SUPPORT to Kconfig
Convert CONFIG_SPL_NAND_SUPPORT to Kconfig
Convert CONFIG_SPL_NET_VCI_STRING to Kconfig
Convert CONFIG_SPL_NET_SUPPORT to Kconfig
Convert CONFIG_SPL_NOR_SUPPORT to Kconfig
Convert CONFIG_SPL_ONENAND_SUPPORT to Kconfig
Remove CONFIG_SPL_PINCTRL_SUPPORT
Convert CONFIG_SPL_POWER_SUPPORT to Kconfig
Convert CONFIG_SPL_SATA_SUPPORT to Kconfig
Convert CONFIG_SPL_SERIAL_SUPPORT to Kconfig
Convert CONFIG_SPL_SPI_FLASH_SUPPORT to Kconfig
Convert CONFIG_SPL_SPI_SUPPORT to Kconfig
Convert CONFIG_SPL_USBETH_SUPPORT to Kconfig
Convert 

Re: [U-Boot] [PATCH v2] drivers: usb: fsl-dt-fixup: Fix the dt for multiple USB nodes in single traversal of device tree

[Sriram Dash]

>From: Sriram Dash [mailto:sriram.d...@nxp.com]
>

Hello Marek,

Any comments? 

>For FSL USB node fixup, the dt is walked multiple times for fixing erratum and 
>phy
>type. This patch walks the tree and fixes the node till no more USB nodes are 
>left.
>
>Signed-off-by: Sriram Dash 
>Signed-off-by: Rajesh Bhagat 
>---
> drivers/usb/common/fsl-dt-fixup.c | 108 +-
> 1 file changed, 47 insertions(+), 61 deletions(-)
>
>diff --git a/drivers/usb/common/fsl-dt-fixup.c 
>b/drivers/usb/common/fsl-dt-fixup.c
>index 9c48852..df785a6 100644
>--- a/drivers/usb/common/fsl-dt-fixup.c
>+++ b/drivers/usb/common/fsl-dt-fixup.c
>@@ -54,25 +54,19 @@ static int fdt_usb_get_node_type(void *blob, int
>start_offset,  }
>
> static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
>- const char *phy_type, int start_offset)
>+ const char *phy_type, int node_offset,
>+ const char **node_type)
> {
>   const char *prop_mode = "dr_mode";
>   const char *prop_type = "phy_type";
>-  const char *node_type = NULL;
>-  int node_offset;
>-  int err;
>-
>-  err = fdt_usb_get_node_type(blob, start_offset,
>-  _offset, _type);
>-  if (err < 0)
>-  return err;
>+  int err = 0;
>
>   if (mode) {
>   err = fdt_setprop(blob, node_offset, prop_mode, mode,
> strlen(mode) + 1);
>   if (err < 0)
>   printf("WARNING: could not set %s for %s: %s.\n",
>- prop_mode, node_type, fdt_strerror(err));
>+ prop_mode, *node_type, fdt_strerror(err));
>   }
>
>   if (phy_type) {
>@@ -80,52 +74,48 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const
>char *mode,
> strlen(phy_type) + 1);
>   if (err < 0)
>   printf("WARNING: could not set %s for %s: %s.\n",
>- prop_type, node_type, fdt_strerror(err));
>+ prop_type, *node_type, fdt_strerror(err));
>   }
>
>-  return node_offset;
>+  return err;
> }
>
> static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
>-   const char *controller_type, int start_offset)
>+   const char *controller_type, int node_offset,
>+   const char **node_type)
> {
>-  int node_offset, err;
>-  const char *node_type = NULL;
>+  int err = -1;
>   const char *node_name = NULL;
>
>-  err = fdt_usb_get_node_type(blob, start_offset,
>-  _offset, _type);
>-  if (err < 0)
>-  return err;
>-
>-  if (!strcmp(node_type, FSL_USB2_MPH) || !strcmp(node_type,
>FSL_USB2_DR))
>+  if (!strcmp(*node_type, FSL_USB2_MPH) ||
>+  !strcmp(*node_type, FSL_USB2_DR))
>   node_name = CHIPIDEA_USB2;
>   else
>-  node_name = node_type;
>+  node_name = *node_type;
>   if (strcmp(node_name, controller_type))
>   return err;
>
>   err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
>   if (err < 0) {
>   printf("ERROR: could not set %s for %s: %s.\n",
>- prop_erratum, node_type, fdt_strerror(err));
>+ prop_erratum, *node_type, fdt_strerror(err));
>   }
>
>-  return node_offset;
>+  return err;
> }
>
>-static int fdt_fixup_erratum(int *usb_erratum_off, void *blob,
>+static int fdt_fixup_erratum(int node_offset, void *blob,
>const char *controller_type, char *str,
>-   bool (*has_erratum)(void))
>+   bool (*has_erratum)(void), const char **node_type)
> {
>   char buf[32] = {0};
>
>   snprintf(buf, sizeof(buf), "fsl,usb-erratum-%s", str);
>   if (!has_erratum())
>   return -EINVAL;
>-  *usb_erratum_off = fdt_fixup_usb_erratum(blob, buf, controller_type,
>-   *usb_erratum_off);
>-  if (*usb_erratum_off < 0)
>+  node_offset = fdt_fixup_usb_erratum(blob, buf, controller_type,
>+  node_offset, node_type);
>+  if (node_offset < 0)
>   return -ENOSPC;
>   debug("Adding USB erratum %s\n", str);
>   return 0;
>@@ -135,23 +125,23 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)  {
>   static const char * const modes[] = { "host", "peripheral", "otg" };
>   static const char * const phys[] = { "ulpi", "utmi", "utmi_dual" };
>-  int usb_erratum_a006261_off = -1;
>-  int usb_erratum_a007075_off = -1;
>-  int usb_erratum_a007792_off = -1;
>-  int usb_erratum_a005697_off = -1;
>-  int 

[U-Boot] [PATCH v3] drivers: usb: xhci-fsl: Implement Erratum A-010151 for FSL USB3 controller

[Sriram Dash]

Currently the controller by default enables the Receive Detect feature in P3
mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
detection in P3 mode.
Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
Detect feature is required.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
Changes in v3:
  - Fixing conflicts and repost
Changes in v2:
  - Do Soc ver checking for applying erratum

 drivers/usb/common/fsl-errata.c | 26 ++
 drivers/usb/host/xhci-dwc3.c|  5 +
 drivers/usb/host/xhci-fsl.c |  8 
 include/fsl_usb.h   |  1 +
 include/linux/usb/dwc3.h|  2 ++
 5 files changed, 42 insertions(+)

diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 183bf2b..f2bffba 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -190,4 +190,30 @@ bool has_erratum_a008751(void)
return false;
 }
 
+bool has_erratum_a010151(void)
+{
+   u32 svr = get_svr();
+   u32 soc = SVR_SOC_VER(svr);
+
+   switch (soc) {
+#ifdef CONFIG_ARM64
+   case SVR_LS2080A:
+   case SVR_LS2085A:
+   case SVR_LS1046A:
+   case SVR_LS1012A:
+   return IS_SVR_REV(svr, 1, 0);
+   case SVR_LS1043A:
+   return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+#ifdef CONFIG_LS102XA
+   case SOC_VER_LS1020:
+   case SOC_VER_LS1021:
+   case SOC_VER_LS1022:
+   case SOC_VER_SLS1020:
+   return IS_SVR_REV(svr, 2, 0);
+#endif
+   }
+   return false;
+}
+
 #endif
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 33961cd..adbd9b5 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -97,3 +97,8 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
setbits_le32(_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
GFLADJ_30MHZ(val));
 }
+
+void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val)
+{
+   setbits_le32(_reg->g_usb3pipectl[0], val);
+}
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 0e3e056..9297ced 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -84,6 +84,14 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
/* Change beat burst and outstanding pipelined transfers requests */
fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
 
+   /*
+* A-010151: USB controller to configure USB in P2 mode
+* whenever the Receive Detect feature is required
+*/
+   if (has_erratum_a010151())
+   dwc3_set_rxdetect_power_mode(fsl_xhci->dwc3_reg,
+DWC3_GUSB3PIPECTL_DISRXDETP3);
+
return ret;
 }
 
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index fc72fb9..73235b8 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -95,5 +95,6 @@ bool has_erratum_a007792(void);
 bool has_erratum_a005697(void);
 bool has_erratum_a004477(void);
 bool has_erratum_a008751(void);
+bool has_erratum_a010151(void);
 #endif
 #endif /*_ASM_FSL_USB_H_ */
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 6d1e365..f68cdd2 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -184,6 +184,7 @@ struct dwc3 {   /* 
offset: 0xC100 */
 
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST   (1 << 31)
+#define DWC3_GUSB3PIPECTL_DISRXDETP3   (1 << 28)
 #define DWC3_GUSB3PIPECTL_SUSPHY   (1 << 17)
 
 /* Global TX Fifo Size Register */
@@ -205,5 +206,6 @@ void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
 int dwc3_core_init(struct dwc3 *dwc3_reg);
 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
+void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val);
 #endif
 #endif /* __DWC3_H_ */
-- 
2.1.0

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[U-Boot] [PATCH 6/6] ARM: OMAP5+: Override switch_to_hypervisor function

[Keerthy]

Override the switch_to_hypervisor function to switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for HYP mode.

Based on the work done by Jonathan Bergsagel jbergsa...@ti.com.

Cc: beagleboard-...@googlegroups.com
Signed-off-by: Keerthy 
---
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 24 
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S 
b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 66a3b3d..8ce12c8 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -24,6 +24,30 @@ ENTRY(save_boot_params)
str r0, [r1]
b   save_boot_params_ret
 ENDPROC(save_boot_params)
+
+#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
+ENTRY(switch_to_hypervisor)
+
+/*
+ * Switch to hypervisor mode
+ */
+   adr r0, save_sp
+   str sp, [r0]
+   adr r1, restore_from_hyp
+   ldr r0, =0x102
+   b   omap_smc1
+restore_from_hyp:
+   adr r0, save_sp
+   ldr sp, [r0]
+   MRC p15, 4, R0, c1, c0, 0
+   ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
+   orr r0, r0, r1
+   MCR p15, 4, R0, c1, c0, 0
+   b   switch_to_hypervisor_ret
+save_sp:
+   .word   0x0
+ENDPROC(switch_to_hypervisor)
+#endif
 #endif
 
 ENTRY(omap_smc1)
-- 
1.9.1

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[U-Boot] [PATCH 5/6] ARM: Introduce function to switch to hypervisor mode

[Keerthy]

On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.

Cc: beagleboard-...@googlegroups.com
Signed-off-by: Keerthy 
---
 arch/arm/cpu/armv7/start.S| 21 +
 arch/arm/include/asm/system.h |  4 
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 691e5d3..7eee54b 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  *
@@ -30,11 +31,24 @@
 
.globl  reset
.globl  save_boot_params_ret
+#ifdef CONFIG_ARMV7_LPAE
+   .global switch_to_hypervisor_ret
+#endif
 
 reset:
/* Allow the board to save important registers */
b   save_boot_params
 save_boot_params_ret:
+#ifdef CONFIG_ARMV7_LPAE
+/*
+ * check for Hypervisor support
+ */
+   mrc p15, 0, r0, c0, c1, 1   @ read ID_PFR1
+   and r0, r0, #CPUID_ARM_VIRT_MASK@ mask virtualization bits
+   cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
+   beq switch_to_hypervisor
+switch_to_hypervisor_ret:
+#endif
/*
 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
 * except if in HYP mode already
@@ -103,6 +117,13 @@ ENTRY(save_boot_params)
 ENDPROC(save_boot_params)
.weak   save_boot_params
 
+#ifdef CONFIG_ARMV7_LPAE
+ENTRY(switch_to_hypervisor)
+   b   switch_to_hypervisor_ret
+ENDPROC(switch_to_hypervisor)
+   .weak   switch_to_hypervisor
+#endif
+
 /*
  *
  * cpu_init_cp15
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 7b7b867..c18e1e3 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -223,6 +223,10 @@ void __noreturn psci_system_reset(bool smc);
  */
 void save_boot_params_ret(void);
 
+#ifdef CONFIG_ARMV7_LPAE
+void switch_to_hypervisor_ret(void);
+#endif
+
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
 #ifdef __ARM_ARCH_7A__
-- 
1.9.1

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[U-Boot] [PATCH 4/6] configs: dra7xx_evm_defconfig: Enable LPAE mode

[Keerthy]

Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.

Signed-off-by: Keerthy 
---
 configs/dra7xx_evm_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 64184de..2b368c3 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_ARMV7_LPAE=y
 CONFIG_SPL_STACK_R_ADDR=0x8200
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
-- 
1.9.1

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[U-Boot] [PATCH 3/6] configs: am57xx_evm_defconfig: Enable LPAE mode

[Keerthy]

Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.

Signed-off-by: Keerthy 
---
 configs/am57xx_evm_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index d49129d..7021c11 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_AM57XX_EVM=y
+CONFIG_ARMV7_LPAE=y
 CONFIG_SPL_STACK_R_ADDR=0x8200
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
-- 
1.9.1

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[U-Boot] [PATCH 2/6] omap: Set appropriate cache configuration for LPAE and non-LAPE cases

[Keerthy]

Cache configuration methods is different for LPAE and non-LPAE cases.
Hence the bits and the interpretaion is different for two cases.
In case of non-LPAE mode short descriptor format is used and we need
to set Cache and Buffer bits.

In the case of LPAE the cache configuration happens via MAIR0 lookup.

Signed-off-by: Keerthy 
---
 arch/arm/cpu/armv7/omap-common/omap-cache.c | 25 +++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c 
b/arch/arm/cpu/armv7/omap-common/omap-cache.c
index ee89f1f..b37163a 100644
--- a/arch/arm/cpu/armv7/omap-common/omap-cache.c
+++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c
@@ -17,7 +17,28 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define ARMV7_DCACHE_WRITEBACK  0xe
+/*
+ * Without LPAE short descriptors are used
+ * Set C - Cache Bit3
+ * Set B - Buffer Bit2
+ * The last 2 bits set to 0b10
+ * Do Not set XN bit4
+ * So value is 0xe
+ *
+ * With LPAE cache configuration happens via MAIR0 register
+ * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
+ * 0xFF maps to Cache writeback with Read and Write Allocate set
+ * The bits[1:0] should have the value 0b01 for the first level
+ * descriptor.
+ * So the value is 0xd
+ */
+
+#ifdef CONFIG_ARMV7_LPAE
+#define ARMV7_DCACHE_POLICYDCACHE_WRITEALLOC
+#else
+#define ARMV7_DCACHE_POLICYDCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
+#endif
+
 #define ARMV7_DOMAIN_CLIENT1
 #define ARMV7_DOMAIN_MASK  (0x3 << 0)
 
@@ -38,7 +59,7 @@ void dram_bank_mmu_setup(int bank)
 
debug("%s: bank: %d\n", __func__, bank);
for (i = start; i < end; i++)
-   set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+   set_section_dcache(i, ARMV7_DCACHE_POLICY);
 }
 
 void arm_init_domains(void)
-- 
1.9.1

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[U-Boot] [PATCH 1/6] omap: Remove hardcoding of mmu section shift to 20

[Keerthy]

As of now the mmu section shift is hardcoded to 20 but with LPAE
coming into picture this can be different. Hence replacing 20 with
MMU_SECTION_SHIFT macro.

Signed-off-by: Keerthy 
---
 arch/arm/cpu/armv7/omap-common/omap-cache.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c 
b/arch/arm/cpu/armv7/omap-common/omap-cache.c
index 579bebf..ee89f1f 100644
--- a/arch/arm/cpu/armv7/omap-common/omap-cache.c
+++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c
@@ -32,8 +32,8 @@ void dram_bank_mmu_setup(int bank)
bd_t *bd = gd->bd;
int i;
 
-   u32 start = bd->bi_dram[bank].start >> 20;
-   u32 size = bd->bi_dram[bank].size >> 20;
+   u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+   u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
u32 end = start + size;
 
debug("%s: bank: %d\n", __func__, bank);
-- 
1.9.1

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[U-Boot] [PATCH 0/6] ARM: Introduce function to switch to hypervisor mode and enable LPAE

[Keerthy]

On SoCs like DRA7, OMAP5 one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. 

Patch 1-4 enable LPAE.

Patch 5: Introduces a weak function which can be overridden specific to
SoCs to switch to hypervisor mode.

Patch 6: overrides weak function in patch 1 switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for hypervisor mode on OMAP5 based SoCs.

Tested on AM57XX-EVM, DRA7XX-EVM.

Keerthy (6):
  omap: Remove hardcoding of mmu section shift to 20
  omap: Set appropriate cache configuration for LPAE and non-LAPE cases
  configs: am57xx_evm_defconfig: Enable LPAE mode
  configs: dra7xx_evm_defconfig: Enable LPAE mode
  ARM: Introduce function to switch to hypervisor mode
  ARM: OMAP5+: Override switch_to_hypervisor function

 arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 24 +
 arch/arm/cpu/armv7/omap-common/omap-cache.c| 29 ++
 arch/arm/cpu/armv7/start.S | 21 +++
 arch/arm/include/asm/system.h  |  4 
 configs/am57xx_evm_defconfig   |  1 +
 configs/dra7xx_evm_defconfig   |  1 +
 6 files changed, 76 insertions(+), 4 deletions(-)

-- 
1.9.1

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Re: [U-Boot] [PATCH v3] net: Fix cache misalignment message after network load operations

[Peter.Chubb]

> "Heiko" == Heiko Schocher  writes:

Heiko> Hello Peter, Am 14.09.2016 um 05:49 schrieb
Heiko> peter.ch...@data61.csiro.au:
>> After any operation that downloads a file (e.g., pxe get, or dhcp),
>> the buffer containing the downloaded data is flushed.  This is
>> unnecessary and annoying.  Unnecessary, because the network driver
>> should already have fliushed the cache for the DMAed area, and
>> annoying because it generates a cache misalignment message.
>> 
>> Signed-off-by: Peter Chubb 
>> ---
>> cmd/net.c | 3 --- 1 file changed, 3 deletions(-)

Heiko> I posted a fix for this here:
Heiko> http://patchwork.ozlabs.org/patch/663489/

Heiko> but I did not remove the flush operation ... can we really
Heiko> remove it?
 I believe so -- removing it was suggested by Joe Hershberger.

Heiko> If so, you can add my Acked-by: Heiko Schocher 

OK. thanks.
-- 
Dr Peter Chubb Tel: +61 2 9490 5852  http://ts.data61.csiro.au/
Trustworthy Systems Group   Data61 (formerly NICTA)
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[U-Boot] [PATCH] armv7: LS1021a: enable i-cache in start.S

[Xiaoliang Yang]

Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.

Signed-off-by: Xiaoliang Yang 
---
 arch/arm/cpu/armv7/Makefile   | 2 +-
 arch/arm/cpu/armv7/ls102xa/soc.c  | 4 
 board/freescale/ls1021aqds/README | 6 ++
 board/freescale/ls1021atwr/README | 6 ++
 include/configs/ls1021aqds.h  | 1 -
 include/configs/ls1021atwr.h  | 1 -
 6 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 0d4bfbc..c1eeefd 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o
 obj-y  += cpu.o cp15.o
 obj-y  += syslib.o
 
-ifneq 
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq 
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y  += lowlevel_init.o
 endif
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b1b0c71..659a2d0 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -58,6 +58,10 @@ unsigned int get_soc_major_rev(void)
return major;
 }
 
+void s_init(void)
+{
+}
+
 int arch_soc_init(void)
 {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
diff --git a/board/freescale/ls1021aqds/README 
b/board/freescale/ls1021aqds/README
index c561776..6cf7146 100644
--- a/board/freescale/ls1021aqds/README
+++ b/board/freescale/ls1021aqds/README
@@ -110,3 +110,9 @@ Start Address   End Address Description 
Size
 0x00_7E80_ 0x00_7E80_  IFC - NAND Flash64KB
 0x00_7FB0_ 0x00_7FB0_0FFF  IFC - FPGA  4KB
 0x00_8000_ 0x00__  DRAM1   2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021aqds.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/board/freescale/ls1021atwr/README 
b/board/freescale/ls1021atwr/README
index d2821cb..896a659 100644
--- a/board/freescale/ls1021atwr/README
+++ b/board/freescale/ls1021atwr/README
@@ -107,3 +107,9 @@ Start Address   End Address Description 
Size
 0x00_4000_ 0x00_5FFF_  QSPI512MB
 0x00_6000_ 0x00_67FF_  IFC - NOR Flash 128MB
 0x00_8000_ 0x00__  DRAM1   2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021atwr.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 105702d..88fb1ff 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -18,7 +18,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 
 #define CONFIG_DEEP_SLEEP
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 90ae770..7673ccc 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -18,7 +18,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DEEP_SLEEP
 #ifdef CONFIG_DEEP_SLEEP
-- 
2.1.0.27.g96db324

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[U-Boot] Standalone Application

[Matthew Larkin]

I have found very little online about getting a standalone application up and 
running.
I don't have much experience in general let alone firmware level code.
What are the steps to creating my own standalone application?
I got the hello_world.bin running, but the makefiles are so complex that I 
don't understand why that is the only standalone app compiled when compiling 
U-boot as a whole.
Do I need to modify one of the makefiles?
I have read the readme.standalone, but it doesn't help much for a beginner.
Essentially I want to make my own standalone, example.bin, and have it compiled 
and ran.
Thanks for any insight!
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[U-Boot] [PATCH] efi_loader: Fix crash on 32-bit systems

[Robin Randhawa]

A type mismatch in the efi_allocate_pool boot service flow causes
hazardous memory scribbling on 32-bit systems.

This is efi_allocate_pool's prototype:

static efi_status_t EFIAPI efi_allocate_pool(int pool_type,
unsigned long size,
void **buffer);

Internally, it invokes efi_allocate_pages as follows:

efi_allocate_pages(0, pool_type, (size + 0xfff) >> 12,
(void*)buffer);

This is efi_allocate_pages' prototype:

efi_status_t efi_allocate_pages(int type, int memory_type,
unsigned long pages,
uint64_t *memory);

The problem: efi_allocate_pages does this internally:

*memory = addr;

This fix in efi_allocate_pool uses a transitional uintptr_t cast to
ensure the correct outcome, irrespective of the system's native word
size.

This was observed when bootefi'ing the EFI instance of FreeBSD's first
stage bootstrap (boot1.efi) on a 32-bit ARM platform (Qemu VExpress +
Cortex-a9).

Signed-off-by: Robin Randhawa 
---
 lib/efi_loader/efi_boottime.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index be6f5e8..784891b 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -134,9 +134,11 @@ static efi_status_t EFIAPI efi_allocate_pool(int 
pool_type, unsigned long size,
 void **buffer)
 {
efi_status_t r;
+   efi_physical_addr_t t;
 
EFI_ENTRY("%d, %ld, %p", pool_type, size, buffer);
-   r = efi_allocate_pages(0, pool_type, (size + 0xfff) >> 12, 
(void*)buffer);
+   r = efi_allocate_pages(0, pool_type, (size + 0xfff) >> 12, );
+   *buffer = (void *)(uintptr_t)t;
return EFI_EXIT(r);
 }
 
-- 
2.9.0

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[U-Boot] [PATCH] mmc: cat u8 to u64 to avoid unexpected error

[Haibo Chen]

Suspicious implicit sign extension exist. ext_csd[] is defined
as "u8", capacity is defined as u64, so u8 is promoted to signed
int first int the "|" expersion, then the sign extended to u64.
if the tmp sign value is largeer than 0x7fff, after the sign
extension, the upper bits of the result will all be 1.
Thanks to coverity 

e.g.
u8  data_8;
u64 data_64;

data_8 = 0x80;
data_64 = data_8 << 24; //0x8000
data_64 = ((u64)data_8) << 24;  //0x8000

Signed-off-by: Haibo Chen 
---
 drivers/mmc/mmc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 43ea0bb..c1d1dc6 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1176,10 +1176,10 @@ static int mmc_startup(struct mmc *mmc)
 * ext_csd's capacity is valid if the value is more
 * than 2GB
 */
-   capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
-   | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
-   | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
-   | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
+   capacity = ((u64)ext_csd[EXT_CSD_SEC_CNT]) << 0
+   | ((u64)ext_csd[EXT_CSD_SEC_CNT + 1]) 
<< 8
+   | ((u64)ext_csd[EXT_CSD_SEC_CNT + 2]) 
<< 16
+   | ((u64)ext_csd[EXT_CSD_SEC_CNT + 3]) 
<< 24;
capacity *= MMC_MAX_BLOCK_LEN;
if ((capacity >> 20) > 2 * 1024)
mmc->capacity_user = capacity;
-- 
1.9.1

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[U-Boot] [PATCH 5/5] configs: dra7xx_evm_defconfig: Enable PALMAS options

[Keerthy]

Enable palmas PMIC config options.

Signed-off-by: Keerthy 
---
 configs/dra7xx_evm_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 64184de..882e615 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -43,8 +43,11 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_DM_ETH=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_PALMAS=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
-- 
1.9.1

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[U-Boot] [PATCH 3/5] power: regulator: palmas: Add regulator support

[Keerthy]

The driver provides regulator set/get voltage
enable/disable functions for palmas family of PMICs.

Signed-off-by: Keerthy 
---
 drivers/power/regulator/Kconfig|   8 +
 drivers/power/regulator/Makefile   |   1 +
 drivers/power/regulator/palmas_regulator.c | 460 +
 3 files changed, 469 insertions(+)
 create mode 100644 drivers/power/regulator/palmas_regulator.c

diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 17f22dd..adb710a 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -115,3 +115,11 @@ config REGULATOR_TPS65090
regulators, one for each FET. The standard regulator interface is
supported, but it is only possible to turn the regulators on or off.
There is no voltage/current control.
+
+config DM_REGULATOR_PALMAS
+   bool "Enable driver for PALMAS PMIC regulators"
+   depends on PMIC_PALMAS
+   ---help---
+   This enables implementation of driver-model regulator uclass
+   features for REGULATOR PALMAS and the family of PALMAS PMICs.
+   The driver implements get/set api for: value and enable.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 1590d85..75080d4 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_REGULATOR_RK808) += rk808.o
 obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
 obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
 obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
diff --git a/drivers/power/regulator/palmas_regulator.c 
b/drivers/power/regulator/palmas_regulator.c
new file mode 100644
index 000..6a506fd
--- /dev/null
+++ b/drivers/power/regulator/palmas_regulator.c
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2016
+ * Texas Instruments Incorporated, 
+ *
+ * Keerthy 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#defineREGULATOR_ON0x1
+#defineREGULATOR_OFF   0x0
+
+#defineSMPS_MODE_MASK  0x3
+#defineSMPS_MODE_SHIFT 0x0
+#defineLDO_MODE_MASK   0x1
+#defineLDO_MODE_SHIFT  0x0
+
+static const char palmas_smps_ctrl[][PALMAS_SMPS_NUM] = {
+   {0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 0x3c},
+   {0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38},
+   {0x20, 0x24, 0x2c, 0x30, 0x38},
+};
+
+static const char palmas_smps_volt[][PALMAS_SMPS_NUM] = {
+   {0x23, 0x27, 0x2b, 0x2f, 0x33, 0x37, 0x3b, 0x3c},
+   {0x23, 0x27, 0x2b, 0x2f, 0x33, 0x37, 0x3b},
+   {0x23, 0x27, 0x2f, 0x33, 0x3B}
+};
+
+static const char palmas_ldo_ctrl[][PALMAS_LDO_NUM] = {
+   {0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x62, 0x64},
+   {0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e, 0x60, 0x62, 0x64},
+   {0x50, 0x52, 0x54, 0x5e, 0x62}
+};
+
+static const char palmas_ldo_volt[][PALMAS_LDO_NUM] = {
+   {0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65},
+   {0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65},
+   {0x51, 0x53, 0x55, 0x5f, 0x63}
+};
+
+static int palmas_smps_enable(struct udevice *dev, int op, bool *enable)
+{
+   int ret;
+   uint8_t val;
+   unsigned int adr;
+   struct dm_regulator_uclass_platdata *uc_pdata;
+
+   uc_pdata = dev_get_uclass_platdata(dev);
+   adr = uc_pdata->ctrl_reg;
+
+   ret = dm_i2c_read(dev->parent, adr, , 1);
+   if (ret)
+   return ret;
+
+   if (op == PMIC_OP_GET) {
+   val &= PALMAS_SMPS_STATUS_MASK;
+
+   if (val)
+   *enable = true;
+   else
+   *enable = false;
+
+   return 0;
+   } else if (op == PMIC_OP_SET) {
+   if (*enable)
+   val |= PALMAS_SMPS_MODE_MASK;
+   else
+   val &= ~(PALMAS_SMPS_MODE_MASK);
+
+   dm_i2c_write(dev->parent, adr, , 1);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
+static int palmas_smps_volt2hex(int uV)
+{
+   if (uV > PALMAS_LDO_VOLT_MAX)
+   return -EINVAL;
+
+   if (uV > 165)
+   return (uV - 100) / 2 + 0x6;
+
+   if (uV == 50)
+   return 0x6;
+   else
+   return 0x6 + ((uV - 50) / 1);
+}
+
+static int palmas_smps_hex2volt(int hex, bool range)
+{
+   unsigned int uV = 0;
+
+   if (hex > PALMAS_SMPS_VOLT_MAX_HEX)
+   return -EINVAL;
+
+   if (hex < 0x7)
+   uV = 50;
+   else
+   uV = 50 + (hex - 0x6) * 1;
+
+   if (range)
+   uV *= 

[U-Boot] [PATCH 2/5] power: pmic: Palmas: Add the base pmic support

[Keerthy]

Add support to bind the regulators/child nodes with the pmic.

Signed-off-by: Keerthy 
---
 drivers/power/pmic/Kconfig  |  7 +
 drivers/power/pmic/Makefile |  1 +
 drivers/power/pmic/palmas.c | 77 +
 include/power/palmas.h  | 25 +++
 4 files changed, 110 insertions(+)
 create mode 100644 drivers/power/pmic/palmas.c
 create mode 100644 include/power/palmas.h

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 69f8d51..92931c5 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -135,3 +135,10 @@ config PMIC_TPS65090
FETs and a battery charger. This driver provides register access
only, and you can enable the regulator/charger drivers separately if
required.
+
+config PMIC_PALMAS
+   bool "Enable driver for Texas Instruments PALMAS PMIC"
+   depends on DM_PMIC
+   ---help---
+   The PALMAS is a PMIC containing several LDOs, SMPS.
+   This driver binds the pmic children.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 52b4f71..828c0cf 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PMIC_PM8916) += pm8916.o
 obj-$(CONFIG_PMIC_RK808) += rk808.o
 obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
+obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
 
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
 obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c
new file mode 100644
index 000..3cef2c9
--- /dev/null
+++ b/drivers/power/pmic/palmas.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2016 Texas Instruments Incorporated, 
+ * Keerthy 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+   { .prefix = "ldo", .driver = PALMAS_LDO_DRIVER },
+   { .prefix = "smps", .driver = PALMAS_SMPS_DRIVER },
+   { },
+};
+
+static int palmas_bind(struct udevice *dev)
+{
+   int pmic_node = -1, regulators_node;
+   const void *blob = gd->fdt_blob;
+   int children;
+   int node = dev->of_offset;
+   int subnode, len;
+
+   fdt_for_each_subnode(blob, subnode, node) {
+   const char *name;
+   char *temp;
+
+   name = fdt_get_name(blob, subnode, );
+   temp = strstr(name, "pmic");
+   if (temp) {
+   pmic_node = subnode;
+   break;
+   }
+   }
+
+   if (pmic_node <= 0) {
+   printf("%s: %s pmic subnode not found!", __func__, dev->name);
+   return -ENXIO;
+   }
+
+   regulators_node = fdt_subnode_offset(blob, pmic_node, "regulators");
+
+   if (regulators_node <= 0) {
+   printf("%s: %s reg subnode not found!", __func__, dev->name);
+   return -ENXIO;
+   }
+
+   children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+   if (!children)
+   printf("%s: %s - no child found\n", __func__, dev->name);
+
+   /* Always return success for this device */
+   return 0;
+}
+
+static const struct udevice_id palmas_ids[] = {
+   { .compatible = "ti,tps659038", .data = TPS659038 },
+   { .compatible = "ti,tps65917" , .data = TPS65917 },
+   { }
+};
+
+U_BOOT_DRIVER(pmic_palmas) = {
+   .name = "palmas_pmic",
+   .id = UCLASS_PMIC,
+   .of_match = palmas_ids,
+   .bind = palmas_bind,
+};
diff --git a/include/power/palmas.h b/include/power/palmas.h
new file mode 100644
index 000..bad5a35
--- /dev/null
+++ b/include/power/palmas.h
@@ -0,0 +1,25 @@
+#definePALMAS  0x0
+#define TPS659038  0x1
+#define TPS65917   0x2
+
+/* I2C device address for pmic palmas */
+#define PALMAS_I2C_ADDR(0x12 >> 1)
+#define PALMAS_LDO_NUM 11
+#define PALMAS_SMPS_NUM8
+
+/* Drivers name */
+#define PALMAS_LDO_DRIVER "palmas_ldo"
+#define PALMAS_SMPS_DRIVER"palmas_smps"
+
+#define PALMAS_SMPS_VOLT_MASK  0x7F
+#define PALMAS_SMPS_RANGE_MASK 0x80
+#define PALMAS_SMPS_VOLT_MAX_HEX   0x7F
+#define PALMAS_SMPS_VOLT_MAX   330
+#define PALMAS_SMPS_MODE_MASK  0x3
+#definePALMAS_SMPS_STATUS_MASK 0x30
+
+#define PALMAS_LDO_VOLT_MASK0x3F
+#define PALMAS_LDO_VOLT_MAX_HEX 0x3F
+#define PALMAS_LDO_VOLT_MAX 330
+#define PALMAS_LDO_MODE_MASK   0x1
+#define PALMAS_LDO_STATUS_MASK 0x10
-- 
1.9.1

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[U-Boot] [PATCH 4/5] configs: am57xx_evm_defconfig: Enable PALMAS options

[Keerthy]

Enable palmas PMIC config options.

Signed-off-by: Keerthy 
---
 configs/am57xx_evm_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index d49129d..b277783 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -39,6 +39,9 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR_PALMAS=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
-- 
1.9.1

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[U-Boot] [PATCH 1/5] power: regulator: Add ctrl_reg and volt_reg fields for pmic

[Keerthy]

The ctrl reg contains bit fields to enable and disable regulators,
and volt_reg has the bit fields to configure the voltage values.
The registers are frequently accessed hence make them part
of dm_regulator_uclass_platdata structure.

Signed-off-by: Keerthy 
---
 include/power/regulator.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/power/regulator.h b/include/power/regulator.h
index 9bcd728..57b14a3 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -171,6 +171,8 @@ struct dm_regulator_uclass_platdata {
bool boot_on;
const char *name;
int flags;
+   u8 ctrl_reg;
+   u8 volt_reg;
 };
 
 /* Regulator device operations */
-- 
1.9.1

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[U-Boot] [PATCH 0/5] power: pmic: Add support for Palmas family of PMICs

[Keerthy]

The series adds support for Palmas family of PMICs.
Implements functions to configure regulators. Enable/Disable
Get/Set voltages of regulators.

Supports TPS659038, TPS65917, Palmas.

Tested on TPS659038, TPS65917 using DRA7XX-EVM and AM57XX-EVM. 

Keerthy (5):
  power: regulator: Add ctrl_reg and volt_reg fields for pmic
  power: pmic: Palmas: Add the base pmic support
  power: regulator: palmas: Add regulator support
  configs: am57xx_evm_defconfig: Enable PALMAS options
  configs: dra7xx_evm_defconfig: Enable PALMAS options

 configs/am57xx_evm_defconfig   |   3 +
 configs/dra7xx_evm_defconfig   |   3 +
 drivers/power/pmic/Kconfig |   7 +
 drivers/power/pmic/Makefile|   1 +
 drivers/power/pmic/palmas.c|  77 +
 drivers/power/regulator/Kconfig|   8 +
 drivers/power/regulator/Makefile   |   1 +
 drivers/power/regulator/palmas_regulator.c | 460 +
 include/power/palmas.h |  25 ++
 include/power/regulator.h  |   2 +
 10 files changed, 587 insertions(+)
 create mode 100644 drivers/power/pmic/palmas.c
 create mode 100644 drivers/power/regulator/palmas_regulator.c
 create mode 100644 include/power/palmas.h

-- 
1.9.1

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Re: [U-Boot] [PATCH v3] net: Fix cache misalignment message after network load operations

[Heiko Schocher]

Hello Peter,

Am 14.09.2016 um 05:49 schrieb peter.ch...@data61.csiro.au:

After any operation that downloads a file (e.g., pxe get, or dhcp), the
buffer containing the downloaded data is flushed.  This is unnecessary
and annoying.  Unnecessary, because
the network driver should already have fliushed the cache for the DMAed area,
and annoying because it generates a cache misalignment message.

Signed-off-by: Peter Chubb 
---
  cmd/net.c |3 ---
  1 file changed, 3 deletions(-)


I posted a fix for this here:
http://patchwork.ozlabs.org/patch/663489/

but I did not remove the flush operation ... can we really remove it?

If so, you can add my
Acked-by: Heiko Schocher 

bye,
Heiko


Index: u-boot/cmd/net.c
===
--- u-boot.orig/cmd/net.c   2016-09-07 13:50:46.616156851 +1000
+++ u-boot/cmd/net.c2016-09-07 19:18:18.962450874 +1000
@@ -243,9 +243,6 @@ static int netboot_common(enum proto_t p
return CMD_RET_SUCCESS;
}

-   /* flush cache */
-   flush_cache(load_addr, size);
-
bootstage_mark(BOOTSTAGE_ID_NET_LOADED);

rcode = bootm_maybe_autostart(cmdtp, argv[0]);
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[U-Boot] [PATCH v3] net: Fix cache misalignment message after network load operations

[Peter.Chubb]

After any operation that downloads a file (e.g., pxe get, or dhcp), the
buffer containing the downloaded data is flushed.  This is unnecessary
and annoying.  Unnecessary, because
the network driver should already have fliushed the cache for the DMAed area,
and annoying because it generates a cache misalignment message.

Signed-off-by: Peter Chubb 
---
 cmd/net.c |3 ---
 1 file changed, 3 deletions(-)

Index: u-boot/cmd/net.c
===
--- u-boot.orig/cmd/net.c   2016-09-07 13:50:46.616156851 +1000
+++ u-boot/cmd/net.c2016-09-07 19:18:18.962450874 +1000
@@ -243,9 +243,6 @@ static int netboot_common(enum proto_t p
return CMD_RET_SUCCESS;
}
 
-   /* flush cache */
-   flush_cache(load_addr, size);
-
bootstage_mark(BOOTSTAGE_ID_NET_LOADED);
 
rcode = bootm_maybe_autostart(cmdtp, argv[0]);
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Re: [U-Boot] [PATCH v3 0/2] Detect and reject new ad-hoc CONFIG options

[Simon Glass]

Hi Tom,

On 13 September 2016 at 21:44, Simon Glass  wrote:
> Despite the availability of Kconfig, the number of ad-hoc CONFIG options in
> U-Boot is still at over 8000.
>
> In February 2015 (commit 741e58e0) there were around 8387 ad-hoc CONFIGs.
> As of this patch there are about 8336, only a little fewer.
>
> One problem is that new ones are still being added, admittedly at a slower
> rate. This series adds a Makefile check to detect that and produce a build
> error. This provides immediate feedback that new CONFIG options should go in
> Kconfig.
>
> Changes in v3:
> - Update the whitelist with mainline
> - Fix the match partern to exclude .py files, not anything containing "py"
> - Handle Kconfig files with extensions (e.g. Kconfig.64)
> - Handle CONFIG_SYS_EXTRA_OPTIONS containing lower case
> - Include lower-case letters in the CONFIG match string
> - Write error output to stderr so that buildman shows it
> - Handle Kconfig files with extensions (e.g. Kconfig.64)
> - Handle extra whitespace after 'config' / 'menuconfig'
>
> Changes in v2:
> - Rebase to mainline
> - Fix scripts so that there are no errors
> - Add the 'build-whitelist.sh' script to the tree
>
> Simon Glass (2):
>   Kconfig: Add a whitelist of ad-hoc CONFIG options
>   Makefile: Give a build error if ad-hoc CONFIG options are added
>
>  Makefile |   10 +-
>  scripts/build-whitelist.sh   |   51 +
>  scripts/check-config.sh  |   55 +
>  scripts/config_whitelist.txt | 8420 
> ++
>  4 files changed, 8535 insertions(+), 1 deletion(-)
>  create mode 100755 scripts/build-whitelist.sh
>  create mode 100755 scripts/check-config.sh
>  create mode 100644 scripts/config_whitelist.txt
>
> --
> 2.8.0.rc3.226.g39d4020
>

I build-tested this on top of the SPL series (see u-boot-dm/kconfig-working2):

buildman -b kc4 -fC --step 0 -s
boards.cfg is up to date. Nothing to do.
Summary of 2 commits for 1196 boards (32 threads, 1 job per thread)
01: buildman
  blackfin:  +   cm-bf527 bf609-ezkit bf537-stamp
 sparc:  +   grsim grsim_leon2 gr_cpci_ax2000 gr_xc3s_1500 gr_ep2s60
 nios2:  +   10m50 3c120
microblaze:  +   microblaze-generic
  openrisc:  +   openrisc-generic
48: Makefile: Give a build error if ad-hoc CONFIG options are added
(kc4=74f3ab: -- asc asc2 asc3 b/ sandbox/ test/) u>

There were a number of tweaked needed to get the config checker to
build all boards without error. My previous tested omitted the -C
flag, meaning that it did not reconfigure all of the boards, so
missing loads of problems.

Regards,
Simon
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[U-Boot] [PATCH v3 0/2] Detect and reject new ad-hoc CONFIG options

[Simon Glass]

Despite the availability of Kconfig, the number of ad-hoc CONFIG options in
U-Boot is still at over 8000.

In February 2015 (commit 741e58e0) there were around 8387 ad-hoc CONFIGs.
As of this patch there are about 8336, only a little fewer.

One problem is that new ones are still being added, admittedly at a slower
rate. This series adds a Makefile check to detect that and produce a build
error. This provides immediate feedback that new CONFIG options should go in
Kconfig.

Changes in v3:
- Update the whitelist with mainline
- Fix the match partern to exclude .py files, not anything containing "py"
- Handle Kconfig files with extensions (e.g. Kconfig.64)
- Handle CONFIG_SYS_EXTRA_OPTIONS containing lower case
- Include lower-case letters in the CONFIG match string
- Write error output to stderr so that buildman shows it
- Handle Kconfig files with extensions (e.g. Kconfig.64)
- Handle extra whitespace after 'config' / 'menuconfig'

Changes in v2:
- Rebase to mainline
- Fix scripts so that there are no errors
- Add the 'build-whitelist.sh' script to the tree

Simon Glass (2):
  Kconfig: Add a whitelist of ad-hoc CONFIG options
  Makefile: Give a build error if ad-hoc CONFIG options are added

 Makefile |   10 +-
 scripts/build-whitelist.sh   |   51 +
 scripts/check-config.sh  |   55 +
 scripts/config_whitelist.txt | 8420 ++
 4 files changed, 8535 insertions(+), 1 deletion(-)
 create mode 100755 scripts/build-whitelist.sh
 create mode 100755 scripts/check-config.sh
 create mode 100644 scripts/config_whitelist.txt

-- 
2.8.0.rc3.226.g39d4020

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Re: [U-Boot] [PATCH v2] Fix cache misalignment after network load operations

[Peter.Chubb]

> "Fabio" == Fabio Estevam  writes:

Fabio> On Tue, Sep 13, 2016 at 10:30 PM, 
Fabio> wrote:
>> After any operation that downloads a file (e.g., pxe get, or dhcp),
>> the buffer containing the downloaded data is flushed.  This patch
>> rounds up the flushed size to a cacheline boundary, preventing a
>> cache misalignment message from u-boot.

Fabio> Looks like you missed to update the commit log for v2 as you
Fabio> are no longer flushing the cache :-)

Arrgh.  Thanks for this -- will respin and resubmit.

Fabio> Also, in the Subject line it is always good practice to start
Fabio> with the subsystem name, so something like: net: Remove
Fabio> flush_cache() operation

 Will do.

Peter C
-- 
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Trustworthy Systems Group   Data61 (formerly NICTA)
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[U-Boot] [PATCH v3 2/2] Makefile: Give a build error if ad-hoc CONFIG options are added

[Simon Glass]

New CONFIG options should be added via Kconfig. To help prevent new ad-hoc
CONFIGs from being added, give a build error when these are detected.

Signed-off-by: Simon Glass 
Acked-by: Stephen Warren 
Tested-by: Stephen Warren 
---

Changes in v3:
- Include lower-case letters in the CONFIG match string
- Write error output to stderr so that buildman shows it
- Handle Kconfig files with extensions (e.g. Kconfig.64)
- Handle extra whitespace after 'config' / 'menuconfig'

Changes in v2:
- Rebase to mainline
- Fix scripts so that there are no errors
- Add the 'build-whitelist.sh' script to the tree

 Makefile| 10 -
 scripts/check-config.sh | 55 +
 2 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100755 scripts/check-config.sh

diff --git a/Makefile b/Makefile
index 03329e7..d1ab412 100644
--- a/Makefile
+++ b/Makefile
@@ -740,7 +740,8 @@ DO_STATIC_RELA =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg 
binary_size_check
+ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg \
+   binary_size_check no_new_adhoc_configs_check
 
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
@@ -946,6 +947,13 @@ u-boot.dis:u-boot
 u-boot.cfg:include/config.h FORCE
$(call if_changed,cpp_cfg)
 
+# Check that this build does not use CONFIG options that we don't know about
+# unless they are in Kconfig. All the existing CONFIG options are whitelisted,
+# so new ones should not be added.
+no_new_adhoc_configs_check: u-boot.cfg FORCE
+   $(srctree)/scripts/check-config.sh $< \
+   $(srctree)/scripts/config_whitelist.txt ${srctree} 1>&2
+
 ifdef CONFIG_TPL
 SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
 else
diff --git a/scripts/check-config.sh b/scripts/check-config.sh
new file mode 100755
index 000..28c8fe9
--- /dev/null
+++ b/scripts/check-config.sh
@@ -0,0 +1,55 @@
+#!/bin/sh
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# Check that the u-boot.cfg file provided does not introduce any new
+# ad-hoc CONFIG options
+#
+# You can generate the list of current ad-hoc CONFIG options (those which are
+# not in Kconfig) with this command:
+#
+# export LC_ALL=C LC_COLLATE=C
+# git grep CONFIG_ |tr ' \t' '\n\n' |sed -n 's/^\(CONFIG_[A-Z0-9_]*\).*/\1/p' \
+#  |sort |uniq >scripts/config_whitelist.txt;
+# unset LC_ALL LC_COLLATE
+
+# Usage
+#check-config.sh   
+#
+# For example:
+#   scripts/check-config.sh b/chromebook_link/u-boot.cfg kconfig_whitelist.txt 
.
+
+path="$1"
+whitelist="$2"
+srctree="$3"
+
+# Temporary files
+configs="${path}.configs"
+suspects="${path}.suspects"
+ok="${path}.ok"
+new_adhoc="${path}.adhoc"
+
+export LC_ALL=C
+export LC_COLLATE=C
+
+cat ${path} |sed -n 's/^#define \(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |sort |uniq \
+   >${configs}
+
+comm -23 ${configs} ${whitelist} > ${suspects}
+
+cat `find ${srctree} -name "Kconfig*"` |sed -n \
+   -e 's/^config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+   -e 's/^menuconfig \([A-Za-z0-9_]*\).*$/CONFIG_\1/p' |sort |uniq > ${ok}
+comm -23 ${suspects} ${ok} >${new_adhoc}
+if [ -s ${new_adhoc} ]; then
+   echo "Error: You must add new CONFIG options using Kconfig"
+   echo "The following new ad-hoc CONFIG options were detected:"
+   cat ${new_adhoc}
+   echo
+   echo "Please add these via Kconfig instead. Find a suitable Kconfig"
+   echo "file and add a 'config' or 'menuconfig' option."
+   # Don't delete the temporary files in case they are useful
+   exit 1
+else
+   rm ${suspects} ${ok} ${new_adhoc}
+fi
-- 
2.8.0.rc3.226.g39d4020

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Re: [U-Boot] [PATCH v2] Fix cache misalignment after network load operations

[Fabio Estevam]

On Tue, Sep 13, 2016 at 10:30 PM,   wrote:
> After any operation that downloads a file (e.g., pxe get, or dhcp), the
> buffer containing the downloaded data is flushed.  This patch rounds
> up the flushed size to a cacheline boundary, preventing a cache
> misalignment message from u-boot.

Looks like you missed to update the commit log for v2 as you are no
longer flushing the cache :-)

Also, in the Subject line it is always good practice to start with the
subsystem name, so something like:
net: Remove flush_cache() operation
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Re: [U-Boot] [PATCH 1/2] configs: Resync with savedefconfig

[Masahiro Yamada]

2016-09-13 3:28 GMT+09:00 Stephen Warren :
> On 09/12/2016 08:23 AM, Tom Rini wrote:
>>
>> On Mon, Sep 12, 2016 at 11:24:35AM +0900, Masahiro Yamada wrote:
>>>
>>> 2016-09-10 7:25 GMT+09:00 Stephen Warren :

 On 09/09/2016 03:14 PM, Tom Rini wrote:
>
>
> On Fri, Sep 09, 2016 at 03:06:01PM -0600, Stephen Warren wrote:
>>
>>
>> On 09/09/2016 01:11 PM, Tom Rini wrote:
>>>
>>>
>>> On Fri, Sep 09, 2016 at 01:09:43PM -0600, Stephen Warren wrote:


 On 09/09/2016 01:02 PM, Tom Rini wrote:
>
>
> On Fri, Sep 09, 2016 at 10:21:45AM -0600, Stephen Warren wrote:
>>
>>
>> On 09/08/2016 07:19 PM, Tom Rini wrote:
>>>
>>>
>>> Signed-off-by: Tom Rini 
>
>
> /bin/bash: ess: command not found
>>>
>>>
>>> diff --git a/configs/harmony_defconfig
>>> b/configs/harmony_defconfig
>>
>>
>>
>>> -CONFIG_USE_PRIVATE_LIBGCC=y
>>
>>
>>
>> I assume that's because =y is the default for that now?
>
>
>
> Yes.



>>> diff --git a/configs/p2771--500_defconfig
>>> b/configs/p2771--500_defconfig
>>
>>
>>
>>> -CONFIG_TARGET_P2771_=y
>>
>>
>>
>> I think we need to keep those two. Those two defconfigs are
>> slightly
>> different configurations of U-Boot's p2771- board/target.
>
>
>
> OK, then you need to submit a patch to fix the underlying problem,
> if
> there is one, really.  Keep in mind that what this is, is
> re-running
> savedefconfig for each target.  So if something odd drops out that
> means
> that it wasn't having any effect before.



 I don't believe there is any underlying problem. The Kconfig option
 in question is defined in arch/arm/mach-tegra/tegra186/Kconfig, when
 building for p2771--000 the option makes it into .config just
 fine, and the value is used by board/nvidia/p2771-/Kconfig.
 Isn't this a bug in savedefconfig? I'm CC'ing Masahiro to get some
 insight.
>>>
>>>
>>>
>>> It is the default value then and isn't saved is I believe the answer.
>>
>>
>>
>> I don't think it's the default; nothing selects that option and it
>> has no "default y".
>>
>> Or maybe since the value is inside a choice, and is the only entry
>> that's there, that does make it the default? If so, that seems a
>> little fragile; what if someone comes along and adds a new board
>> into the list, and puts it before the existing entry (e.g. to
>> maintain alphabetical sorting). That would changing the meaning of
>> the current defconfig file if the first entry is picked as default.
>> If so, I'm surprised if nobody has had that issue yet.
>
>
>
> It's all correct and I think we have had this hit once or twice when
> adding or changing the order.  It is a side effect of how Kconfig just
> works.



 I'm not convinced. If I apply your patch, and also the following:

> diff --git a/arch/arm/mach-tegra/tegra186/Kconfig
> b/arch/arm/mach-tegra/tegra186/Kconfig
> index 97cf23f31f80..05f691ed3ede 100644
> --- a/arch/arm/mach-tegra/tegra186/Kconfig
> +++ b/arch/arm/mach-tegra/tegra186/Kconfig
> @@ -7,6 +7,14 @@ if TEGRA186
>  choice
> prompt "Tegra186 board select"
>
> +config TARGET_E_1234
> +   bool "NVIDIA Tegra186 E-1234 board"
> +   help
> + P2771- is a P3310 CPU board married to a P2597 I/O board.
> The
> + combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
> + micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two
> GPIO
> + expansion headers.
> +
>  config TARGET_P2771_
> bool "NVIDIA Tegra186 P2771- board"
> help



 ... then I get a build failure for p2771--000_defconfig since
 .config
 ends up containing CONFIG_TARGET_E_1234 rather than
 CONFIG_TARGET_P2771_. I think we want to avoid that don't we? If we
 don't, savedefconfig in the face of choice options seems rather too
 fragile,
 or we need to force people to update *_defconfig any time any Kconfig
 choice
 is edited.
>>>
>>>
>>>
>>> We have discussed this problem several times before.
>>>
>>>   - The first entry in a "choice" is the default, unless otherwise
>>> specified.
>>>   - "make savedefconfig" drops all the defaults to create a minimum
>>> set of configs.
>>>
>>> So, we need to be careful when 

[U-Boot] [PATCH 1/3] sunxi: Add mmc0 card detect pin for Sinlinx SinA33

[Chen-Yu Tsai]

Sinlinx SinA33 uses PB4 for mmc0 card detect.

Signed-off-by: Chen-Yu Tsai 
---
 configs/Sinlinx_SinA33_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 013c35e1a835..77eb05bf251a 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN8I_A33=y
 CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
+CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-- 
2.9.3

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[U-Boot] [PATCH 2/3] sunxi: Enable USB host support for Sinlinx SinA33

[Chen-Yu Tsai]

Sinlinx SinA33 has 1 USB host port. Enable EHCI_HCD support for it.
Also enable USB mass storage support so we can access USB sticks.

Signed-off-by: Chen-Yu Tsai 
---
 configs/Sinlinx_SinA33_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 77eb05bf251a..673f3210a1b5 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -9,4 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_USB_EHCI_HCD=y
-- 
2.9.3

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[U-Boot] [PATCH 3/3] sunxi: Enable USB gadget support for Sinlinx SinA33

[Chen-Yu Tsai]

Sinlinx SinA33 has a USB OTG port, but VBUS is controlled manually from
a jumper pad.

Enable OTG in gadget mode, as well as the download gadget and related
functions.

Signed-off-by: Chen-Yu Tsai 
---
 configs/Sinlinx_SinA33_defconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 673f3210a1b5..a3a234fb875a 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -4,11 +4,19 @@ CONFIG_MACH_SUN8I_A33=y
 CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
 CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_USB0_ID_DET="PH8"
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
-- 
2.9.3

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Re: [U-Boot] [Patch v6 5/9] armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r

[york sun]

On 09/08/2016 11:12 PM, Q.Y. Gong wrote:
>
> I can boot it up with this patch set on star server: LS2085ARDB-1.
> I also tested the single patch and no issue.
>
> This is my U-Boot command:
> =>tftp 8200 b52263/ls2080ardb/u-boot-with-spl.bin;nand erase 8 
> 18;nand write 8200 8 12;qixis_reset nand
>

It looks like I have a bad combination of toolchain and code. First I 
have to revert commit "ARM: Rework and correct barrier definitions", 
then I can make it boot with older toolchains

Linaro GCC 4.9-2015.03, and Linaro GCC 4.9-2014.09

But I cannot use a newer toolchain with the same code, for example 
gcc-linaro-4.9-2016.02, gcc-linaro-5.3-2016.02. What's your toolchain 
version?

York

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[U-Boot] [PATCH v1 3/3] arm: mvebu: NAND support for DB-88F6820-AMC

[Chris Packham]

Enable the NAND interface on this board.

Signed-off-by: Chris Packham 
---

 arch/arm/dts/armada-385-amc.dts  | 8 
 configs/db-88f6820-amc_defconfig | 2 ++
 include/configs/db-88f6820-amc.h | 4 
 3 files changed, 14 insertions(+)

diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts
index 858138a3376b..a5a8a7f186db 100644
--- a/arch/arm/dts/armada-385-amc.dts
+++ b/arch/arm/dts/armada-385-amc.dts
@@ -120,6 +120,14 @@
reg = <0>;
};
};
+
+   flash@d {
+   status = "okay";
+   num-cs = <1>;
+   marvell,nand-keep-config;
+   marvell,nand-enable-arbiter;
+   nand-on-flash-bbt;
+   };
};
 
pcie-controller {
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index 74794fed4766..9a6cf4767d92 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL=y
 CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -23,6 +24,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_NAND_PXA3XX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
index b9cb243e402d..97c51c91d9bb 100644
--- a/include/configs/db-88f6820-amc.h
+++ b/include/configs/db-88f6820-amc.h
@@ -68,6 +68,10 @@
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 
+/* NAND */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
 #define CONFIG_SYS_CONSOLE_INFO_QUIET  /* don't print console @ startup */
 #define CONFIG_SYS_ALT_MEMTEST
 
-- 
2.9.2.518.ged577c6.dirty

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[U-Boot] [PATCH v1 2/3] arm: mvebu: add DB-88F6820-AMC board

[Chris Packham]

This board is a plug in card for Marvell's switch system development
kits. Form-factor aside it is similar to the DB-88F6820-GP with the
following differences.
- TCLK is 200MHz
- SPI1 is used
- No SATA
- No MMC
- NAND flash

Signed-off-by: Chris Packham 
---
I've used my work email address for the MAINTAINERS entry. Mainly
because it gives a better chance at finding someone else to contact
rather than a random gmail address.

I've also left the copyright assignments to Stefan and Gregory since the
code was derived from the -GP board.

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/armada-385-amc.dts   | 155 ++
 arch/arm/mach-mvebu/Kconfig   |   7 ++
 board/Marvell/db-88f6820-amc/MAINTAINERS  |   6 +
 board/Marvell/db-88f6820-amc/Makefile |   7 ++
 board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 129 +
 board/Marvell/db-88f6820-amc/kwbimage.cfg |  12 ++
 configs/db-88f6820-amc_defconfig  |  38 +++
 include/configs/db-88f6820-amc.h  | 130 +
 9 files changed, 485 insertions(+)
 create mode 100644 arch/arm/dts/armada-385-amc.dts
 create mode 100644 board/Marvell/db-88f6820-amc/MAINTAINERS
 create mode 100644 board/Marvell/db-88f6820-amc/Makefile
 create mode 100644 board/Marvell/db-88f6820-amc/db-88f6820-amc.c
 create mode 100644 board/Marvell/db-88f6820-amc/kwbimage.cfg
 create mode 100644 configs/db-88f6820-amc_defconfig
 create mode 100644 include/configs/db-88f6820-amc.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a4ab06964e20..78a8416e4686 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=   \
armada-375-db.dtb   \
armada-388-clearfog.dtb \
armada-388-gp.dtb   \
+   armada-385-amc.dtb  \
armada-xp-gp.dtb\
armada-xp-maxbcm.dtb\
armada-xp-synology-ds414.dtb\
diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts
new file mode 100644
index ..858138a3376b
--- /dev/null
+++ b/arch/arm/dts/armada-385-amc.dts
@@ -0,0 +1,155 @@
+/*
+ * Device Tree file for Marvell Armada 385 development board
+ * (DB-88F6820-AMC)
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include 
+
+/ {
+   model = "Marvell Armada 385 AMC";
+   compatible = "marvell,a385-amc", "marvell,armada385", 
"marvell,armada380";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   spi1 = 
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x 0x8000>; /* 2 GB */
+   };
+
+   soc {
+   ranges = ;
+
+   internal-regs {
+   i2c@11000 {
+   pinctrl-names = "default";
+   

[U-Boot] [PATCH v1 1/3] arm: mvebu: create generic 88F6820 config option

[Chris Packham]

88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP
board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which
selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards
using the 88F6820 can be added.

Signed-off-by: Chris Packham 
---

 arch/arm/mach-mvebu/Kconfig   | 4 ++--
 arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 220886aa592a..06820a5e4f2c 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -21,7 +21,7 @@ config MV78460
bool
select ARMADA_XP
 
-config DB_88F6820_GP
+config 88F6820
bool
select ARMADA_38X
 
@@ -39,7 +39,7 @@ config TARGET_DB_88F6720
 
 config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
-   select DB_88F6820_GP
+   select 88F6820
 
 config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c 
b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
index 49d704a36230..cc3e5e23c0dd 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
@@ -45,7 +45,7 @@ u32 g_dev_id = -1;
 
 u32 mv_board_id_get(void)
 {
-#if defined(CONFIG_DB_88F6820_GP)
+#if defined(CONFIG_TARGET_DB_88F6820_GP)
return DB_GP_68XX_ID;
 #else
/*
-- 
2.9.2.518.ged577c6.dirty

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[U-Boot] [PATCH v2] rtl8169: fix cache misalignment message on transmit.

[Peter.Chubb]

The call to flush cache on the transmit buffer was misplaced (for very
short packets) and asked to flush less than a cacheline.

Move the flush cache call to after a short packet has been padded
to minimum length (so the padding is flushed too), and round the size
up to a cacheline.

Signed-off-by: Peter Chubb 
Acked-by: Joe Hershberger 
---
 drivers/net/rtl8169.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 1cc0b40..a3f4423 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -629,11 +629,12 @@ static int rtl_send_common(pci_dev_t dev, unsigned long 
dev_iobase,
/* point to the current txb incase multiple tx_rings are used */
ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
memcpy(ptxb, (char *)packet, (int)length);
-   rtl_flush_buffer(ptxb, length);
 
while (len < ETH_ZLEN)
ptxb[len++] = '\0';
 
+   rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
+
tpc->TxDescArray[entry].buf_Haddr = 0;
 #ifdef CONFIG_DM_ETH
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
-- 
2.9.3
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[U-Boot] [PATCH v2] Fix cache misalignment after network load operations

[Peter.Chubb]

After any operation that downloads a file (e.g., pxe get, or dhcp), the
buffer containing the downloaded data is flushed.  This patch rounds
up the flushed size to a cacheline boundary, preventing a cache
misalignment message from u-boot.

Signed-off-by: Peter Chubb 
---
 cmd/net.c |3 ---
 1 file changed, 3 deletions(-)

Index: u-boot/cmd/net.c
===
--- u-boot.orig/cmd/net.c   2016-09-07 13:50:46.616156851 +1000
+++ u-boot/cmd/net.c2016-09-07 19:18:18.962450874 +1000
@@ -243,9 +243,6 @@ static int netboot_common(enum proto_t p
return CMD_RET_SUCCESS;
}
 
-   /* flush cache */
-   flush_cache(load_addr, size);
-
bootstage_mark(BOOTSTAGE_ID_NET_LOADED);
 
rcode = bootm_maybe_autostart(cmdtp, argv[0]);
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Re: [U-Boot] [PATCH 21/21] arm: imx: add i.MX6ULL 14x14 EVK board support

[Peng Fan]

Hi Jagan,
On Wed, Sep 14, 2016 at 12:41:17AM +0530, Jagan Teki wrote:
>Hi Peng,
>
>On Thu, Sep 8, 2016 at 7:05 AM, Peng Fan  wrote:
>> Hi Jagan,
>> On Wed, Sep 07, 2016 at 08:21:07PM +0530, Jagan Teki wrote:
>>>On Thu, Aug 11, 2016 at 11:32 AM, Peng Fan  wrote:
 Add i.MX6ULL EVK board support:
 Add device tree file, which is copied from NXP Linux.
 Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
 The uart iomux settings are still keeped in board file.

 Boot Log:
 U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)

 CPU:   Freescale i.MX6ULL rev1.0 at 396MHz
 CPU:   Commercial temperature grade (0C to 95C) at 15C
 Reset cause: POR
 Model: Freescale i.MX6 ULL 14x14 EVK Board
 Board: MX6ULL 14x14 EVK
 DRAM:  512 MiB
 MMC:   initialized IMX pinctrl driver
 FSL_SDHC: 0, FSL_SDHC: 1
>>>
>>>
>>>
 diff --git a/board/freescale/mx6ullevk/mx6ullevk.c 
 b/board/freescale/mx6ullevk/mx6ullevk.c
 new file mode 100644
 index 000..489bf21
 --- /dev/null
 +++ b/board/freescale/mx6ullevk/mx6ullevk.c
 @@ -0,0 +1,99 @@
 +/*
 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
 + *
 + * SPDX-License-Identifier:GPL-2.0+
 + */
 +
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +#include 
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
 +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
 +   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
 +   PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 +
 +int dram_init(void)
 +{
 +   gd->ram_size = imx_ddr_size();
>
>Is this common call for all imx soc's to get the ddr size? because I
>observed incorrect size when I call this function.
>
 +
 +   return 0;
 +}
 +
 +static iomux_v3_cfg_t const uart1_pads[] = {
 +   MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 +   MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 +};
 +
 +static void setup_iomux_uart(void)
 +{
 +   imx_iomux_v3_setup_multiple_pads(uart1_pads, 
 ARRAY_SIZE(uart1_pads));
 +}
 +
 +int board_mmc_get_env_dev(int devno)
 +{
 +   return devno;
 +}
 +
 +int mmc_map_to_kernel_blk(int devno)
 +{
 +   return devno;
 +}
 +
 +int board_early_init_f(void)
 +{
 +   setup_iomux_uart();
>>>
>>>Don't we need iomux settings for sdhc? I guess pinctrl for SD not
>>>supporting now.
>>
>> The pinctrl driver will configure the pinmux, no need to add iomux settings
>> in board file. In this patchset, I enabled PINCTRL, DM_MMC, DM_GPIO and etc.
>
>Yeah, but the uart pinx mux are still in board file right?

I did not enable DM UART. Since lowlevel debug not implemented for i.MX6,
I need to initialize uart as early as possible. When lowlevel debug
implemented, we could switch to use pinctrl to initialze uart pinmux and
use DM UART.
So now I keep the uart pinmux settings in board file.

Regards,
Peng.
>
>-- 
>Jagan Teki
>Free Software Engineer | www.openedev.com
>U-Boot, Linux | Upstream Maintainer
>Hyderabad, India.
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[U-Boot] [PATCH] armv8: fsl-layerscape: Fix "cpu status" command

[York Sun]

The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.

Tested on LS2080ARDB and LS1043ARDB.

Signed-off-by: York Sun 
---

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 21 +
 arch/arm/cpu/armv8/fsl-layerscape/mp.c| 16 
 arch/arm/include/asm/arch-fsl-layerscape/mp.h |  1 +
 3 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index e12b773..e69268a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -201,6 +201,27 @@ static inline u32 initiator_type(u32 cluster, int init_id)
return 0;
 }
 
+u32 cpu_pos_mask(void)
+{
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   int i = 0;
+   u32 cluster, type, mask = 0;
+
+   do {
+   int j;
+
+   cluster = gur_in32(>tp_cluster[i].lower);
+   for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+   type = initiator_type(cluster, j);
+   if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
+   mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
+   }
+   i++;
+   } while ((cluster & TP_CLUSTER_EOC) == 0x0);
+
+   return mask;
+}
+
 u32 cpu_mask(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c 
b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index df7ffb8..f607c39 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -104,6 +104,11 @@ int is_core_valid(unsigned int core)
return !!((1 << core) & cpu_mask());
 }
 
+static int is_pos_valid(unsigned int pos)
+{
+   return !!((1 << pos) & cpu_pos_mask());
+}
+
 int is_core_online(u64 cpu_id)
 {
u64 *table;
@@ -126,9 +131,9 @@ int cpu_disable(int nr)
return 0;
 }
 
-int core_to_pos(int nr)
+static int core_to_pos(int nr)
 {
-   u32 cores = cpu_mask();
+   u32 cores = cpu_pos_mask();
int i, count = 0;
 
if (nr == 0) {
@@ -139,14 +144,17 @@ int core_to_pos(int nr)
}
 
for (i = 1; i < 32; i++) {
-   if (is_core_valid(i)) {
+   if (is_pos_valid(i)) {
count++;
if (count == nr)
break;
}
}
 
-   return count;
+   if (count != nr)
+   return -1;
+
+   return i;
 }
 
 int cpu_status(int nr)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h 
b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index e46e076..f7306ff 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -34,5 +34,6 @@ void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
 void secondary_boot_func(void);
 int is_core_online(u64 cpu_id);
+u32 cpu_pos_mask(void);
 #endif
 #endif /* _FSL_LAYERSCAPE_MP_H */
-- 
2.7.4

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[U-Boot] [PATCH v2 1/5] test/fs: Restructure file path specification to allow some flexibility

[Stefan Brüns]

Instead of providing the full path, specify directory and filename
separately. This allows to specify intermediate directories, required
for some additional tests.

Signed-off-by: Stefan Brüns 
---
 test/fs/fs-test.sh | 58 +-
 1 file changed, 22 insertions(+), 36 deletions(-)

diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index 93679cb..f95350b 100755
--- a/test/fs/fs-test.sh
+++ b/test/fs/fs-test.sh
@@ -135,22 +135,6 @@ function create_image() {
fi
 }
 
-# 1st parameter is the FS type: fat/ext4
-# 2nd parameter is the name of small file
-# Returns filename which can be used for fat or ext4 for writing
-function fname_for_write() {
-   case $1 in
-   ext4)
-   # ext4 needs absolute path name of file
-   echo /${2}.w
-   ;;
-
-   *)
-   echo ${2}.w
-   ;;
-   esac
-}
-
 # 1st parameter is image file
 # 2nd parameter is file system type - fat/ext4
 # 3rd parameter is name of small file
@@ -166,11 +150,14 @@ function test_image() {
 
case "$2" in
fat)
+   FPATH=""
PREFIX="fat"
WRITE="write"
;;
 
ext4)
+   # ext4 needs absolute path
+   FPATH="/"
PREFIX="ext4"
WRITE="write"
;;
@@ -205,16 +192,15 @@ function test_image() {
 
esac
 
-   if [ -z "$6" ]; then
-   FILE_WRITE=`fname_for_write $2 $3`
-   FILE_SMALL=$3
-   FILE_BIG=$4
-   else
-   FILE_WRITE=$6/`fname_for_write $2 $3`
-   FILE_SMALL=$6/$3
-   FILE_BIG=$6/$4
+   # sb always uses full path to mointpoint, irrespective of filesystem
+   if [ "$5" = "sb" ]; then
+   FPATH=${6}/
fi
 
+   FILE_WRITE=${3}.w
+   FILE_SMALL=$3
+   FILE_BIG=$4
+
# In u-boot commands,  stands for host or hostfs
# hostfs maps to the host fs.
# host maps to the "sb bind" that we do
@@ -230,13 +216,13 @@ ${PREFIX}ls host${SUFFIX} $6
 # sb size hostfs - $3 for hostfs commands.
 # 1MB is 0x0010 
 # Test Case 2 - size of small file
-${PREFIX}size host${SUFFIX} $FILE_SMALL
+${PREFIX}size host${SUFFIX} ${FPATH}$FILE_SMALL
 printenv filesize
 setenv filesize
 
 # 2.5GB (1024*1024*2500) is 0x9C40 
 # Test Case 3 - size of big file
-${PREFIX}size host${SUFFIX} $FILE_BIG
+${PREFIX}size host${SUFFIX} ${FPATH}$FILE_BIG
 printenv filesize
 setenv filesize
 
@@ -245,14 +231,14 @@ setenv filesize
 # Last two parameters are size and offset.
 
 # Test Case 4a - Read full 1MB of small file
-${PREFIX}load host${SUFFIX} $addr $FILE_SMALL
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_SMALL
 printenv filesize
 # Test Case 4b - Read full 1MB of small file
 md5sum $addr \$filesize
 setenv filesize
 
 # Test Case 5a - First 1MB of big file
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x0
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x0
 printenv filesize
 # Test Case 5b - First 1MB of big file
 md5sum $addr \$filesize
@@ -260,7 +246,7 @@ setenv filesize
 
 # fails for ext as no offset support
 # Test Case 6a - Last 1MB of big file
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x9C30
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x9C30
 printenv filesize
 # Test Case 6b - Last 1MB of big file
 md5sum $addr \$filesize
@@ -268,7 +254,7 @@ setenv filesize
 
 # fails for ext as no offset support
 # Test Case 7a - One from the last 1MB chunk of 2GB
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF0
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x7FF0
 printenv filesize
 # Test Case 7b - One from the last 1MB chunk of 2GB
 md5sum $addr \$filesize
@@ -276,7 +262,7 @@ setenv filesize
 
 # fails for ext as no offset support
 # Test Case 8a - One from the start 1MB chunk from 2GB
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x8000
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x8000
 printenv filesize
 # Test Case 8b - One from the start 1MB chunk from 2GB
 md5sum $addr \$filesize
@@ -284,7 +270,7 @@ setenv filesize
 
 # fails for ext as no offset support
 # Test Case 9a - One 1MB chunk crossing the 2GB boundary
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF8
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x7FF8
 printenv filesize
 # Test Case 9b - One 1MB chunk crossing the 2GB boundary
 md5sum $addr \$filesize
@@ -292,17 +278,17 @@ setenv filesize
 
 # Generic failure case
 # Test Case 10 - 2MB chunk from the last 1MB of big file
-${PREFIX}load host${SUFFIX} $addr $FILE_BIG 0x0020 0x9C30
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG 0x0020 0x9C30
 printenv filesize
 #
 
 # Read 1MB from 

[U-Boot] [PATCH v2 3/5] test/fs: strip noise from filesystem code prior to checking results

[Stefan Brüns]

ext4 and fat code emit some diagnostic messages during command execution.
These additional lines force a match window size which strictly is not
necessary.

Signed-off-by: Stefan Brüns 
---
 test/fs/fs-test.sh | 26 +++---
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index 9615898..b9c2306 100755
--- a/test/fs/fs-test.sh
+++ b/test/fs/fs-test.sh
@@ -386,7 +386,7 @@ check_md5() {
# md5sum in u-boot has output of form:
# md5 for 0108 ... 0117 ==> 
# the 7th field is the actual md5
-   md5_src=`grep -A3 "$1" "$2" | grep "md5 for" | tr -d '\r'`
+   md5_src=`grep -A2 "$1" "$2" | grep "md5 for" | tr -d '\r'`
md5_src=($md5_src)
md5_src=${md5_src[6]}
 
@@ -431,45 +431,44 @@ function check_results() {
pass_fail "TC3: size of $4"
 
# Check read full mb of 1MB.file
-   grep -A6 "Test Case 4a " "$1" | grep -q "filesize=10"
+   grep -A4 "Test Case 4a " "$1" | grep -q "filesize=10"
pass_fail "TC4: load of $3 size"
check_md5 "Test Case 4b " "$1" "$2" 1 "TC4: load from $3"
 
# Check first mb of 2.5GB.file
-   grep -A6 "Test Case 5a " "$1" | grep -q "filesize=10"
+   grep -A4 "Test Case 5a " "$1" | grep -q "filesize=10"
pass_fail "TC5: load of 1st MB from $4 size"
check_md5 "Test Case 5b " "$1" "$2" 2 "TC5: load of 1st MB from $4"
 
# Check last mb of 2.5GB.file
-   grep -A6 "Test Case 6a " "$1" | grep -q "filesize=10"
+   grep -A4 "Test Case 6a " "$1" | grep -q "filesize=10"
pass_fail "TC6: load of last MB from $4 size"
check_md5 "Test Case 6b " "$1" "$2" 3 "TC6: load of last MB from $4"
 
# Check last 1mb chunk of 2gb from 2.5GB file
-   grep -A6 "Test Case 7a " "$1" | grep -q "filesize=10"
+   grep -A4 "Test Case 7a " "$1" | grep -q "filesize=10"
pass_fail "TC7: load of last 1mb chunk of 2GB from $4 size"
check_md5 "Test Case 7b " "$1" "$2" 4 \
"TC7: load of last 1mb chunk of 2GB from $4"
 
# Check first 1mb chunk after 2gb from 2.5GB file
-   grep -A6 "Test Case 8a " "$1" | grep -q "filesize=10"
+   grep -A4 "Test Case 8a " "$1" | grep -q "filesize=10"
pass_fail "TC8: load 1st MB chunk after 2GB from $4 size"
check_md5 "Test Case 8b " "$1" "$2" 5 \
"TC8: load 1st MB chunk after 2GB from $4"
 
# Check 1mb chunk crossing the 2gb boundary from 2.5GB file
-   grep -A6 "Test Case 9a " "$1" | grep -q "filesize=10"
+   grep -A4 "Test Case 9a " "$1" | grep -q "filesize=10"
pass_fail "TC9: load 1MB chunk crossing 2GB boundary from $4 size"
check_md5 "Test Case 9b " "$1" "$2" 6 \
"TC9: load 1MB chunk crossing 2GB boundary from $4"
 
# Check 2mb chunk from the last 1MB of 2.5GB file loads 1MB
-   grep -A6 "Test Case 10 " "$1" | grep -q "filesize=10"
+   grep -A5 "Test Case 10 " "$1" | grep -q "filesize=10"
pass_fail "TC10: load 2MB from the last 1MB of $4 loads 1MB"
 
# Check 1mb chunk write
-   grep -A3 "Test Case 11a " "$1" | \
-   egrep -q '1048576 bytes written|update journal'
+   grep -A2 "Test Case 11a " "$1" | grep -q '1048576 bytes written'
pass_fail "TC11: 1MB write to $3.w - write succeeded"
check_md5 "Test Case 11b " "$1" "$2" 1 \
"TC11: 1MB write to $3.w - content verified"
@@ -486,7 +485,12 @@ function test_fs_nonfs() {
OUT_FILE="${OUT}.$1.${fs}.out"
test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \
> ${OUT_FILE} 2>&1
-   check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE
+   # strip out noise from fs code
+   grep -v -e "File System is consistent\|update journal finished" \
+   -e "reading .*\.file\|writing .*\.file.w" \
+   < ${OUT_FILE} > ${OUT_FILE}_clean
+   check_results ${OUT_FILE}_clean $MD5_FILE_FS $SMALL_FILE \
+   $BIG_FILE
TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
TOTAL_PASS=$((TOTAL_PASS + PASS))
echo "Summary: PASS: $PASS FAIL: $FAIL"
-- 
2.10.0

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[U-Boot] [PATCH v2 5/5] test/fs: Check writes using "." (same dir) relative path

[Stefan Brüns]

/ and /./ should reference the same file.

Signed-off-by: Stefan Brüns 
---
 test/fs/fs-test.sh | 29 -
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index 69abdab..520344b 100755
--- a/test/fs/fs-test.sh
+++ b/test/fs/fs-test.sh
@@ -299,6 +299,23 @@ setenv filesize
 # The write should fail, but the lookup should work
 # Test Case 12 - Check directory traversal
 ${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}. 0x10
+
+# Read 1MB from small file
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_SMALL
+# Write it via "same directory", i.e. "." dirent
+# Test Case 13a - Check directory traversal
+${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}./${FILE_WRITE}2 \$filesize
+mw.b $addr 00 100
+${PREFIX}load host${SUFFIX} $addr ${FPATH}./${FILE_WRITE}2
+# Test Case 13b - Check md5 of written to is same as the one read from
+md5sum $addr \$filesize
+setenv filesize
+mw.b $addr 00 100
+${PREFIX}load host${SUFFIX} $addr ${FPATH}${FILE_WRITE}2
+# Test Case 13c - Check md5 of written to is same as the one read from
+md5sum $addr \$filesize
+setenv filesize
+#
 reset
 
 EOF
@@ -335,9 +352,10 @@ function create_files() {
&> /dev/null
fi
 
-   # Delete the small file which possibly is written as part of a
+   # Delete the small file copies which possibly are written as part of a
# previous test.
sudo rm -f "${MB1}.w"
+   sudo rm -f "${MB1}.w2"
 
# Generate the md5sums of reads that we will test against small file
dd if="${MB1}" bs=1M skip=0 count=1 2> /dev/null | md5sum > "$2"
@@ -482,6 +500,15 @@ function check_results() {
# Check lookup of 'dot' directory
grep -A4 "Test Case 12 " "$1" | grep -q 'Unable to write file'
pass_fail "TC12: 1MB write to . - write denied"
+
+   # Check directory traversal
+   grep -A2 "Test Case 13a " "$1" | grep -q '1048576 bytes written'
+   pass_fail "TC13: 1MB write to ./$3.w2 - write succeeded"
+   check_md5 "Test Case 13b " "$1" "$2" 1 \
+   "TC13: 1MB read from ./$3.w2 - content verified"
+   check_md5 "Test Case 13c " "$1" "$2" 1 \
+   "TC13: 1MB read from $3.w2 - content verified"
+
echo "** End $1"
 }
 
-- 
2.10.0

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[U-Boot] [PATCH v2 4/5] test/fs: Check ext4 behaviour if dirent is first entry in directory block

[Stefan Brüns]

This is a regression test for a crash happening if the first dirent
in the block matches. Code tried to access a predecessor entry which
does not exist.
The crash happened for any block, but "." is always the first entry in
the first directory block and thus easy to check for.

Signed-off-by: Stefan Brüns 
---
 test/fs/fs-test.sh | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index b9c2306..69abdab 100755
--- a/test/fs/fs-test.sh
+++ b/test/fs/fs-test.sh
@@ -293,6 +293,12 @@ ${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_WRITE
 md5sum $addr \$filesize
 setenv filesize
 #
+
+# Next test case checks writing a file whose dirent
+# is the first in the block, which is always true for "."
+# The write should fail, but the lookup should work
+# Test Case 12 - Check directory traversal
+${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}. 0x10
 reset
 
 EOF
@@ -472,6 +478,10 @@ function check_results() {
pass_fail "TC11: 1MB write to $3.w - write succeeded"
check_md5 "Test Case 11b " "$1" "$2" 1 \
"TC11: 1MB write to $3.w - content verified"
+
+   # Check lookup of 'dot' directory
+   grep -A4 "Test Case 12 " "$1" | grep -q 'Unable to write file'
+   pass_fail "TC12: 1MB write to . - write denied"
echo "** End $1"
 }
 
-- 
2.10.0

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[U-Boot] [PATCH v2 0/5] Enhance fs tests

[Stefan Brüns]

The first 3 patches do some cleanups for the current test, especially TC11
had some issues (strange match for expected output, use of unitialized
variable).

The last two patches add test cases for handling ".". Ext4 used to crash,
as a match on the first entry of a directory block was not handled
correctly.

v2:
  Updated:
test/fs: Restructure file path specification to allow some flexibility
  * avoid creation of paths with double slashes
test/fs: Check writes using "." (same dir) relative path
  * fix issues copied from TC11
  * delete written file in cleanup
  Added:
test/fs: remove use of undefined WRITE_FILE variable
test/fs: strip noise from filesystem code prior to checking results

Stefan Brüns (5):
  test/fs: Restructure file path specification to allow some flexibility
  test/fs: remove use of undefined WRITE_FILE variable
  test/fs: strip noise from filesystem code prior to checking results
  test/fs: Check ext4 behaviour if dirent is first entry in directory
block
  test/fs: Check writes using "." (same dir) relative path

 test/fs/fs-test.sh | 131 +++--
 1 file changed, 78 insertions(+), 53 deletions(-)

-- 
2.10.0

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[U-Boot] [PATCH v2 2/5] test/fs: remove use of undefined WRITE_FILE variable

[Stefan Brüns]

The write file is created from $SMALL_FILE by appending ".w" on all
other occurences in the code.

Signed-off-by: Stefan Brüns 
---
 test/fs/fs-test.sh | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index f95350b..9615898 100755
--- a/test/fs/fs-test.sh
+++ b/test/fs/fs-test.sh
@@ -470,9 +470,9 @@ function check_results() {
# Check 1mb chunk write
grep -A3 "Test Case 11a " "$1" | \
egrep -q '1048576 bytes written|update journal'
-   pass_fail "TC11: 1MB write to $5 - write succeeded"
+   pass_fail "TC11: 1MB write to $3.w - write succeeded"
check_md5 "Test Case 11b " "$1" "$2" 1 \
-   "TC11: 1MB write to $5 - content verified"
+   "TC11: 1MB write to $3.w - content verified"
echo "** End $1"
 }
 
@@ -486,8 +486,7 @@ function test_fs_nonfs() {
OUT_FILE="${OUT}.$1.${fs}.out"
test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \
> ${OUT_FILE} 2>&1
-   check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \
-   $WRITE_FILE
+   check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE
TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
TOTAL_PASS=$((TOTAL_PASS + PASS))
echo "Summary: PASS: $PASS FAIL: $FAIL"
@@ -537,8 +536,7 @@ for fs in ext4 fat; do
sudo umount "$MOUNT_DIR"
rmdir "$MOUNT_DIR"
 
-   check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \
-   $WRITE_FILE
+   check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE
TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
TOTAL_PASS=$((TOTAL_PASS + PASS))
echo "Summary: PASS: $PASS FAIL: $FAIL"
-- 
2.10.0

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Re: [U-Boot] [PATCH 5/5] arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support

[Fabio Estevam]

On Tue, Sep 13, 2016 at 11:24 AM, Jagan Teki  wrote:

> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
> +   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
> +   PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> +   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
> +   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> +
> +iomux_v3_cfg_t const usdhc1_pads[] = {

static

> +   IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +   IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +   IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +   IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +   IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +   IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +   IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD 
> */
> +};
> +
> +#ifdef CONFIG_FSL_ESDHC
> +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
> +#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 15)
> +
> +struct fsl_esdhc_cfg usdhc_cfg[2] = {

static

> +int board_mmc_init(bd_t *bis)
> +{
> +   int i;
> +
> +   /*
> +   * According to the board_mmc_init() the following map is done:
> +   * (U-boot device node)(Physical Port)
> +   * mmc0  USDHC1
> +   * mmc1  USDHC3

Here you say both mmc are used.

> +   */
> +   for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> +   switch (i) {
> +   case 0:
> +   SETUP_IOMUX_PADS(usdhc1_pads);
> +   gpio_direction_input(USDHC1_CD_GPIO);
> +   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> +   break;

,but here only USDHC1 is initialized.

If only USDHC1 is initialized you can skip the for loop.


> +   default:
> +   printf("Warning: you configured more USDHC 
> controllers"
> +   "(%d) than supported by the board\n", i + 1);
> +   return 0;
> +   }
> +
> +   if (fsl_esdhc_initialize(bis, _cfg[i]))
> +   printf("Warning: failed to initialize mmc dev %d\n", 
> i);

If fsl_esdhc_initialize() fails you are returning 0, whic is wrong.

You want this probably:

ret = fsl_esdhc_initialize(bis, _cfg[i]);
if (ret)
return ret;

Or if only USDHC1 is used you can do:

ret = fsl_esdhc_initialize(bis, _cfg[0]);
if (ret)
return ret;


> +   }
> +
> +   return 0;
> +}
> +#endif
> +
> +iomux_v3_cfg_t const uart4_pads[] = {

static

> +int dram_init(void)
> +{
> +   gd->ram_size = get_ram_size((long *)PHYS_SDRAM, MAX_SDRAM_SIZE);

You should use imx_ddr_size() here.
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[U-Boot] [PATCH 1/2] cros_ec: Add function to read back flash parameters

[Moritz Fischer]

Add support for reading back flash parameters as reported by
the ec.

Signed-off-by: Moritz Fischer 
Cc: Simon Glass 
Cc: u-boot@lists.denx.de
---
 drivers/misc/cros_ec.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 06a7dcc..931fdf5 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -809,6 +809,27 @@ static int cros_ec_data_is_erased(const uint32_t *data, 
int size)
return 1;
 }
 
+/**
+ * Read back flash parameters
+ *
+ * This function reads back parameters of the flash as reported by the EC
+ *
+ * @param dev  Pointer to device
+ * @param info Pointer to output flash info struct
+ */
+int cros_ec_read_flashinfo(struct cros_ec_dev *dev,
+ struct ec_response_flash_info *info)
+{
+   int ret;
+
+   ret = ec_command(dev, EC_CMD_FLASH_INFO, 0,
+NULL, 0, info, sizeof(*info));
+   if (ret < 0)
+   return ret;
+
+   return ret < sizeof(*info) ? -1 : 0;
+}
+
 int cros_ec_flash_write(struct cros_ec_dev *dev, const uint8_t *data,
 uint32_t offset, uint32_t size)
 {
-- 
2.7.4

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[U-Boot] [PATCH 2/2] cros_ec: Add crosec flashinfo command

[Moritz Fischer]

Add command to print out the flash info as reported by the
ec. The data read back includes size, write block size,
erase block size.

Signed-off-by: Moritz Fischer 
Cc: Simon Glass 
Cc: u-boot@lists.denx.de
---
 drivers/misc/cros_ec.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 931fdf5..cb5db0f 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1382,6 +1382,15 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
printf("Offset: %x\n", offset);
printf("Size:   %x\n", size);
}
+   } else if (0 == strcmp("flashinfo", cmd)) {
+   struct ec_response_flash_info p;
+
+   ret = cros_ec_read_flashinfo(dev, );
+   if (!ret) {
+   printf("Flash size: %u\n", p.flash_size);
+   printf("Write block size:   %u\n", p.write_block_size);
+   printf("Erase block size:   %u\n", p.erase_block_size);
+   }
} else if (0 == strcmp("vbnvcontext", cmd)) {
uint8_t block[EC_VBNV_BLOCK_SIZE];
char buf[3];
@@ -1501,6 +1510,7 @@ U_BOOT_CMD(
"crosec events  Read CROS-EC host events\n"
"crosec clrevents [mask]Clear CROS-EC host events\n"
"crosec regioninfo   Read image info\n"
+   "crosec flashinfo   Read flash info\n"
"crosec erase    Erase EC image\n"
"crosec read   []   Read EC image\n"
"crosec write   []  Write EC image\n"
-- 
2.7.4

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Re: [U-Boot] [PATCH 21/21] arm: imx: add i.MX6ULL 14x14 EVK board support

[Fabio Estevam]

Hi Jagan,

On Tue, Sep 13, 2016 at 4:11 PM, Jagan Teki  wrote:

 +int dram_init(void)
 +{
 +   gd->ram_size = imx_ddr_size();
>
> Is this common call for all imx soc's to get the ddr size? because I
> observed incorrect size when I call this function.

Yes, if you get incorrect size when using this function, it means that
your DDR initialization is incorrect.
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Re: [U-Boot] [PATCH v1 2/7] clk: at91: Improve the clock implementation

[Stephen Warren]

On 09/12/2016 07:54 PM, Wenyou Yang wrote:

For the peripheral clock, provide the clock ops for the clock
provider, such as spi0_clk. The .of_xlate is to get the clk->id,
the .enable is to enable the spi0 peripheral clock, the .get_rate
is to get the clock frequency.

The driver for periph32ck node is responsible for recursively
binding its children as clk devices, not provide the clock ops.

So do the generated clock and system clock.



diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c



+/**
+ * generated_clk_bind() - for the generated clock driver
+ * Recursively bind its children as clk devices.
+ *
+ * @return: 0 on success, or negative error code on failure
+ */
+static int generated_clk_bind(struct udevice *dev)

... (code to enumerate/instantiate all child DT nodes)

+}
+
+static const struct udevice_id generated_clk_match[] = {
+   { .compatible = "atmel,sama5d2-clk-generated" },
+   {}
+};
+
+U_BOOT_DRIVER(generated_clk) = {
+   .name = "generated-clk",
+   .id = UCLASS_CLK,
+   .of_match = generated_clk_match,
+   .bind = generated_clk_bind,
+};


This driver shouldn't be UCLASS_CLK, and can't be without any clock ops 
implemented. It appears to be for another DT node that solely exists to 
house various sub-nodes which are the actual clock providers. I believe 
you should make this UCLASS_MISC. I guess you need to keep the custom 
bind function, since all the child nodes that it enumerates explicitly 
don't have a compatible value, so you can't rely on e.g. the default 
UCLASS_SIMPLE_BUS bind function to enumerate them.


BTW, while reading ./arch/arm/dts/sama5d2.dtsi, I noticed:

sdmmc0_gclk: sdmmc0_gclk {
#clock-cells = <0>;
reg = <31>;
};

Doesn't dtc complain about that? The node has a reg property, yet there 
is no unit address in the node name to match it. Instead, that node 
should be:


sdmmc0_gclk: sdmmc0_gclk@31 {
#clock-cells = <0>;
reg = <31>;
};


+static int generic_clk_of_xlate(struct clk *clk,
+  struct fdtdec_phandle_args *args)
 {
-   struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+   int periph;


The following should likely be added here:

if (args->args_count) {
debug("Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}


+   periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1);
+   if (periph < 0)
+   return -EINVAL;
+
+   clk->id = periph;


I guess that's OK. of_xlate is really intended to parse/process the 
clocks property in the client DT node. However, I suppose parsing the 
referenced DT node is probably OK too. Has this Atmel clock binding, and 
a similar clock driver implementation (including custom of_xlate) been 
reviewed for inclusion in the Linux kernel? I'd be curious if the same 
technique was/wasn't allowed there.



+static int generic_clk_probe(struct udevice *dev)

...

+   dev = dev_get_parent(dev);
+   dev = dev_get_parent(dev);


That line is duplicated.


diff --git a/drivers/clk/at91/clk-peripheral.c 
b/drivers/clk/at91/clk-peripheral.c


The same comments as above all apply to this file too.


+static ulong periph_get_rate(struct clk *clk)
 {
+   struct udevice *dev;
+   struct clk clk_dev;
+   int ret;

+   dev = dev_get_parent(clk->dev);
+   ret = clk_request(dev, _dev);


You haven't filled in clk_dev.id here. That needs to be filled in before 
calling clk_request().



+   if (ret)
+   return ret;
+
+   ret = clk_get_by_index(dev, 0, _dev);


This over-writes everything in clk_dev, thus making the call to 
clk_request() above pointless.



+   if (ret)
+   return ret;
+
+   return clk_get_rate(_dev);


You need to call clk_free(_dev) before returning. This comment 
applies to generated_clk_get_rate()/generic_clk_get_rate() too (in the 
previous file), although that problem existed before this patch.



+static int periph_clk_probe(struct udevice *dev)
+{
+   struct periph_clk_platdata *plat = dev_get_platdata(dev);
+
+   dev = dev_get_parent(dev);
+   dev = dev_get_parent(dev);
+   plat->reg_base = (struct at91_pmc *)dev_get_addr_ptr(dev);


It would be helpful documentation-wise to use separate variables for 
those parents; make the variable name indicate what the parent is 
expected to be:


dev_periph_container = dev_get_parent(dev);
dev_pmc = dev_get_parent(dev_periph_container);


diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c


Likewise, all the same comments above apply to this file too.


+/**
+ * at91_system_clk_bind() - for the system clock driver
+ * Recursively bind its children as clk devices.
+ *
+ * @return: 0 on success, or negative error code on failure
+ */
+static int at91_system_clk_bind(struct udevice *dev)
+{

...

+   /*
+* If this node has 

Re: [U-Boot] [PATCH 21/21] arm: imx: add i.MX6ULL 14x14 EVK board support

[Jagan Teki]

Hi Peng,

On Thu, Sep 8, 2016 at 7:05 AM, Peng Fan  wrote:
> Hi Jagan,
> On Wed, Sep 07, 2016 at 08:21:07PM +0530, Jagan Teki wrote:
>>On Thu, Aug 11, 2016 at 11:32 AM, Peng Fan  wrote:
>>> Add i.MX6ULL EVK board support:
>>> Add device tree file, which is copied from NXP Linux.
>>> Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
>>> The uart iomux settings are still keeped in board file.
>>>
>>> Boot Log:
>>> U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)
>>>
>>> CPU:   Freescale i.MX6ULL rev1.0 at 396MHz
>>> CPU:   Commercial temperature grade (0C to 95C) at 15C
>>> Reset cause: POR
>>> Model: Freescale i.MX6 ULL 14x14 EVK Board
>>> Board: MX6ULL 14x14 EVK
>>> DRAM:  512 MiB
>>> MMC:   initialized IMX pinctrl driver
>>> FSL_SDHC: 0, FSL_SDHC: 1
>>
>>
>>
>>> diff --git a/board/freescale/mx6ullevk/mx6ullevk.c 
>>> b/board/freescale/mx6ullevk/mx6ullevk.c
>>> new file mode 100644
>>> index 000..489bf21
>>> --- /dev/null
>>> +++ b/board/freescale/mx6ullevk/mx6ullevk.c
>>> @@ -0,0 +1,99 @@
>>> +/*
>>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
>>> +   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
>>> +   PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
>>> +
>>> +int dram_init(void)
>>> +{
>>> +   gd->ram_size = imx_ddr_size();

Is this common call for all imx soc's to get the ddr size? because I
observed incorrect size when I call this function.

>>> +
>>> +   return 0;
>>> +}
>>> +
>>> +static iomux_v3_cfg_t const uart1_pads[] = {
>>> +   MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +   MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +};
>>> +
>>> +static void setup_iomux_uart(void)
>>> +{
>>> +   imx_iomux_v3_setup_multiple_pads(uart1_pads, 
>>> ARRAY_SIZE(uart1_pads));
>>> +}
>>> +
>>> +int board_mmc_get_env_dev(int devno)
>>> +{
>>> +   return devno;
>>> +}
>>> +
>>> +int mmc_map_to_kernel_blk(int devno)
>>> +{
>>> +   return devno;
>>> +}
>>> +
>>> +int board_early_init_f(void)
>>> +{
>>> +   setup_iomux_uart();
>>
>>Don't we need iomux settings for sdhc? I guess pinctrl for SD not
>>supporting now.
>
> The pinctrl driver will configure the pinmux, no need to add iomux settings
> in board file. In this patchset, I enabled PINCTRL, DM_MMC, DM_GPIO and etc.

Yeah, but the uart pinx mux are still in board file right?

-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH 2/3] test/fs: Check ext4 behaviour if dirent is first entry in directory block

[Brüns , Stefan]

On Dienstag, 13. September 2016 12:33:15 CEST Stephen Warren wrote:
> On 09/12/2016 03:48 PM, Stefan Bruens wrote:
> > On Montag, 12. September 2016 12:39:35 CEST you wrote:
> >> On 09/11/2016 02:46 PM, Stefan Brüns wrote:
> >>> This is a regression test for a crash happening if the first dirent
> >>> in the block matches. Code tried to access a predecessor entry which
> >>> does not exist.
> >>> The crash happened for any block, but "." is always the first entry in
> >>> the first directory block and thus easy to check for.
> >>> 
> >>> diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
> >>> 
> >>> +# Next test case checks writing a file whose dirent
> >>> +# is the first in the block, which is always true for "."
> >>> +# The write should fail, but the lookup should work
> >>> +# Test Case 12 - Check directory traversal
> >>> +${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}. 0x10
> >> 
> >> Doesn't that attempt to write a file named ".", which would end up
> >> over-writing the directory content? Unless I'm misunderstanding, that
> >> doesn't seem like a good idea.
> >> 
> >> Also, ${FPATH} might be "", "/", "something", or "something/". Appending
> >> "." to some of those won't work the same way as some others.
> > 
> > "something" can not happen.
> 
> I don't see any code that prevents that. I think it's fairer to say that
> nothing currently happens to call the function with FPATH with a
> trailing /. Someone could easily edit the script later and add such a
> call without knowing about the undocumented restriction.
> 
> I note that in patch 1, the following logic:
> 
> + if [ ! -z "$6" ]; then
> + FPATH=${6}/${FPATH}
>   fi
> 
> ... ends up with FPATH having a leading / for the second invocation of
> test_image by the main script body, since ${6} has the value
> `pwd`/$MOUNT_DIR. That seems to violate FAT's requirement for pathnames
> not to have a leading /.

There are 6 different test runs: { sb, fs, nonfs } x { fat, ext4 }

fs and nonfs can be treated the same way, its just e.g. "ext4ls", "ls" or 
"fatls", "ls" resp. Thats what I called "native" in the other mail.

Now in the "sb" cases, it does not matter if the mounted image is fat or ext4 
- it always uses the full absolute path to the mountpoint.

The specific requirements of ext4 (absolute path) and fat (relative path) only 
apply to the nonfs and fs test runs.

Kind regards,

Stefan

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Re: [U-Boot] [PATCH v9] dm: at91: Add driver model support for the spi driver

[Stephen Warren]

On 09/12/2016 08:23 PM, Wenyou Yang wrote:

Add driver model support while retaining the existing legacy code.
This allows the driver to support boards that have converted to
driver model as well as those that have not.


I only reviewed the clock-related calls in this file, and they look 
fine, so,

Acked-by: Stephen Warren 
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Re: [U-Boot] [PATCH v1 3/7] gpio: atmel_pio4: Remove unneccessary clock calling

[Stephen Warren]

On 09/12/2016 07:54 PM, Wenyou Yang wrote:

Due to the peripheral clock driver improvement, remove the
unneccessary clock calling.


Patches 3-7,
Acked-by: Stephen Warren 
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Re: [U-Boot] [PATCH 3/3] test/fs: Check writes using "." (same dir) relative path

[Brüns , Stefan]

On Dienstag, 13. September 2016 12:36:26 CEST you wrote:
> On 09/12/2016 04:04 PM, Stefan Bruens wrote:
> > On Montag, 12. September 2016 12:44:08 CEST you wrote:
> >> On 09/11/2016 02:46 PM, Stefan Brüns wrote:
> >>> / and /./ should reference the same file.
> >>> 
> >>> diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
> >>> 
> >>> +# Read 1MB from small file
> >>> +${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_SMALL
> >> 
> >> I think the same issue with $FPATH ending/not-ending in / applies here
> >> too, and for all commands in this patch.
> > 
> > FPATH is either "" for native fat, "/" for native ext4, or / for
> > hostfs, so this is correct. Specifically, for fat, we dont want any "/" in
> > front of $FILE_foo.
> 
> I believe FPATH can be either "", "/" or "/foo/bar" here, due to the
> issue I just mentioned in the other email.

FPATH is either "", "/", "/foo/bar" + "/" or "/foo/bar" + "/" + "/". The last 
one is not to too nice, but still correct.

FPATH is *never* "/foo/bar", i.e. without trailing slash.

 
> >>> @@ -482,6 +499,16 @@ function check_results() {
> >>> 
> >>> + # Check directory traversal
> >>> + grep -A6 "Test Case 13a " "$1" | \
> >>> + egrep -q '1048576 bytes written|update journal'
> >> 
> >> Why is "update journal" considered successful? Surely the "n bytes
> >> written" message is always printed irrespective of whether anything
> >> journal-related happened?
> > 
> > Thats a question left to the author of Test Case 11, where the fragment
> > was
> > copied from.
> 
> I don't quite agree; you're adding the new test, so should make sure the
> validation code makes sense.

I did not claim this is correct. I just stated this problem exists already for 
the older test cases.
 
> > Ext4 unfortunately is quite verbose, it inserts "File system is
> > consistent"
> > and "update journal finished" lines in the output. I think these lines
> > where better stripped from the log prior to any further parsing.
> 
> ext4 may print some extra output, but that doesn't mean that any of it
> should be used in the validation. I think the simplest thing is to just
> ignore it in the validation code. Using egrep -q '1048576 bytes written'
> should do that just fine, and not get a false-positive if ext4 does say
> "update journal" without saying the required "1048576 bytes written".

No, this will not work for ext4 *and* fat.

Every check starts with a "grep -Axx 'Test Case n'" match. If "-Axx" is 
extended to *always* include the "yyy bytes written", then it will work for 
ext4, but it will also match "Test Case n \n failed \n Test Case n+1 \n yyy 
bytes written".

Kind Regards,

Stefan
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Re: [U-Boot] [PATCH v1 1/7] clk: clk-uclass: Assign clk->dev before call .of_xlate

[Stephen Warren]

On 09/12/2016 07:54 PM, Wenyou Yang wrote:

In order to make clk->dev available in ops->of_xlate() to get the
clock ID from the 'reg' property of the clock node, assign the
clk->dev before calling ops->of_xlate().


It does seem reasonable to me to allow using the same of_xlate 
implementation across multiple similar-but-different clock providers, 
and this change is required to allow that. I note that the reset and 
power domain uclasses already work this way. So, from that perspective, 
you get an ack.



diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c



@@ -80,6 +80,9 @@ int clk_get_by_index(struct udevice *dev, int index, struct 
clk *clk)
  __func__, ret);
return ret;
}
+
+   clk->dev = dev_clk;


That assignment also happens in clk_request() itself. I'm tempted to say 
that we should modify clk_request() to remove the dev parameter, and 
remove the assignment of clk->dev. clk_request()'s documentation says:



 * @clock:  A pointer to a clock struct to initialize. The caller must
 *  have already initialized any field in this struct which the
 *  clock provider uses to identify the clock.


... and since clk->dev is a field that is used to identify the clock, it 
really should be set already, thus removing the need for this function 
to set clk->dev.


However, I suppose we can clean that up later, so,
Acked-by: Stephen Warren 
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Re: [U-Boot] [PATCH v2 0/2] Detect and reject new ad-hoc CONFIG options

[Simon Glass]

Hi Tom,

On 13 September 2016 at 07:49, Tom Rini  wrote:
> On Tue, Sep 13, 2016 at 07:35:42AM -0600, Simon Glass wrote:
>> Hi Tom,
>>
>> On 13 September 2016 at 07:16, Tom Rini  wrote:
>> > On Mon, Sep 12, 2016 at 11:20:00PM -0600, Simon Glass wrote:
>> >
>> >> Despite the availability of Kconfig, the number of ad-hoc CONFIG options 
>> >> in
>> >> U-Boot is still at over 8000.
>> >>
>> >> In February 2015 (commit 741e58e0) there were around 8387 ad-hoc CONFIGs.
>> >> As of this patch there are about 8336, only a little fewer.
>> >>
>> >> One problem is that new ones are still being added, admittedly at a slower
>> >> rate. This series adds a Makefile check to detect that and produce a build
>> >> error. This provides immediate feedback that new CONFIG options should go 
>> >> in
>> >> Kconfig.
>> >>
>> >> Changes in v2:
>> >> - Rebase to mainline
>> >> - Fix scripts so that there are no errors
>> >> - Add the 'build-whitelist.sh' script to the tree
>> >>
>> >> Simon Glass (2):
>> >>   Kconfig: Add a whitelist of ad-hoc CONFIG options
>> >>   Makefile: Give a build error if ad-hoc CONFIG options are added
>> >
>> > OK, this is still a little fragile.  When I do:
>> > ./tools/buildman/buildman -b master --force-build --step 0 \
>> >  -SCdvel 
>> > 'avr32|nds32|bfin|m68k|microblaze|or32|sh4|sparc|mips|mips64|xtensa'
>> >
>> > vs kconfig-working2 I'm seeing a bunch of failures:
>> > +(M5475GFE) make[1]: *** [no_new_adhoc_configs_check] Error 1
>> > +(M5475GFE) make: *** [sub-make] Error 2
>>
>> Yes it looks like I was testing it incorrectly, relying on running on
>> from the SPL series. One problem is that it misses configs with lower
>> case which are defined in Kconfig and then used. I've updated
>> u-boot-dm/kconfig-working2 to deal with that.
>>
>> I'll take another look at this and have an update out today. But we
>> can decouple this from the painful SPL series if you like, since in
>> principle we can run the generation script to create the first of the
>> two patches.
>
> Yes, we can de-couple this.  However, you might want to take a look at
> say xtensa as in my check with before/after kconfig-working2 there's a
> tiny size difference and I don't see that normally for a Kconfig
> migration.  I'm doing my arm/powerpc build now to see if there's a
> similar set of size changes there and will then start poking at map
> files.

Here's a full list of config changes for the SPL series as far as I can tell:

$ buildman -b kc4-conf -fC --step 0 -DI -s
boards.cfg is up to date. Nothing to do.
Summary of 2 commits for 1196 boards (32 threads, 1 job per thread)
01: buildman
  openrisc:  +   openrisc-generic
 sparc:  +   grsim grsim_leon2 gr_cpci_ax2000 gr_xc3s_1500 gr_ep2s60
  blackfin:  +   bf609-ezkit
46: Convert CONFIG_SPL_YMODEM_SUPPORT to Kconfig
arm:
   + u-boot.cfg: CONFIG_ENV_ADDR=(CONFIG_SYS_FLASH_BASE +
CONFIG_SYS_MONITOR_LEN) CONFIG_ENV_IS_IN_FLASH=1
CONFIG_ENV_SECT_SIZE=0x0001 CONFIG_NAND=1 CONFIG_SPL_ENV_SUPPORT=1
CONFIG_SPL_NET_SUPPORT=1 CONFIG_SPL_NET_VCI_STRING="" CONFIG_STV0991=1
CONFIG_SYS_MONITOR_LEN=0x0004 CONFIG_USBTTY=1
   - u-boot.cfg: CONFIG_DW_UDC=1 CONFIG_ENV_IS_IN_NAND=1
CONFIG_ENV_OFFSET=0x6 CONFIG_ENV_RANGE=0x1
CONFIG_SPEAR_USBTTY=1 CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_USBD_HS=1 CONFIG_USBD_MANUFACTURER="ST Microelectronics"
CONFIG_USBD_PRODUCT_NAME="SPEAr SoC" CONFIG_USB_DEVICE=1
CONFIG_USB_TTY=1 CONFIG_nand=1 CONFIG_spear300=1 CONFIG_spear310=1
CONFIG_spear320=1 CONFIG_spear600=1 CONFIG_stv0991=1 CONFIG_usbtty=1
   + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1
CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_YMODEM_SUPPORT=1
   - u-boot-spl.cfg: CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
   + all: CONFIG_ENV_ADDR=(CONFIG_SYS_FLASH_BASE +
CONFIG_SYS_MONITOR_LEN) CONFIG_ENV_IS_IN_FLASH=1
CONFIG_ENV_SECT_SIZE=0x0001 CONFIG_NAND=1 CONFIG_SPL_ENV_SUPPORT=1
CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
CONFIG_SPL_NET_SUPPORT=1 CONFIG_SPL_NET_VCI_STRING=""
CONFIG_SPL_YMODEM_SUPPORT=1 CONFIG_STV0991=1
CONFIG_SYS_MONITOR_LEN=0x0004 CONFIG_USBTTY=1
   - all: CONFIG_DW_UDC=1 CONFIG_ENV_IS_IN_NAND=1
CONFIG_ENV_OFFSET=0x6 CONFIG_ENV_RANGE=0x1
CONFIG_SPEAR_USBTTY=1 CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_USBD_HS=1 CONFIG_USBD_MANUFACTURER="ST Microelectronics"
CONFIG_USBD_PRODUCT_NAME="SPEAr SoC" CONFIG_USB_DEVICE=1
CONFIG_USB_TTY=1 CONFIG_nand=1 CONFIG_spear300=1 CONFIG_spear310=1
CONFIG_spear320=1 CONFIG_spear600=1 CONFIG_stv0991=1 CONFIG_usbtty=1
spear320_usbtty spear320_usbtty_pnor :
   + u-boot.cfg: CONFIG_USBTTY=1
   - u-boot.cfg: CONFIG_DW_UDC=1 CONFIG_SPEAR_USBTTY=1
CONFIG_USBD_HS=1 CONFIG_USBD_MANUFACTURER="ST Microelectronics"
CONFIG_USBD_PRODUCT_NAME="SPEAr SoC" CONFIG_USB_DEVICE=1
CONFIG_USB_TTY=1 CONFIG_spear320=1 CONFIG_usbtty=1
   + all: CONFIG_USBTTY=1
   - all: CONFIG_DW_UDC=1 CONFIG_SPEAR_USBTTY=1 CONFIG_USBD_HS=1
CONFIG_USBD_MANUFACTURER="ST Microelectronics"

Re: [U-Boot] [PATCH 3/3] test/fs: Check writes using "." (same dir) relative path

[Stephen Warren]

On 09/12/2016 04:04 PM, Stefan Bruens wrote:

On Montag, 12. September 2016 12:44:08 CEST you wrote:

On 09/11/2016 02:46 PM, Stefan Brüns wrote:

/ and /./ should reference the same file.

diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh

+# Read 1MB from small file
+${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_SMALL


I think the same issue with $FPATH ending/not-ending in / applies here
too, and for all commands in this patch.


FPATH is either "" for native fat, "/" for native ext4, or / for
hostfs, so this is correct. Specifically, for fat, we dont want any "/" in
front of $FILE_foo.


I believe FPATH can be either "", "/" or "/foo/bar" here, due to the 
issue I just mentioned in the other email.



@@ -482,6 +499,16 @@ function check_results() {

+   # Check directory traversal
+   grep -A6 "Test Case 13a " "$1" | \
+   egrep -q '1048576 bytes written|update journal'


Why is "update journal" considered successful? Surely the "n bytes
written" message is always printed irrespective of whether anything
journal-related happened?


Thats a question left to the author of Test Case 11, where the fragment was
copied from.


I don't quite agree; you're adding the new test, so should make sure the 
validation code makes sense.



Ext4 unfortunately is quite verbose, it inserts "File system is consistent"
and "update journal finished" lines in the output. I think these lines where
better stripped from the log prior to any further parsing.


ext4 may print some extra output, but that doesn't mean that any of it 
should be used in the validation. I think the simplest thing is to just 
ignore it in the validation code. Using egrep -q '1048576 bytes written' 
should do that just fine, and not get a false-positive if ext4 does say 
"update journal" without saying the required "1048576 bytes written".

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Re: [U-Boot] [PATCH 2/3] test/fs: Check ext4 behaviour if dirent is first entry in directory block

[Stephen Warren]

On 09/12/2016 03:48 PM, Stefan Bruens wrote:

On Montag, 12. September 2016 12:39:35 CEST you wrote:

On 09/11/2016 02:46 PM, Stefan Brüns wrote:

This is a regression test for a crash happening if the first dirent
in the block matches. Code tried to access a predecessor entry which
does not exist.
The crash happened for any block, but "." is always the first entry in
the first directory block and thus easy to check for.

diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh

+# Next test case checks writing a file whose dirent
+# is the first in the block, which is always true for "."
+# The write should fail, but the lookup should work
+# Test Case 12 - Check directory traversal
+${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}. 0x10


Doesn't that attempt to write a file named ".", which would end up
over-writing the directory content? Unless I'm misunderstanding, that
doesn't seem like a good idea.

Also, ${FPATH} might be "", "/", "something", or "something/". Appending
"." to some of those won't work the same way as some others.


"something" can not happen.


I don't see any code that prevents that. I think it's fairer to say that 
nothing currently happens to call the function with FPATH with a 
trailing /. Someone could easily edit the script later and add such a 
call without knowing about the undocumented restriction.


I note that in patch 1, the following logic:

+   if [ ! -z "$6" ]; then
+   FPATH=${6}/${FPATH}
fi

... ends up with FPATH having a leading / for the second invocation of 
test_image by the main script body, since ${6} has the value 
`pwd`/$MOUNT_DIR. That seems to violate FAT's requirement for pathnames 
not to have a leading /.


> The other three cases are exactly what is wanted

here, as fat currently needs a relative path, with CWD being "/", and ext
explicitly wants an absolute path.


@@ -471,6 +477,11 @@ function check_results() {

+   # Check lookup of 'dot' directory
+   grep -A5 "Test Case 12 " "$1" | \
+   egrep -q 'Unable to write file'
+   pass_fail "TC12: 1MB write to . - write denied"


Oh, I see; this expects the write to be denied since the destination is
a directory. Perhaps that's OK. I'd rather see a read attempt though, to
guarantee that even if the access does end up being allowed, the FS
isn't trashed for any future tests that may be added afterwards.


U-Boot master/2016-09 crashes here without the pending ext4 fixes.


> IMHO after

a failed test case, everything afterwards is invalid anyway, if the same fs
image is used.


That's fair.


As soon as the image is modified, tests are no longer idempotent. Block
allocation order may change, anything that allocates any resource changes the
image.

Atempting a write here is done as it actually exercises a different code path.
"ext4load host 0:0 0 /." reports "File not found", "ext4write host 0:0 0 /."
crashes.

Kind regards,

Stefan



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Re: [U-Boot] [RFC] board/liteboard: Add support for liteSOM and liteBoard

[Fabio Estevam]

Hi Marcin,

On Wed, Aug 31, 2016 at 7:54 AM, Marcin Niestroj
 wrote:
> liteSOM is a System On Module (http://grinn-global.com/litesom/). It
> can't exists on its own, but will be used as part of other boards.
>
> Hardware specification:
>  * NXP i.MX6UL processor
>  * 256M or 512M DDR3 memory
>  * optional eMMC (uSDHC2)
>
> liteBoard is a development board which uses liteSOM as its base.
>
> Hardware specification:
>  * liteSOM (i.MX6UL, DRAM, eMMC)
>  * Ethernet PHY (id 0)
>  * USB host (usb_otg1)
>  * MicroSD slot (uSDHC1)
>
> The main question is: how should liteSOM sources be integrated? I didn't
> find similar modules, which are part of different boards in u-boot
> tree. For now, I've put source into arch/arm/mach-litesom, but I guess
> it is not the best place for them.

What about placing it inside board/grinn/ ?

> +   .p0_mpdgctrl0 = 0x41490145,
> +   .p0_mprddlctl = 0x40404546,
> +   .p0_mpwrdlctl = 0x4040524D,
> +};
> +
> +struct mx6_ddr_sysinfo ddr_sysinfo = {
> +   .dsize = 0,
> +   .cs_density = 20,
> +   .ncs = 1,
> +   .cs1_mirror = 0,
> +   .rtt_wr = 2,
> +   .rtt_nom = 1,   /* RTT_Nom = RZQ/2 */
> +   .walat = 1, /* Write additional latency */
> +   .ralat = 5, /* Read additional latency */
> +   .mif3_mode = 3, /* Command prediction working mode */
> +   .bi_on = 1, /* Bank interleaving enabled */
> +   .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
> +   .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
> +   .ddr_type = DDR_TYPE_DDR3,

Please rebase against U-Boot 2016.09. There are new fields now: refsel and refr.
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[U-Boot] [PATCH 18/21] clock: implement a driver for the Tegra CAR

[Stephen Warren]

From: Stephen Warren 

Implement a clock uclass driver for the Tegra CAR. This allows clients to
use standard clock APIs on Tegra. This device is intended to be
instantiated by the core Tegra CAR driver, rather than being instantiated
directly from DT. The implementation uses the existing custom Tegra-
specific clock APIs to avoid coupling the series with significant
refactoring of the existing Tegra clock/clock code. The driver currently
only supports peripheral clocks, and avoids support for other clocks such
as PLLs and external clocks. This should be sufficient to convert over all
Tegra peripheral drivers, and avoids a complex implementation which calls
different Tegra-specific clock APIs based on the type of clock being
manipulated.

Signed-off-by: Stephen Warren 
---
 drivers/clk/tegra/Kconfig |   7 +++
 drivers/clk/tegra/Makefile|   1 +
 drivers/clk/tegra/tegra-car-clk.c | 103 ++
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/clk/tegra/tegra-car-clk.c

diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
index 659fe022c2af..ce80b1ff3ea4 100644
--- a/drivers/clk/tegra/Kconfig
+++ b/drivers/clk/tegra/Kconfig
@@ -1,3 +1,10 @@
+config TEGRA_CAR_CLOCK
+   bool "Enable Tegra CAR-based clock driver"
+   depends on TEGRA_CAR
+   help
+ Enable support for manipulating Tegra's on-SoC clocks via direct
+ register access to the Tegra CAR (Clock And Reset controller).
+
 config TEGRA186_CLOCK
bool "Enable Tegra186 BPMP-based clock driver"
depends on TEGRA186_BPMP
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index f32998ccc27d..0fcc5205a70b 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -2,4 +2,5 @@
 #
 # SPDX-License-Identifier: GPL-2.0
 
+obj-$(CONFIG_TEGRA_CAR_CLOCK) += tegra-car-clk.o
 obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o
diff --git a/drivers/clk/tegra/tegra-car-clk.c 
b/drivers/clk/tegra/tegra-car-clk.c
new file mode 100644
index ..b8a2c82a25c0
--- /dev/null
+++ b/drivers/clk/tegra/tegra-car-clk.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int tegra_car_clk_request(struct clk *clk)
+{
+   debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+   /*
+* Note that the first PERIPH_ID_COUNT clock IDs (where the value
+* varies per SoC) are the peripheral clocks, which use a numbering
+* scheme that matches HW registers 1:1. There are other clock IDs
+* beyond this that are assigned arbitrarily by the Tegra CAR DT
+* binding. Due to the implementation of this driver, it currently
+* only supports the peripheral IDs.
+*/
+   if (clk->id >= PERIPH_ID_COUNT)
+   return -EINVAL;
+
+   return 0;
+}
+
+static int tegra_car_clk_free(struct clk *clk)
+{
+   debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+   return 0;
+}
+
+static ulong tegra_car_clk_get_rate(struct clk *clk)
+{
+   enum clock_id parent;
+
+   debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+   parent = clock_get_periph_parent(clk->id);
+   return clock_get_periph_rate(clk->id, parent);
+}
+
+static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
+{
+   enum clock_id parent;
+
+   debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
+ clk->dev, clk->id);
+
+   parent = clock_get_periph_parent(clk->id);
+   return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
+}
+
+static int tegra_car_clk_enable(struct clk *clk)
+{
+   debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+   clock_enable(clk->id);
+
+   return 0;
+}
+
+static int tegra_car_clk_disable(struct clk *clk)
+{
+   debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+   clock_disable(clk->id);
+
+   return 0;
+}
+
+static struct clk_ops tegra_car_clk_ops = {
+   .request = tegra_car_clk_request,
+   .free = tegra_car_clk_free,
+   .get_rate = tegra_car_clk_get_rate,
+   .set_rate = tegra_car_clk_set_rate,
+   .enable = tegra_car_clk_enable,
+   .disable = tegra_car_clk_disable,
+};
+
+static int tegra_car_clk_probe(struct udevice *dev)
+{
+   debug("%s(dev=%p)\n", __func__, dev);
+
+   return 0;
+}
+
+U_BOOT_DRIVER(tegra_car_clk) = {
+   .name = "tegra_car_clk",
+   .id = UCLASS_CLK,
+   .probe = tegra_car_clk_probe,
+   .ops = _car_clk_ops,
+};
-- 
2.9.3

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[U-Boot] [PATCH 19/21] ARM: tegra: enable standard clock/reset APIs everywhere

[Stephen Warren]

From: Stephen Warren 

Implementations of the standard clock and reset APIs are available on all
Tegra SoCs now, so enable compilation of those uclasses.

Enable the Tegra CAR drivers for all SoCs prior to the BPMP being
available. This provides an implementation of those APIs everywhere.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/Kconfig | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 448c31902d50..d8267a837239 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,6 +10,7 @@ config TEGRA_IVC
 
 config TEGRA_COMMON
bool "Tegra common options"
+   select CLK
select DM
select DM_ETH
select DM_GPIO
@@ -19,12 +20,20 @@ config TEGRA_COMMON
select DM_PCI
select DM_PCI_COMPAT
select DM_PWM
+   select DM_RESET
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+   select MISC
select OF_CONTROL
select VIDCONSOLE_AS_LCD if DM_VIDEO
 
+config TEGRA_NO_BPMP
+   bool "Tegra common options for SoCs without BPMP"
+   select TEGRA_CAR
+   select TEGRA_CAR_CLOCK
+   select TEGRA_CAR_RESET
+
 config TEGRA_ARMV7_COMMON
bool "Tegra 32-bit common options"
select CPU_V7
@@ -32,6 +41,7 @@ config TEGRA_ARMV7_COMMON
select SUPPORT_SPL
select TEGRA_COMMON
select TEGRA_GPIO
+   select TEGRA_NO_BPMP
 
 config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
@@ -62,13 +72,11 @@ config TEGRA210
bool "Tegra210 family"
select TEGRA_GPIO
select TEGRA_ARMV8_COMMON
+   select TEGRA_NO_BPMP
 
 config TEGRA186
bool "Tegra186 family"
-   select CLK
select DM_MAILBOX
-   select DM_RESET
-   select MISC
select TEGRA186_BPMP
select TEGRA186_CLOCK
select TEGRA186_GPIO
-- 
2.9.3

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[U-Boot] [PATCH 20/21] mmc: tegra: only use new clock/reset APIs

[Stephen Warren]

From: Stephen Warren 

Now that the standard clock/reset APIs are available for all Tegra SoCs,
convert the MMC driver to use them exclusively, and remove any references
to the custom Tegra-specific APIs.

Cc: Jaehoon Chung 
Signed-off-by: Stephen Warren 
---
 drivers/mmc/tegra_mmc.c | 45 +
 1 file changed, 5 insertions(+), 40 deletions(-)

diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 7b9628adb96e..97b115459546 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -13,32 +13,15 @@
 #include 
 #include 
 #include 
-#ifndef CONFIG_TEGRA186
-#include 
-#include 
-#endif
 #include 
 #include 
 
-/*
- * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
- * should not be present. These are needed because newer Tegra SoCs support
- * only the standard clock/reset APIs, whereas older Tegra SoCs support only
- * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
- * fixed to implement the standard APIs, and all drivers converted to solely
- * use the new standard APIs, with no ifdefs.
- */
-
 DECLARE_GLOBAL_DATA_PTR;
 
 struct tegra_mmc_priv {
struct tegra_mmc *reg;
-#ifdef CONFIG_TEGRA186
struct reset_ctl reset_ctl;
struct clk clk;
-#else
-   enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
-#endif
struct gpio_desc cd_gpio;   /* Change Detect GPIO */
struct gpio_desc pwr_gpio;  /* Power GPIO */
struct gpio_desc wp_gpio;   /* Write Protect GPIO */
@@ -373,6 +356,7 @@ static int tegra_mmc_send_cmd(struct mmc *mmc, struct 
mmc_cmd *cmd,
 
 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
 {
+   ulong rate;
int div;
unsigned short clk;
unsigned long timeout;
@@ -384,15 +368,9 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv 
*priv, uint clock)
 */
if (clock == 0)
goto out;
-#ifdef CONFIG_TEGRA186
-   {
-   ulong rate = clk_set_rate(>clk, clock);
-   div = (rate + clock - 1) / clock;
-   }
-#else
-   clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, clock,
-   );
-#endif
+
+   rate = clk_set_rate(>clk, clock);
+   div = (rate + clock - 1) / clock;
debug("div = %d\n", div);
 
writew(0, >reg->clkcon);
@@ -593,10 +571,7 @@ static int tegra_mmc_probe(struct udevice *dev)
 {
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct tegra_mmc_priv *priv = dev_get_priv(dev);
-   int bus_width;
-#ifdef CONFIG_TEGRA186
-   int ret;
-#endif
+   int bus_width, ret;
 
priv->cfg.name = "Tegra SD/MMC";
priv->cfg.ops = _mmc_ops;
@@ -625,7 +600,6 @@ static int tegra_mmc_probe(struct udevice *dev)
 
priv->reg = (void *)dev_get_addr(dev);
 
-#ifdef CONFIG_TEGRA186
ret = reset_get_by_name(dev, "sdhci", >reset_ctl);
if (ret) {
debug("reset_get_by_name() failed: %d\n", ret);
@@ -649,15 +623,6 @@ static int tegra_mmc_probe(struct udevice *dev)
ret = reset_deassert(>reset_ctl);
if (ret)
return ret;
-#else
-   priv->mmc_id = clock_decode_periph_id(gd->fdt_blob, dev->of_offset);
-   if (priv->mmc_id == PERIPH_ID_NONE) {
-   debug("%s: could not decode periph id\n", __func__);
-   return -FDT_ERR_NOTFOUND;
-   }
-
-   clock_start_periph_pll(priv->mmc_id, CLOCK_ID_PERIPH, 2000);
-#endif
 
/* These GPIOs are optional */
gpio_request_by_name(dev, "cd-gpios", 0, >cd_gpio,
-- 
2.9.3

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[U-Boot] [PATCH 21/21] i2c: tegra: only use new clock/reset APIs

[Stephen Warren]

From: Stephen Warren 

Now that the standard clock/reset APIs are available for all Tegra SoCs,
convert the I2C driver to use them exclusively, and remove any references
to the custom Tegra-specific APIs.

Cc: Heiko Schocher 
Signed-off-by: Stephen Warren 
---
 drivers/i2c/tegra_i2c.c | 68 -
 1 file changed, 11 insertions(+), 57 deletions(-)

diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 0dbcc5a1cfea..898f12a94689 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -12,27 +12,15 @@
 #include 
 #include 
 #include 
-#ifdef CONFIG_TEGRA186
 #include 
 #include 
-#else
+#ifndef CONFIG_TEGRA186
 #include 
 #include 
-#include 
-#include 
 #endif
 #include 
 #include 
 
-/*
- * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
- * should not be present. These are needed because newer Tegra SoCs support
- * only the standard clock/reset APIs, whereas older Tegra SoCs support only
- * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
- * fixed to implement the standard APIs, and all drivers converted to solely
- * use the new standard APIs, with no ifdefs.
- */
-
 DECLARE_GLOBAL_DATA_PTR;
 
 enum i2c_type {
@@ -44,12 +32,8 @@ enum i2c_type {
 /* Information about i2c controller */
 struct i2c_bus {
int id;
-#ifdef CONFIG_TEGRA186
struct reset_ctlreset_ctl;
struct clk  clk;
-#else
-   enum periph_id  periph_id;
-#endif
int speed;
int pinmux_config;
struct i2c_control  *control;
@@ -81,20 +65,15 @@ static void set_packet_mode(struct i2c_bus *i2c_bus)
 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
 {
/* Reset I2C controller. */
-#ifdef CONFIG_TEGRA186
reset_assert(_bus->reset_ctl);
udelay(1);
reset_deassert(_bus->reset_ctl);
udelay(1);
-#else
-   reset_periph(i2c_bus->periph_id, 1);
-#endif
 
/* re-program config register to packet mode */
set_packet_mode(i2c_bus);
 }
 
-#ifdef CONFIG_TEGRA186
 static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
 {
int ret;
@@ -114,7 +93,6 @@ static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned 
rate)
 
return 0;
 }
-#endif
 
 static void i2c_init_controller(struct i2c_bus *i2c_bus)
 {
@@ -126,12 +104,7 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
 * here, in section 23.3.1, but in fact we seem to need a factor of
 * 16 to get the right frequency.
 */
-#ifdef CONFIG_TEGRA186
i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
-#else
-   clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
-   i2c_bus->speed * 2 * 8);
-#endif
 
if (i2c_bus->type == TYPE_114) {
/*
@@ -151,12 +124,7 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
clk_div_stdfst_mode);
 
-#ifdef CONFIG_TEGRA186
i2c_init_clock(i2c_bus, rate);
-#else
-   clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
-  rate);
-#endif
}
 
/* Reset I2C controller. */
@@ -170,7 +138,7 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
}
 
 #ifndef CONFIG_TEGRA186
-   funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
+   funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
 #endif
 }
 
@@ -392,23 +360,13 @@ static int tegra_i2c_set_bus_speed(struct udevice *dev, 
unsigned int speed)
 static int tegra_i2c_probe(struct udevice *dev)
 {
struct i2c_bus *i2c_bus = dev_get_priv(dev);
-#ifdef CONFIG_TEGRA186
int ret;
-#else
-   const void *blob = gd->fdt_blob;
-   int node = dev->of_offset;
-#endif
bool is_dvc;
 
i2c_bus->id = dev->seq;
i2c_bus->type = dev_get_driver_data(dev);
i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev);
 
-   /*
-* We don't have a binding for pinmux yet. Leave it out for now. So
-* far no one needs anything other than the default.
-*/
-#ifdef CONFIG_TEGRA186
ret = reset_get_by_name(dev, "i2c", _bus->reset_ctl);
if (ret) {
error("reset_get_by_name() failed: %d\n", ret);
@@ -419,9 +377,13 @@ static int tegra_i2c_probe(struct udevice *dev)
error("clk_get_by_name() failed: %d\n", ret);
return ret;
}
-#else
+
+#ifndef CONFIG_TEGRA186
+   /*
+* We don't have a binding for pinmux yet. Leave it out for now. So
+* far no one needs anything other than the default.
+*/
i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
-   i2c_bus->periph_id = clock_decode_periph_id(blob, node);
 
   

[U-Boot] [PATCH 17/21] reset: implement a driver for the Tegra CAR

[Stephen Warren]

From: Stephen Warren 

Implement a reset uclass driver for the Tegra CAR. This allows clients to
use standard reset APIs on Tegra. This device is intended to be
instantiated by the core Tegra CAR driver, rather than being instantiated
directly from DT. The implementation uses the existing custom Tegra-
specific reset APIs to avoid coupling the series with significant
refactoring of the existing Tegra clock/reset code.

Signed-off-by: Stephen Warren 
---
 drivers/reset/Kconfig   |  7 
 drivers/reset/Makefile  |  1 +
 drivers/reset/tegra-car-reset.c | 72 +
 3 files changed, 80 insertions(+)
 create mode 100644 drivers/reset/tegra-car-reset.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 5b84f2178b71..4fcc0d95b4f1 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -20,6 +20,13 @@ config SANDBOX_RESET
  simply accepts requests to reset various HW modules without actually
  doing anything beyond a little error checking.
 
+config TEGRA_CAR_RESET
+   bool "Enable Tegra CAR-based reset driver"
+   depends on TEGRA_CAR
+   help
+ Enable support for manipulating Tegra's on-SoC reset signals via
+ direct register access to the Tegra CAR (Clock And Reset controller).
+
 config TEGRA186_RESET
bool "Enable Tegra186 BPMP-based reset driver"
depends on TEGRA186_BPMP
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index ff0e0907758b..5d4ea3d79dc4 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,4 +5,5 @@
 obj-$(CONFIG_DM_RESET) += reset-uclass.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
diff --git a/drivers/reset/tegra-car-reset.c b/drivers/reset/tegra-car-reset.c
new file mode 100644
index ..3147a50853a3
--- /dev/null
+++ b/drivers/reset/tegra-car-reset.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int tegra_car_reset_request(struct reset_ctl *reset_ctl)
+{
+   debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+   /* PERIPH_ID_COUNT varies per SoC */
+   if (reset_ctl->id >= PERIPH_ID_COUNT)
+   return -EINVAL;
+
+   return 0;
+}
+
+static int tegra_car_reset_free(struct reset_ctl *reset_ctl)
+{
+   debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+   return 0;
+}
+
+static int tegra_car_reset_assert(struct reset_ctl *reset_ctl)
+{
+   debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+   reset_set_enable(reset_ctl->id, 1);
+
+   return 0;
+}
+
+static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl)
+{
+   debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+   reset_set_enable(reset_ctl->id, 0);
+
+   return 0;
+}
+
+struct reset_ops tegra_car_reset_ops = {
+   .request = tegra_car_reset_request,
+   .free = tegra_car_reset_free,
+   .rst_assert = tegra_car_reset_assert,
+   .rst_deassert = tegra_car_reset_deassert,
+};
+
+static int tegra_car_reset_probe(struct udevice *dev)
+{
+   debug("%s(dev=%p)\n", __func__, dev);
+
+   return 0;
+}
+
+U_BOOT_DRIVER(tegra_car_reset) = {
+   .name = "tegra_car_reset",
+   .id = UCLASS_RESET,
+   .probe = tegra_car_reset_probe,
+   .ops = _car_reset_ops,
+};
-- 
2.9.3

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[U-Boot] [PATCH 16/21] misc: implement Tegra CAR core driver

[Stephen Warren]

From: Stephen Warren 

The Tegra CAR (Clock And Reset) module provides control of most clocks
and reset signals within the Tegra SoC. This change implements a driver
for this module. However, since the module implements multiple kinds of
services (clocks, resets, perhaps more), all this driver does is bind
various sub-devices, which in turn provide the real services. This driver
is essentially an "MFD" (Multi-Function Device) in Linux kernel speak.

Signed-off-by: Stephen Warren 
---
 drivers/misc/Kconfig |  7 +
 drivers/misc/Makefile|  1 +
 drivers/misc/tegra_car.c | 68 
 3 files changed, 76 insertions(+)
 create mode 100644 drivers/misc/tegra_car.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 899048983553..1aae4bcd07e1 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -129,6 +129,13 @@ config PCA9551_I2C_ADDR
help
  The I2C address of the PCA9551 LED controller.
 
+config TEGRA_CAR
+   bool "Enable support for the Tegra CAR driver"
+   depends on TEGRA_NO_BPMP
+   help
+ The Tegra CAR (Clock and Reset Controller) is a HW module that
+ controls almost all clocks and resets in a Tegra SoC.
+
 config TEGRA186_BPMP
bool "Enable support for the Tegra186 BPMP driver"
depends on TEGRA186
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index c0e5f03f8cbd..c9b2590453ad 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
 endif
 endif
 obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
+obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
 obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/drivers/misc/tegra_car.c b/drivers/misc/tegra_car.c
new file mode 100644
index ..0eb009657c43
--- /dev/null
+++ b/drivers/misc/tegra_car.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * The CAR exposes multiple different services. We create a sub-device for
+ * each separate type of service, since each device must be of the appropriate
+ * UCLASS.
+ */
+static int tegra_car_bpmp_bind(struct udevice *dev)
+{
+   int ret;
+   struct udevice *child;
+
+   debug("%s(dev=%p)\n", __func__, dev);
+
+   ret = device_bind_driver_to_node(dev, "tegra_car_clk", "tegra_car_clk",
+dev->of_offset, );
+   if (ret)
+   return ret;
+
+   ret = device_bind_driver_to_node(dev, "tegra_car_reset",
+"tegra_car_reset", dev->of_offset,
+);
+   if (ret)
+   return ret;
+
+   return 0;
+}
+
+static int tegra_car_bpmp_probe(struct udevice *dev)
+{
+   debug("%s(dev=%p)\n", __func__, dev);
+
+   return 0;
+}
+
+static int tegra_car_bpmp_remove(struct udevice *dev)
+{
+   debug("%s(dev=%p)\n", __func__, dev);
+
+   return 0;
+}
+
+static const struct udevice_id tegra_car_bpmp_ids[] = {
+   { .compatible = "nvidia,tegra20-car" },
+   { .compatible = "nvidia,tegra30-car" },
+   { .compatible = "nvidia,tegra114-car" },
+   { .compatible = "nvidia,tegra124-car" },
+   { .compatible = "nvidia,tegra210-car" },
+   { }
+};
+
+U_BOOT_DRIVER(tegra_car_bpmp) = {
+   .name   = "tegra_car",
+   .id = UCLASS_MISC,
+   .of_match   = tegra_car_bpmp_ids,
+   .bind   = tegra_car_bpmp_bind,
+   .probe  = tegra_car_bpmp_probe,
+   .remove = tegra_car_bpmp_remove,
+};
-- 
2.9.3

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[U-Boot] [PATCH 14/21] ARM: tegra: add peripheral clock init table

[Stephen Warren]

From: Stephen Warren 

Currently, Tegra peripheral drivers control two aspects of their HW module
clock(s):

1) The clock enable/rate for the peripheral clock itself.

2) The system-level clock tree setup, i.e. the clock parent.

Aspect 1 is reasonable, but aspect 2 is a system-level decision, not
something that an individual peripheral driver should in general know
about or influence. Such system-level knowledge ties the driver to a
specific SoC implementation, even when they use generic APIs for clock
manipulation, since they must have SoC-specific knowledge such as parent
clock IDs. Limited exceptions exist, such as where peripheral HW is
expected to dynamically switch between clock sources at run-time, such
as CPU clock scaling or display clock conflict management in a multi-head
scenario.

This patch enhances the Tegra core code to perform system-level clock
tree setup, in a similar fashion to the Linux kernel Tegra clock driver.
This will allow future patches to simplify peripheral drivers by removing
the clock parent setup logic.

This change is required prior to converting peripheral drivers to use the
standard clock APIs, since:

1) The clock uclass doesn't currently support a set_parent() operation.
Adding one is possible, but not necessary at the moment.

2) The clock APIs retrieve all clock IDs from device tree, and the DT
bindings for almost all peripherals only includes information about the
relevant peripheral clocks, and not any potential parent clocks.

Signed-off-by: Stephen Warren 
---
 arch/arm/include/asm/arch-tegra/clock.h |  6 ++
 arch/arm/mach-tegra/clock.c | 15 +++
 arch/arm/mach-tegra/tegra114/clock.c| 23 +++
 arch/arm/mach-tegra/tegra124/clock.c| 23 +++
 arch/arm/mach-tegra/tegra20/clock.c | 21 +
 arch/arm/mach-tegra/tegra210/clock.c| 23 +++
 arch/arm/mach-tegra/tegra30/clock.c | 23 +++
 7 files changed, 134 insertions(+)

diff --git a/arch/arm/include/asm/arch-tegra/clock.h 
b/arch/arm/include/asm/arch-tegra/clock.h
index 7daf8bc1632a..e0737f574add 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -362,6 +362,12 @@ struct clk_pll_info {
 };
 extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
 
+struct periph_clk_init {
+   enum periph_id periph_id;
+   enum clock_id parent_clock_id;
+};
+extern struct periph_clk_init periph_clk_init_table[];
+
 /**
  * Enable output clock for external peripherals
  *
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 36eabc8f5721..597f6286d6c1 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -612,6 +612,8 @@ int clock_verify(void)
 
 void clock_init(void)
 {
+   int i;
+
pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
@@ -630,6 +632,19 @@ void clock_init(void)
debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+
+   for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
+   enum periph_id periph_id;
+   enum clock_id parent;
+   int source, mux_bits, divider_bits;
+
+   periph_id = periph_clk_init_table[i].periph_id;
+   parent = periph_clk_init_table[i].parent_clock_id;
+
+   source = get_periph_clock_source(periph_id, parent, _bits,
+_bits);
+   clock_ll_set_source_bits(periph_id, mux_bits, source);
+   }
 }
 
 static void set_avp_clock_source(u32 src)
diff --git a/arch/arm/mach-tegra/tegra114/clock.c 
b/arch/arm/mach-tegra/tegra114/clock.c
index e6ef873c8dc4..6620206be0ba 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -699,3 +699,26 @@ void arch_timer_init(void)
writel(val, >cntcr);
debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
 }
+
+struct periph_clk_init periph_clk_init_table[] = {
+   { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
+   { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
+   { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+   { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
+   { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
+   { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+   { 

[U-Boot] [PATCH 15/21] ARM: tegra: add APIs the clock uclass driver will need

[Stephen Warren]

From: Stephen Warren 

A future patch will implement a clock uclass driver for Tegra. That driver
will call into Tegra's existing clock code to simplify the transition;
this avoids tieing the clock uclass patches into significant refactoring
of the existing custom clock API implementation.

Some of the Tegra clock APIs that manipulate peripheral clocks require
both the peripheral clock ID and parent clock ID to be passed in together.
However, the clock uclass API does not require any such "parent"
parameter, so the clock driver must determine this information itself.
This patch implements new Tegra- specific clock API
clock_get_periph_parent() for this purpose.

The new API is implemented in the core Tegra clock code rather than SoC-
specific clock code. The implementation uses various SoC-/clock-specific
data. That data is only available in SoC-specific clock code.
Consequently, two new internal APIs are added that enable the core clock
code to retrieve this information from the SoC-specific clock code. Due to
the structure of the Tegra clock code, this leads to some unfortunate code
duplication. However, this situation predates this patch.

Ideally, future work will de-duplicate the Tegra clock code, and migrate
it into drivers/clk/tegra. However, such refactoring is kept separate from
this series.

Signed-off-by: Stephen Warren 
---
 arch/arm/include/asm/arch-tegra/clock.h | 40 +
 arch/arm/mach-tegra/clock.c | 37 
 arch/arm/mach-tegra/tegra114/clock.c| 64 ---
 arch/arm/mach-tegra/tegra124/clock.c| 64 ---
 arch/arm/mach-tegra/tegra20/clock.c | 76 +++--
 arch/arm/mach-tegra/tegra210/clock.c| 64 ---
 arch/arm/mach-tegra/tegra30/clock.c | 64 ---
 7 files changed, 323 insertions(+), 86 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/clock.h 
b/arch/arm/include/asm/arch-tegra/clock.h
index e0737f574add..388afcb72316 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -187,6 +187,16 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, 
unsigned source,
unsigned divisor);
 
 /**
+ * Returns the current parent clock ID of a given peripheral. This can be
+ * useful in order to call clock_*_periph_*() from generic code that has no
+ * specific knowledge of system-level clock tree structure.
+ *
+ * @param periph_idperipheral to query
+ * @return clock ID of the peripheral's current parent clock
+ */
+enum clock_id clock_get_periph_parent(enum periph_id periph_id);
+
+/**
  * Start a peripheral PLL clock at the given rate. This also resets the
  * peripheral.
  *
@@ -284,6 +294,36 @@ u32 *get_periph_source_reg(enum periph_id periph_id);
 /* Returns a pointer to the given 'simple' PLL */
 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
 
+/*
+ * Given a peripheral ID, determine where the mux bits are in the peripheral
+ * clock's register, the number of divider bits the clock has, and the SoC-
+ * specific clock type.
+ *
+ * This is an internal API between the core Tegra clock code and the SoC-
+ * specific clock code.
+ *
+ * @param periph_id peripheral to query
+ * @param mux_bits  Set to number of bits in mux register
+ * @param divider_bits  Set to the relevant MASK_BITS_* value
+ * @param type  Set to the SoC-specific clock type
+ * @return 0 on success, -1 on error
+ */
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+ int *divider_bits, int *type);
+
+/*
+ * Given a peripheral ID and clock source mux value, determine the clock_id
+ * of that peripheral's parent.
+ *
+ * This is an internal API between the core Tegra clock code and the SoC-
+ * specific clock code.
+ *
+ * @param periph_id peripheral to query
+ * @param sourceraw clock source mux value
+ * @return the CLOCK_ID_* value @source represents
+ */
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source);
+
 /**
  * Given a peripheral ID and the required source clock, this returns which
  * value should be programmed into the source mux for that peripheral.
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 597f6286d6c1..cf8bc38925d2 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -206,6 +206,29 @@ int clock_ll_set_source_bits(enum periph_id periph_id, int 
mux_bits,
return 0;
 }
 
+static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
+{
+   u32 *reg = get_periph_source_reg(periph_id);
+   u32 val = readl(reg);
+
+   switch (mux_bits) {
+   case MASK_BITS_31_30:
+   val >>= OUT_CLK_SOURCE_31_30_SHIFT;
+   val &= OUT_CLK_SOURCE_31_30_MASK;
+   return val;
+   case MASK_BITS_31_29:
+

[U-Boot] [PATCH 13/21] ARM: tegra: pull Tegra210 SoC DT from Linux v4.7

[Stephen Warren]

From: Stephen Warren 

The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.

Main changes:
* Brought in the correct Tegra210 CAR binding; the old file in U-Boot
  appears to be a renamed version of the Tegra124 bindings rather than
  the real Tegra210 version.
* Conversion of SPI and UART nodes to standard DMA bindings. U-Boot
  doesn't use DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
  information required by U-Boot, so U-Boot is not affected.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot, including separation of the
  Tegra LIC (Legacy IRQ controller) and GIC.
* Node sort order fixes.

Remaining deltas relative to the Linux DT:
* U-Boot has enabled PCIe for Tegra210, but the kernel hasn't yet.
* The GPIO node compatible value in the kernel explicitly includes
  Tegra124 values whereas U-Boot does not. I'll send a kernel patch to
  correct this.

Signed-off-by: Stephen Warren 
---
 arch/arm/dts/tegra210.dtsi   | 693 +++
 include/dt-bindings/clock/tegra210-car.h | 403 ++
 include/dt-bindings/memory/tegra210-mc.h |  36 ++
 3 files changed, 880 insertions(+), 252 deletions(-)
 create mode 100644 include/dt-bindings/memory/tegra210-mc.h

diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi
index fd4cc793d906..229fed04529a 100644
--- a/arch/arm/dts/tegra210.dtsi
+++ b/arch/arm/dts/tegra210.dtsi
@@ -1,14 +1,13 @@
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
-#include "skeleton.dtsi"
-
 / {
compatible = "nvidia,tegra210";
-   interrupt-parent = <>;
+   interrupt-parent = <>;
#address-cells = <2>;
#size-cells = <2>;
 
@@ -78,6 +77,201 @@
};
};
 
+   host1x@5000 {
+   compatible = "nvidia,tegra210-host1x", "simple-bus";
+   reg = <0x0 0x5000 0x0 0x00034000>;
+   interrupts = , /* syncpt */
+; /* general */
+   clocks = <_car TEGRA210_CLK_HOST1X>;
+   clock-names = "host1x";
+   resets = <_car 28>;
+   reset-names = "host1x";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   ranges = <0x0 0x5400 0x0 0x5400 0x0 0x0100>;
+
+   dpaux1: dpaux@5404 {
+   compatible = "nvidia,tegra210-dpaux";
+   reg = <0x0 0x5404 0x0 0x0004>;
+   interrupts = ;
+   clocks = <_car TEGRA210_CLK_DPAUX1>,
+<_car TEGRA210_CLK_PLL_DP>;
+   clock-names = "dpaux", "parent";
+   resets = <_car 207>;
+   reset-names = "dpaux";
+   status = "disabled";
+   };
+
+   vi@5408 {
+   compatible = "nvidia,tegra210-vi";
+   reg = <0x0 0x5408 0x0 0x0004>;
+   interrupts = ;
+   status = "disabled";
+   };
+
+   tsec@5410 {
+   compatible = "nvidia,tegra210-tsec";
+   reg = <0x0 0x5410 0x0 0x0004>;
+   };
+
+   dc@5420 {
+   compatible = "nvidia,tegra210-dc";
+   reg = <0x0 0x5420 0x0 0x0004>;
+   interrupts = ;
+   clocks = <_car TEGRA210_CLK_DISP1>,
+<_car TEGRA210_CLK_PLL_P>;
+   clock-names = "dc", "parent";
+   resets = <_car 27>;
+   reset-names = "dc";
+
+   iommus = < TEGRA_SWGROUP_DC>;
+
+   nvidia,head = <0>;
+   };
+
+   dc@5424 {
+   compatible = "nvidia,tegra210-dc";
+   reg = <0x0 0x5424 0x0 0x0004>;
+   interrupts = ;
+   clocks = <_car TEGRA210_CLK_DISP2>,
+<_car TEGRA210_CLK_PLL_P>;
+   clock-names = "dc", "parent";
+   resets = <_car 26>;
+   reset-names = "dc";
+
+   iommus = < TEGRA_SWGROUP_DCB>;
+
+   nvidia,head = <1>;
+   };
+
+   dsi@5430 {
+   compatible = "nvidia,tegra210-dsi";
+   reg = <0x0 0x5430 0x0 0x0004>;
+   clocks = <_car TEGRA210_CLK_DSIA>,
+<_car TEGRA210_CLK_DSIALP>,
+ 

[U-Boot] [PATCH 11/21] ARM: tegra: pull Tegra114 SoC DT from Linux v4.7

[Stephen Warren]

From: Stephen Warren 

The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.

Main changes:
* Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use
  DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
  information required by U-Boot, so U-Boot is not affected.
* Boards need to define the clk32k_in clock that feeds the Tegra PMC.
* Addition of tegra114-mc.h since tegra114.dtsi now includes it.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot.
* Node sort order fixes.

Remaining deltas relative to the Linux DT:
* USB node compatible values in U-Boot explicitly list Tegra114 values
  whereas the kernel does not. I'll send a kernel patch to correct this.

Signed-off-by: Stephen Warren 
---
 arch/arm/dts/tegra114-dalmore.dts|  13 +
 arch/arm/dts/tegra114.dtsi   | 743 +--
 include/dt-bindings/clock/tegra114-car.h |   5 +-
 include/dt-bindings/memory/tegra114-mc.h |  25 ++
 4 files changed, 655 insertions(+), 131 deletions(-)
 create mode 100644 include/dt-bindings/memory/tegra114-mc.h

diff --git a/arch/arm/dts/tegra114-dalmore.dts 
b/arch/arm/dts/tegra114-dalmore.dts
index 9325149cba6f..5f4df88f849b 100644
--- a/arch/arm/dts/tegra114-dalmore.dts
+++ b/arch/arm/dts/tegra114-dalmore.dts
@@ -79,4 +79,17 @@
nvidia,vbus-gpio = < TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+   clocks {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   clk32k_in: clock@0 {
+   compatible = "fixed-clock";
+   reg=<0>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+   };
 };
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 88bdc4904508..8932ea3afd5f 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -1,53 +1,222 @@
 #include 
 #include 
+#include 
+#include 
 #include 
 
 #include "skeleton.dtsi"
 
 / {
compatible = "nvidia,tegra114";
+   interrupt-parent = <>;
 
-   tegra_car: clock {
+   host1x@5000 {
+   compatible = "nvidia,tegra114-host1x", "simple-bus";
+   reg = <0x5000 0x00028000>;
+   interrupts = , /* syncpt */
+; /* general */
+   clocks = <_car TEGRA114_CLK_HOST1X>;
+   resets = <_car 28>;
+   reset-names = "host1x";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   ranges = <0x5400 0x5400 0x0100>;
+
+   gr2d@5414 {
+   compatible = "nvidia,tegra114-gr2d", 
"nvidia,tegra20-gr2d";
+   reg = <0x5414 0x0004>;
+   interrupts = ;
+   clocks = <_car TEGRA114_CLK_GR2D>;
+   resets = <_car 21>;
+   reset-names = "2d";
+   };
+
+   gr3d@5418 {
+   compatible = "nvidia,tegra114-gr3d", 
"nvidia,tegra20-gr3d";
+   reg = <0x5418 0x0004>;
+   clocks = <_car TEGRA114_CLK_GR3D>;
+   resets = <_car 24>;
+   reset-names = "3d";
+   };
+
+   dc@5420 {
+   compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+   reg = <0x5420 0x0004>;
+   interrupts = ;
+   clocks = <_car TEGRA114_CLK_DISP1>,
+<_car TEGRA114_CLK_PLL_P>;
+   clock-names = "dc", "parent";
+   resets = <_car 27>;
+   reset-names = "dc";
+
+   iommus = < TEGRA_SWGROUP_DC>;
+
+   nvidia,head = <0>;
+
+   rgb {
+   status = "disabled";
+   };
+   };
+
+   dc@5424 {
+   compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+   reg = <0x5424 0x0004>;
+   interrupts = ;
+   clocks = <_car TEGRA114_CLK_DISP2>,
+<_car TEGRA114_CLK_PLL_P>;
+   clock-names = "dc", "parent";
+   resets = <_car 26>;
+   reset-names = "dc";
+
+   iommus = < TEGRA_SWGROUP_DCB>;
+
+   nvidia,head = <1>;
+
+   rgb {
+  

[U-Boot] [PATCH 12/21] ARM: tegra: pull Tegra124 SoC DT from Linux v4.7

[Stephen Warren]

From: Stephen Warren 

The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.

Main changes:
* USB phy_type property is aligned with the kernel, so board files are
  updated so the final DT content doesn't change. I'm not convinved that
  Nyan uses HSIC phy_type. However, I'd rather this change be a no-op,
  and any DT bug-fixes be separate.
* Sync misc changes from the kernel: missing DT content, minor compatible
  value fixes, typos.

Remaining deltas relative to the Linux DT:
* U-Boot uses #address-cells/#size-cells of 1 whereas the kernel uses 2.
  I believe U-Boot's DT parsing currently assumes that these values match
  the physical address size, so I didn't synchronize this part of the DT.
* U-Boot uses the original XUSB PHY DT binding, wherease the kernel DT
  has moved to a newer version. Thus, XUSB client nodes include properties
  names phys and phy-names that do not appear in the kernel, and don't
  include pad definitions in the padctl node.

Signed-off-by: Stephen Warren 
---
 arch/arm/dts/tegra124-nyan.dtsi |  2 +
 arch/arm/dts/tegra124.dtsi  | 59 ++---
 include/dt-bindings/thermal/tegra124-soctherm.h |  1 +
 3 files changed, 55 insertions(+), 7 deletions(-)

diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi
index 780131f7361c..51895e4816c4 100644
--- a/arch/arm/dts/tegra124-nyan.dtsi
+++ b/arch/arm/dts/tegra124-nyan.dtsi
@@ -424,10 +424,12 @@
 
usb@7d004000 { /* Internal webcam. */
status = "okay";
+   phy_type = "hsic";
};
 
usb-phy@7d004000 {
status = "okay";
+   phy_type = "hsic";
vbus-supply = <_run_cam>;
};
 
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index 275a509f753e..83d63480471b 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -196,13 +196,18 @@
 
lic: interrupt-controller@60004000 {
compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
+   reg = <0x0 0x60004000 0x0 0x100>,
+ <0x0 0x60004100 0x0 0x100>,
+ <0x0 0x60004200 0x0 0x100>,
+ <0x0 0x60004300 0x0 0x100>,
+ <0x0 0x60004400 0x0 0x100>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <>;
};
 
timer@60005000 {
-   compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
+   compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", 
"nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
interrupts = ,
 ,
@@ -316,7 +321,7 @@
 * driver and APB DMA based serial driver for higher baudrate
 * and performace. To enable the 8250 based driver, the compatible
 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
-* the APB DMA based serial driver, the comptible is
+* the APB DMA based serial driver, the compatible is
 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 */
uarta: serial@70006000 {
@@ -399,10 +404,15 @@
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
-   interrupts = <0 84 0x04>;
+   interrupts = ;
#address-cells = <1>;
#size-cells = <0>;
-   clocks = <_car 54>;
+   clocks = <_car TEGRA124_CLK_I2C2>;
+   clock-names = "div-clk";
+   resets = <_car 54>;
+   reset-names = "i2c";
+   dmas = < 22>, < 22>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
@@ -631,6 +641,41 @@
status = "disabled";
};
 
+   usb@7009 {
+   compatible = "nvidia,tegra124-xusb";
+   reg = <0x7009 0x8000>,
+ <0x70098000 0x1000>,
+ <0x70099000 0x1000>;
+   reg-names = "hcd", "fpci", "ipfs";
+
+   interrupts = ,
+;
+
+   clocks = <_car TEGRA124_CLK_XUSB_HOST>,
+<_car TEGRA124_CLK_XUSB_HOST_SRC>,
+<_car TEGRA124_CLK_XUSB_FALCON_SRC>,
+<_car TEGRA124_CLK_XUSB_SS>,
+<_car TEGRA124_CLK_XUSB_SS_DIV2>,
+<_car TEGRA124_CLK_XUSB_SS_SRC>,
+<_car TEGRA124_CLK_XUSB_HS_SRC>,
+<_car TEGRA124_CLK_XUSB_FS_SRC>,
+<_car TEGRA124_CLK_PLL_U_480M>,
+<_car 

[U-Boot] [PATCH 10/21] ARM: tegra: pull Tegra30 SoC DT from Linux v4.7

[Stephen Warren]

From: Stephen Warren 

The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.

Main changes:
* Modification of PCIe memory region addresses. The HW memory layout is
  programmable, so this should work fine, and Beaver PCIe was tested
  without issue.
* Removal of pcie_xclk from the PCIe node and clock binding header. This
  clock doesn't exist and isn't used; only a reset with this ID exists.
* Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use
  DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
  information required by U-Boot, so U-Boot is not affected.
* Changed the phy_type value for the second USB port. This required board
  DTs to be updated to keep the same configuration.
* Boards need to define the clk32k_in clock that feeds the Tegra PMC.
* Addition of tegra30-mc.h since tegra30.dtsi now includes it.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot.
* Node sort order fixes.

Remaining deltas relative to the Linux DT:
* None.

Signed-off-by: Stephen Warren 
---
 arch/arm/dts/tegra30-apalis.dts |  21 +-
 arch/arm/dts/tegra30-beaver.dts |  13 +
 arch/arm/dts/tegra30-cardhu.dts |  13 +
 arch/arm/dts/tegra30-colibri.dts|  14 +-
 arch/arm/dts/tegra30-tamonten.dtsi  |  12 +
 arch/arm/dts/tegra30.dtsi   | 828 ++--
 include/dt-bindings/clock/tegra30-car.h |   2 +-
 include/dt-bindings/memory/tegra30-mc.h |  24 +
 8 files changed, 783 insertions(+), 144 deletions(-)
 create mode 100644 include/dt-bindings/memory/tegra30-mc.h

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 60e87a4f3af5..f83f09475ecd 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -277,7 +277,6 @@
status = "okay";
/* USBH_EN */
nvidia,vbus-gpio = < TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
-   phy_type = "utmi";
};
 
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -287,6 +286,26 @@
nvidia,vbus-gpio = < TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};
 
+   clocks {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   clk32k_in: clk@0 {
+   compatible = "fixed-clock";
+   reg=<0>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+   clk16m: clk@1 {
+   compatible = "fixed-clock";
+   reg=<1>;
+   #clock-cells = <0>;
+   clock-frequency = <1600>;
+   clock-output-names = "clk16m";
+   };
+   };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index 340fcaf845c7..4a32fcf44a8b 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -219,6 +219,19 @@
status = "okay";
};
 
+   clocks {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   clk32k_in: clock@0 {
+   compatible = "fixed-clock";
+   reg=<0>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+   };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts
index 2237682e0ebd..70fd916f1a00 100644
--- a/arch/arm/dts/tegra30-cardhu.dts
+++ b/arch/arm/dts/tegra30-cardhu.dts
@@ -202,6 +202,19 @@
status = "okay";
};
 
+   clocks {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   clk32k_in: clock@0 {
+   compatible = "fixed-clock";
+   reg=<0>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+   };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts
index 8784cd20b4c4..3cff2f62e62e 100644
--- a/arch/arm/dts/tegra30-colibri.dts
+++ b/arch/arm/dts/tegra30-colibri.dts
@@ -84,7 +84,6 @@
status = "okay";
/* VBUS_LAN */
nvidia,vbus-gpio = < TEGRA_GPIO(DD, 2) 

[U-Boot] [PATCH 07/21] mmc: tegra: Add DM_MMC support to Tegra MMC driver

[Stephen Warren]

From: Tom Warren 

Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed
to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds.

Cc: Jaehoon Chung 
Signed-off-by: Tom Warren 
(swarren, fixed some NULL pointer dereferences, removed extraneous
changes, rebased on various other changes, removed non-DM support etc.)
Signed-off-by: Stephen Warren 
---
 arch/arm/include/asm/arch-tegra/mmc.h |  11 --
 arch/arm/mach-tegra/Kconfig   |   1 +
 arch/arm/mach-tegra/board186.c|   8 -
 arch/arm/mach-tegra/board2.c  |  16 --
 drivers/mmc/tegra_mmc.c   | 277 +-
 5 files changed, 70 insertions(+), 243 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-tegra/mmc.h

diff --git a/arch/arm/include/asm/arch-tegra/mmc.h 
b/arch/arm/include/asm/arch-tegra/mmc.h
deleted file mode 100644
index c2d52b297743..
--- a/arch/arm/include/asm/arch-tegra/mmc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2011, Google Inc. All rights reserved.
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef _TEGRA_MMC_H_
-#define _TEGRA_MMC_H_
-
-void tegra_mmc_init(void);
-
-#endif /* _TEGRA_MMC_H_ */
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1eaf40627254..448c31902d50 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -15,6 +15,7 @@ config TEGRA_COMMON
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
+   select DM_MMC
select DM_PCI
select DM_PCI_COMPAT
select DM_PWM
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
index 356556618907..691c3fd98dab 100644
--- a/arch/arm/mach-tegra/board186.c
+++ b/arch/arm/mach-tegra/board186.c
@@ -6,7 +6,6 @@
 
 #include 
 #include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -34,10 +33,3 @@ int board_late_init(void)
 {
return tegra_soc_board_init_late();
 }
-
-int board_mmc_init(bd_t *bd)
-{
-   tegra_mmc_init();
-
-   return 0;
-}
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 3f87891b25c8..cb9503f8e61f 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -32,9 +32,6 @@
 #ifdef CONFIG_USB_EHCI_TEGRA
 #include 
 #endif
-#ifdef CONFIG_TEGRA_MMC
-#include 
-#endif
 #include 
 #include 
 #include 
@@ -234,19 +231,6 @@ int board_late_init(void)
return 0;
 }
 
-#if defined(CONFIG_TEGRA_MMC)
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-   debug("%s called\n", __func__);
-
-   debug("%s: init MMC\n", __func__);
-   tegra_mmc_init();
-
-   return 0;
-}
-#endif /* MMC */
-
 /*
  * In some SW environments, a memory carve-out exists to house a secure
  * monitor, a trusted OS, and/or various statically allocated media buffers.
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 9287f1c3424f..7b9628adb96e 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang 
  * Jaehoon Chung 
- * Portions Copyright 2011-2015 NVIDIA Corporation
+ * Portions Copyright 2011-2016 NVIDIA Corporation
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -17,7 +17,6 @@
 #include 
 #include 
 #endif
-#include 
 #include 
 #include 
 
@@ -34,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct tegra_mmc_priv {
struct tegra_mmc *reg;
-   int id; /* device id/number, 0-3 */
-   int enabled;/* 1 to enable, 0 to disable */
-   int width;  /* Bus Width, 1, 4 or 8 */
 #ifdef CONFIG_TEGRA186
struct reset_ctl reset_ctl;
struct clk clk;
@@ -49,14 +45,9 @@ struct tegra_mmc_priv {
unsigned int version;   /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
struct mmc_config cfg;  /* mmc configuration */
+   struct mmc *mmc;
 };
 
-struct tegra_mmc_priv mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
-
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
-#error "Please enable device tree support to use this driver"
-#endif
-
 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
unsigned short power)
 {
@@ -534,11 +525,11 @@ static void tegra_mmc_reset(struct tegra_mmc_priv *priv, 
struct mmc *mmc)
tegra_mmc_pad_init(priv);
 }
 
-static int tegra_mmc_core_init(struct mmc *mmc)
+static int tegra_mmc_init(struct mmc *mmc)
 {
struct tegra_mmc_priv *priv = mmc->priv;
unsigned int mask;
-   debug(" mmc_core_init called\n");
+   debug(" tegra_mmc_init called\n");
 
tegra_mmc_reset(priv, mmc);
 
@@ -594,59 +585,30 @@ static int tegra_mmc_getcd(struct mmc *mmc)
 static const struct mmc_ops tegra_mmc_ops = {
.send_cmd   = tegra_mmc_send_cmd,

[U-Boot] [PATCH 09/21] ARM: tegra: pull Tegra20 SoC DT from Linux v4.7

[Stephen Warren]

From: Stephen Warren 

This brings in a few minor fixes since the last sync. The largest change
is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock
doesn't actually exist.

Remaining deltas:
* Addition of u-boot,dm-pre-reloc property to a couple of nodes.
* Addition of the NAND controller, which Linux doesn't yet support.

Signed-off-by: Stephen Warren 
---
 arch/arm/dts/tegra20.dtsi   | 4 ++--
 include/dt-bindings/clock/tegra20-car.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 31223e4fc9aa..84bb1b0215c8 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -147,7 +147,7 @@
interrupt-parent = <>;
reg = <0x50040600 0x20>;
interrupts = ;
+   (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <_car TEGRA20_CLK_TWD>;
};
 
@@ -311,7 +311,7 @@
 * driver and APB DMA based serial driver for higher baudrate
 * and performace. To enable the 8250 based driver, the compatible
 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
-* driver, the comptible is "nvidia,tegra20-hsuart".
+* driver, the compatible is "nvidia,tegra20-hsuart".
 */
uarta: serial@70006000 {
compatible = "nvidia,tegra20-uart";
diff --git a/include/dt-bindings/clock/tegra20-car.h 
b/include/dt-bindings/clock/tegra20-car.h
index a1ae9a8fdd6c..04500b243a4d 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -49,7 +49,7 @@
 /* 30 */
 #define TEGRA20_CLK_CACHE2 31
 
-#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_MC 32
 #define TEGRA20_CLK_AHBDMA 33
 #define TEGRA20_CLK_APBDMA 34
 /* 35 */
@@ -92,7 +92,7 @@
 #define TEGRA20_CLK_OWR 71
 #define TEGRA20_CLK_AFI 72
 #define TEGRA20_CLK_CSITE 73
-#define TEGRA20_CLK_PCIE_XCLK 74
+/* 74 */
 #define TEGRA20_CLK_AVPUCQ 75
 #define TEGRA20_CLK_LA 76
 /* 77 */
-- 
2.9.3

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[U-Boot] [PATCH 08/21] ARM: tegra: remove "0, " from DT unit addresses

[Stephen Warren]

From: Stephen Warren 

Apparently the unit address in a DT node name is now supposed to be a
single integer value, rather than a comma-separated list of individual
cell values. Fix the U-Boot DTs to comply with this naming convention.

Signed-off-by: Stephen Warren 
---
 arch/arm/dts/tegra124-nyan-big.dts   |  8 +++---
 arch/arm/dts/tegra124-nyan.dtsi  |  4 +--
 arch/arm/dts/tegra210-e2220-1170.dts | 16 +--
 arch/arm/dts/tegra210-p2371-.dts | 16 +--
 arch/arm/dts/tegra210-p2371-2180.dts | 20 +++---
 arch/arm/dts/tegra210-p2571.dts  | 48 -
 arch/arm/dts/tegra210.dtsi   | 52 ++--
 7 files changed, 82 insertions(+), 82 deletions(-)

diff --git a/arch/arm/dts/tegra124-nyan-big.dts 
b/arch/arm/dts/tegra124-nyan-big.dts
index a0f1d09bee58..3758395c6f76 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -15,8 +15,8 @@
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
-   rtc0 = "/i2c@0,7000d000/pmic@40";
-   rtc1 = "/rtc@0,7000e000";
+   rtc0 = "/i2c@7000d000/pmic@40";
+   rtc1 = "/rtc@7000e000";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
@@ -58,7 +58,7 @@
ddc-i2c-bus = <>;
};
 
-   sdhci@0,700b0400 { /* SD Card on this bus */
+   sdhci@700b0400 { /* SD Card on this bus */
wp-gpios = < TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
};
 
@@ -69,7 +69,7 @@
nvidia,model = "GoogleNyanBig";
};
 
-   pinmux@0,7868 {
+   pinmux@7868 {
pinctrl-names = "default";
pinctrl-0 = <_default>;
 
diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi
index 1b6931fae806..780131f7361c 100644
--- a/arch/arm/dts/tegra124-nyan.dtsi
+++ b/arch/arm/dts/tegra124-nyan.dtsi
@@ -3,8 +3,8 @@
 
 / {
aliases {
-   rtc0 = "/i2c@0,7000d000/pmic@40";
-   rtc1 = "/rtc@0,7000e000";
+   rtc0 = "/i2c@7000d000/pmic@40";
+   rtc1 = "/rtc@7000e000";
serial0 = 
};
 
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts 
b/arch/arm/dts/tegra210-e2220-1170.dts
index 69af9cfe2a3d..70cd72b56103 100644
--- a/arch/arm/dts/tegra210-e2220-1170.dts
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -11,35 +11,35 @@
};
 
aliases {
-   i2c0 = "/i2c@0,7000d000";
-   mmc0 = "/sdhci@0,700b0600";
-   mmc1 = "/sdhci@0,700b";
-   usb0 = "/usb@0,7d00";
+   i2c0 = "/i2c@7000d000";
+   mmc0 = "/sdhci@700b0600";
+   mmc1 = "/sdhci@700b";
+   usb0 = "/usb@7d00";
};
 
memory {
reg = <0x0 0x8000 0x0 0xc000>;
};
 
-   sdhci@0,700b {
+   sdhci@700b {
status = "okay";
cd-gpios = < TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = < TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
 
-   sdhci@0,700b0600 {
+   sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
 
-   i2c@0,7000d000 {
+   i2c@7000d000 {
status = "okay";
clock-frequency = <40>;
};
 
-   usb@0,7d00 {
+   usb@7d00 {
status = "okay";
dr_mode = "peripheral";
};
diff --git a/arch/arm/dts/tegra210-p2371-.dts 
b/arch/arm/dts/tegra210-p2371-.dts
index 44315476275f..d9612962bd8c 100644
--- a/arch/arm/dts/tegra210-p2371-.dts
+++ b/arch/arm/dts/tegra210-p2371-.dts
@@ -11,35 +11,35 @@
};
 
aliases {
-   i2c0 = "/i2c@0,7000d000";
-   mmc0 = "/sdhci@0,700b0600";
-   mmc1 = "/sdhci@0,700b";
-   usb0 = "/usb@0,7d00";
+   i2c0 = "/i2c@7000d000";
+   mmc0 = "/sdhci@700b0600";
+   mmc1 = "/sdhci@700b";
+   usb0 = "/usb@7d00";
};
 
memory {
reg = <0x0 0x8000 0x0 0xc000>;
};
 
-   sdhci@0,700b {
+   sdhci@700b {
status = "okay";
cd-gpios = < TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = < TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
 
-   sdhci@0,700b0600 {
+   sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
 
-   i2c@0,7000d000 {
+   i2c@7000d000 {
status = "okay";
clock-frequency = 

[U-Boot] [PATCH 06/21] ARM: tegra: set MMC pin mux in board_init()

[Stephen Warren]

From: Stephen Warren 

Most other pin mux is configured in this function. This removes the
need to do it in an MMC-specific initialization function, which is good
since that function is going away later in this series.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/board2.c | 12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index e3cdb009ce92..3f87891b25c8 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -53,6 +53,7 @@ U_BOOT_DEVICE(tegra_gpios) = {
 __weak void pinmux_init(void) {}
 __weak void pin_mux_usb(void) {}
 __weak void pin_mux_spi(void) {}
+__weak void pin_mux_mmc(void) {}
 __weak void gpio_early_init_uart(void) {}
 __weak void pin_mux_display(void) {}
 __weak void start_cpu_fan(void) {}
@@ -127,6 +128,10 @@ int board_init(void)
pin_mux_spi();
 #endif
 
+#ifdef CONFIG_TEGRA_MMC
+   pin_mux_mmc();
+#endif
+
/* Init is handled automatically in the driver-model case */
 #if defined(CONFIG_DM_VIDEO)
pin_mux_display();
@@ -230,18 +235,11 @@ int board_late_init(void)
 }
 
 #if defined(CONFIG_TEGRA_MMC)
-__weak void pin_mux_mmc(void)
-{
-}
-
 /* this is a weak define that we are overriding */
 int board_mmc_init(bd_t *bd)
 {
debug("%s called\n", __func__);
 
-   /* Enable muxes, etc. for SDMMC controllers */
-   pin_mux_mmc();
-
debug("%s: init MMC\n", __func__);
tegra_mmc_init();
 
-- 
2.9.3

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[U-Boot] [PATCH 02/21] mmc: tegra: use correct alias for SDHCI/MMC nodes

[Stephen Warren]

From: Stephen Warren 

The Tegra MMC driver currently honors "sdhci" entries in /aliases. The
MMC core however uses "mmc" entries in /aliases. This difference will be
relevant once the Tegra MMC driver is converted to DM, and the MMC core
handles alias lookups. To avoid issues during that conversion, fix the
Tegra MMC driver and all Tegra DTs to use the same alias name as the MMC
core does.

Cc: Jaehoon Chung 
Signed-off-by: Stephen Warren 
---
 arch/arm/dts/tegra114-dalmore.dts |  4 ++--
 arch/arm/dts/tegra124-cei-tk1-som.dts |  4 ++--
 arch/arm/dts/tegra124-jetson-tk1.dts  |  4 ++--
 arch/arm/dts/tegra124-nyan-big.dts|  4 ++--
 arch/arm/dts/tegra124-venice2.dts |  4 ++--
 arch/arm/dts/tegra186-p2771-.dtsi |  4 ++--
 arch/arm/dts/tegra20-colibri.dts  |  2 +-
 arch/arm/dts/tegra20-harmony.dts  |  4 ++--
 arch/arm/dts/tegra20-medcom-wide.dts  |  2 +-
 arch/arm/dts/tegra20-paz00.dts|  4 ++--
 arch/arm/dts/tegra20-plutux.dts   |  2 +-
 arch/arm/dts/tegra20-seaboard.dts |  4 ++--
 arch/arm/dts/tegra20-tec.dts  |  2 +-
 arch/arm/dts/tegra20-trimslice.dts|  4 ++--
 arch/arm/dts/tegra20-ventana.dts  |  4 ++--
 arch/arm/dts/tegra20-whistler.dts |  4 ++--
 arch/arm/dts/tegra210-e2220-1170.dts  |  4 ++--
 arch/arm/dts/tegra210-p2371-.dts  |  4 ++--
 arch/arm/dts/tegra210-p2371-2180.dts  |  4 ++--
 arch/arm/dts/tegra210-p2571.dts   |  4 ++--
 arch/arm/dts/tegra30-apalis.dts   |  6 +++---
 arch/arm/dts/tegra30-beaver.dts   |  4 ++--
 arch/arm/dts/tegra30-cardhu.dts   |  4 ++--
 arch/arm/dts/tegra30-colibri.dts  |  4 ++--
 arch/arm/dts/tegra30-tamonten.dtsi|  6 +++---
 drivers/mmc/tegra_mmc.c   | 10 +-
 26 files changed, 53 insertions(+), 53 deletions(-)

diff --git a/arch/arm/dts/tegra114-dalmore.dts 
b/arch/arm/dts/tegra114-dalmore.dts
index f0331a740178..9325149cba6f 100644
--- a/arch/arm/dts/tegra114-dalmore.dts
+++ b/arch/arm/dts/tegra114-dalmore.dts
@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
-   sdhci0 = "/sdhci@78000600";
-   sdhci1 = "/sdhci@78000400";
+   mmc0 = "/sdhci@78000600";
+   mmc1 = "/sdhci@78000400";
usb0 = "/usb@7d00";
usb1 = "/usb@7d008000";
};
diff --git a/arch/arm/dts/tegra124-cei-tk1-som.dts 
b/arch/arm/dts/tegra124-cei-tk1-som.dts
index d22c0cabec7a..c4d4f9d89f12 100644
--- a/arch/arm/dts/tegra124-cei-tk1-som.dts
+++ b/arch/arm/dts/tegra124-cei-tk1-som.dts
@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
-   sdhci0 = "/sdhci@700b0600";
-   sdhci1 = "/sdhci@700b0400";
+   mmc0 = "/sdhci@700b0600";
+   mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d00";
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts 
b/arch/arm/dts/tegra124-jetson-tk1.dts
index 4a63b6d86160..f1db952355b8 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -16,8 +16,8 @@
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
-   sdhci0 = "/sdhci@700b0600";
-   sdhci1 = "/sdhci@700b0400";
+   mmc0 = "/sdhci@700b0600";
+   mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d00";
diff --git a/arch/arm/dts/tegra124-nyan-big.dts 
b/arch/arm/dts/tegra124-nyan-big.dts
index 20e0be30e980..a0f1d09bee58 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -17,8 +17,8 @@
i2c5 = "/i2c@7000d100";
rtc0 = "/i2c@0,7000d000/pmic@40";
rtc1 = "/rtc@0,7000e000";
-   sdhci0 = "/sdhci@700b0600";
-   sdhci1 = "/sdhci@700b0400";
+   mmc0 = "/sdhci@700b0600";
+   mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d00";
diff --git a/arch/arm/dts/tegra124-venice2.dts 
b/arch/arm/dts/tegra124-venice2.dts
index 6c39563bfc64..add9244e6874 100644
--- a/arch/arm/dts/tegra124-venice2.dts
+++ b/arch/arm/dts/tegra124-venice2.dts
@@ -17,8 +17,8 @@
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
-   sdhci0 = "/sdhci@700b0600";
-   sdhci1 = "/sdhci@700b0400";
+   mmc0 = "/sdhci@700b0600";
+   mmc1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
   

[U-Boot] [PATCH 03/21] mmc: tegra: move pad_init_mmc() into MMC driver

[Stephen Warren]

From: Stephen Warren 

pad_init_mmc() is performing an SoC-specific operation, using registers
within the MMC controller. There's no reason to implement this code
outside the MMC driver, so move it inside the driver.

Cc: Jaehoon Chung 
Signed-off-by: Stephen Warren 
---
 arch/arm/include/asm/arch-tegra/tegra_mmc.h |  2 --
 arch/arm/mach-tegra/board186.c  |  5 -
 arch/arm/mach-tegra/board2.c| 29 -
 drivers/mmc/tegra_mmc.c | 28 
 4 files changed, 28 insertions(+), 36 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h 
b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index 07ef4c04c858..fecb6599a844 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -151,7 +151,5 @@ struct mmc_host {
struct mmc_config cfg;  /* mmc configuration */
 };
 
-void pad_init_mmc(struct mmc_host *host);
-
 #endif /* __ASSEMBLY__ */
 #endif /* __TEGRA_MMC_H_ */
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
index 38261e421cc1..356556618907 100644
--- a/arch/arm/mach-tegra/board186.c
+++ b/arch/arm/mach-tegra/board186.c
@@ -7,7 +7,6 @@
 #include 
 #include 
 #include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -36,10 +35,6 @@ int board_late_init(void)
return tegra_soc_board_init_late();
 }
 
-void pad_init_mmc(struct mmc_host *host)
-{
-}
-
 int board_mmc_init(bd_t *bd)
 {
tegra_mmc_init();
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 9158ace44c42..e3cdb009ce92 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -33,7 +33,6 @@
 #include 
 #endif
 #ifdef CONFIG_TEGRA_MMC
-#include 
 #include 
 #endif
 #include 
@@ -248,34 +247,6 @@ int board_mmc_init(bd_t *bd)
 
return 0;
 }
-
-void pad_init_mmc(struct mmc_host *host)
-{
-#if defined(CONFIG_TEGRA30)
-   enum periph_id id = host->mmc_id;
-   u32 val;
-
-   debug("%s: sdmmc address = %08x, id = %d\n", __func__,
-   (unsigned int)host->reg, id);
-
-   /* Set the pad drive strength for SDMMC1 or 3 only */
-   if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
-   debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
-   __func__);
-   return;
-   }
-
-   val = readl(>reg->sdmemcmppadctl);
-   val &= 0xFFF0;
-   val |= MEMCOMP_PADCTRL_VREF;
-   writel(val, >reg->sdmemcmppadctl);
-
-   val = readl(>reg->autocalcfg);
-   val &= 0x;
-   val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
-   writel(val, >reg->autocalcfg);
-#endif /* T30 */
-}
 #endif /* MMC */
 
 /*
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 08b4bd48245a..5e6cfe710a1d 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -448,6 +448,34 @@ static void tegra_mmc_set_ios(struct mmc *mmc)
debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 }
 
+static void pad_init_mmc(struct mmc_host *host)
+{
+#if defined(CONFIG_TEGRA30)
+   enum periph_id id = host->mmc_id;
+   u32 val;
+
+   debug("%s: sdmmc address = %08x, id = %d\n", __func__,
+ (unsigned int)host->reg, id);
+
+   /* Set the pad drive strength for SDMMC1 or 3 only */
+   if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
+   debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+ __func__);
+   return;
+   }
+
+   val = readl(>reg->sdmemcmppadctl);
+   val &= 0xFFF0;
+   val |= MEMCOMP_PADCTRL_VREF;
+   writel(val, >reg->sdmemcmppadctl);
+
+   val = readl(>reg->autocalcfg);
+   val &= 0x;
+   val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+   writel(val, >reg->autocalcfg);
+#endif
+}
+
 static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
 {
unsigned int timeout;
-- 
2.9.3

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[U-Boot] [PATCH 05/21] mmc: tegra: priv struct and naming cleanup

[Stephen Warren]

From: Stephen Warren 

struct mmc_host is a Tegra-specific structure, but the name implies it's
something defined by core MMC code, which is confusing. Rename it to
struct tegra_mmc_priv to make its purpose more obvious. The new name is
also more appropriate for a DM driver private data structure, which will
be relevant later in this series.

Nothing needs access to this type except the MMC driver itself. Move the
definition into the driver C file.

Make sure all Tegra MMC functions are named tegra_mmc_*. Even though
they're all static, it's useful to have good naming so that symbol tables
are easy to interpret. A few functions aren't renamed by this patch since
they'll be deleted by a subsequent patch in this series.

Cc: Jaehoon Chung 
Signed-off-by: Stephen Warren 
---
 arch/arm/include/asm/arch-tegra/tegra_mmc.h |  19 --
 drivers/mmc/tegra_mmc.c | 299 +++-
 2 files changed, 161 insertions(+), 157 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h 
b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index fecb6599a844..64c848acb139 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -132,24 +132,5 @@ struct tegra_mmc {
 #define AUTO_CAL_PD_OFFSET (0x70 << 8)
 #define AUTO_CAL_PU_OFFSET (0x62 << 0)
 
-struct mmc_host {
-   struct tegra_mmc *reg;
-   int id; /* device id/number, 0-3 */
-   int enabled;/* 1 to enable, 0 to disable */
-   int width;  /* Bus Width, 1, 4 or 8 */
-#ifdef CONFIG_TEGRA186
-   struct reset_ctl reset_ctl;
-   struct clk clk;
-#else
-   enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
-#endif
-   struct gpio_desc cd_gpio;   /* Change Detect GPIO */
-   struct gpio_desc pwr_gpio;  /* Power GPIO */
-   struct gpio_desc wp_gpio;   /* Write Protect GPIO */
-   unsigned int version;   /* SDHCI spec. version */
-   unsigned int clock; /* Current clock (MHz) */
-   struct mmc_config cfg;  /* mmc configuration */
-};
-
 #endif /* __ASSEMBLY__ */
 #endif /* __TEGRA_MMC_H_ */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 4335431acc17..9287f1c3424f 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -32,13 +32,33 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
+struct tegra_mmc_priv {
+   struct tegra_mmc *reg;
+   int id; /* device id/number, 0-3 */
+   int enabled;/* 1 to enable, 0 to disable */
+   int width;  /* Bus Width, 1, 4 or 8 */
+#ifdef CONFIG_TEGRA186
+   struct reset_ctl reset_ctl;
+   struct clk clk;
+#else
+   enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
+#endif
+   struct gpio_desc cd_gpio;   /* Change Detect GPIO */
+   struct gpio_desc pwr_gpio;  /* Power GPIO */
+   struct gpio_desc wp_gpio;   /* Write Protect GPIO */
+   unsigned int version;   /* SDHCI spec. version */
+   unsigned int clock; /* Current clock (MHz) */
+   struct mmc_config cfg;  /* mmc configuration */
+};
+
+struct tegra_mmc_priv mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 #error "Please enable device tree support to use this driver"
 #endif
 
-static void mmc_set_power(struct mmc_host *host, unsigned short power)
+static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
+   unsigned short power)
 {
u8 pwr = 0;
debug("%s: power = %x\n", __func__, power);
@@ -61,17 +81,18 @@ static void mmc_set_power(struct mmc_host *host, unsigned 
short power)
debug("%s: pwr = %X\n", __func__, pwr);
 
/* Set the bus voltage first (if any) */
-   writeb(pwr, >reg->pwrcon);
+   writeb(pwr, >reg->pwrcon);
if (pwr == 0)
return;
 
/* Now enable bus power */
pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
-   writeb(pwr, >reg->pwrcon);
+   writeb(pwr, >reg->pwrcon);
 }
 
-static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
-   struct bounce_buffer *bbstate)
+static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
+  struct mmc_data *data,
+  struct bounce_buffer *bbstate)
 {
unsigned char ctrl;
 
@@ -80,7 +101,7 @@ static void mmc_prepare_data(struct mmc_host *host, struct 
mmc_data *data,
bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
data->blocksize);
 
-   writel((u32)(unsigned long)bbstate->bounce_buffer, >reg->sysad);
+   writel((u32)(unsigned long)bbstate->bounce_buffer, >reg->sysad);
/*
 * DMASEL[4:3]
 * 00 = Selects SDMA
@@ -88,17 +109,18 @@ static void 

[U-Boot] [PATCH 04/21] mmc: tegra: don't use periph_id in pad_init_mmc()

[Stephen Warren]

From: Stephen Warren 

The MMC driver will soon be converted to use standard clock/reset APIs,
and so the periph_id field in the MMC device priv struct will disappear.
Rework the implementation of pad_init_mmc() to rely on this; using the
device register address is a much more direct test anyway.

Cc: Jaehoon Chung 
Signed-off-by: Stephen Warren 
---
 drivers/mmc/tegra_mmc.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 5e6cfe710a1d..4335431acc17 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -451,14 +451,13 @@ static void tegra_mmc_set_ios(struct mmc *mmc)
 static void pad_init_mmc(struct mmc_host *host)
 {
 #if defined(CONFIG_TEGRA30)
-   enum periph_id id = host->mmc_id;
u32 val;
 
-   debug("%s: sdmmc address = %08x, id = %d\n", __func__,
- (unsigned int)host->reg, id);
+   debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)host->reg);
 
/* Set the pad drive strength for SDMMC1 or 3 only */
-   if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
+   if (host->reg != (void *)0x7800 &&
+   host->reg != (void *)0x78000400) {
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
  __func__);
return;
-- 
2.9.3

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[U-Boot] [PATCH 01/21] ARM: tegra: fdt: Add 'non-removable' property to all eMMC nodes

[Stephen Warren]

From: Tom Warren 

During debug of the DM_MMC changes to the Tegra MMC driver, I
noticed that the 'removable' property wasn't being set correctly
for the eMMC parts on most Tegra boards. Since the kernel DTS has
this property set correctly, it should be in U-Boot's Tegra DT too.

Signed-off-by: Tom Warren 
Signed-off-by: Stephen Warren 
---
 arch/arm/dts/tegra114-dalmore.dts | 1 +
 arch/arm/dts/tegra124-jetson-tk1.dts  | 1 +
 arch/arm/dts/tegra124-venice2.dts | 1 +
 arch/arm/dts/tegra186-p2771-.dtsi | 1 +
 arch/arm/dts/tegra20-paz00.dts| 1 +
 arch/arm/dts/tegra20-whistler.dts | 1 +
 arch/arm/dts/tegra210-e2220-1170.dts  | 1 +
 arch/arm/dts/tegra210-p2371-.dts  | 1 +
 arch/arm/dts/tegra210-p2371-2180.dts  | 1 +
 arch/arm/dts/tegra210-p2571.dts   | 1 +
 arch/arm/dts/tegra30-beaver.dts   | 1 +
 arch/arm/dts/tegra30-cardhu.dts   | 1 +
 arch/arm/dts/tegra30-tamonten.dtsi| 1 +
 13 files changed, 13 insertions(+)

diff --git a/arch/arm/dts/tegra114-dalmore.dts 
b/arch/arm/dts/tegra114-dalmore.dts
index 49195c35964a..f0331a740178 100644
--- a/arch/arm/dts/tegra114-dalmore.dts
+++ b/arch/arm/dts/tegra114-dalmore.dts
@@ -66,6 +66,7 @@
sdhci@78000600 {
bus-width = <8>;
status = "okay";
+   non-removable;
};
 
usb@7d00 {
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts 
b/arch/arm/dts/tegra124-jetson-tk1.dts
index 21ed1aef0bb2..4a63b6d86160 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -312,6 +312,7 @@
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
usb@7d00 {
diff --git a/arch/arm/dts/tegra124-venice2.dts 
b/arch/arm/dts/tegra124-venice2.dts
index 9de86c014361..6c39563bfc64 100644
--- a/arch/arm/dts/tegra124-venice2.dts
+++ b/arch/arm/dts/tegra124-venice2.dts
@@ -81,6 +81,7 @@
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
usb@7d00 {
diff --git a/arch/arm/dts/tegra186-p2771-.dtsi 
b/arch/arm/dts/tegra186-p2771-.dtsi
index 41ef64479a99..28fac5d8a261 100644
--- a/arch/arm/dts/tegra186-p2771-.dtsi
+++ b/arch/arm/dts/tegra186-p2771-.dtsi
@@ -55,6 +55,7 @@
sdhci@346 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
i2c@c24 {
diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts
index 5c7e80558da3..946862e72095 100644
--- a/arch/arm/dts/tegra20-paz00.dts
+++ b/arch/arm/dts/tegra20-paz00.dts
@@ -50,6 +50,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
clocks {
diff --git a/arch/arm/dts/tegra20-whistler.dts 
b/arch/arm/dts/tegra20-whistler.dts
index 358c5824f7cc..d4577c99c5d9 100644
--- a/arch/arm/dts/tegra20-whistler.dts
+++ b/arch/arm/dts/tegra20-whistler.dts
@@ -58,6 +58,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
clocks {
diff --git a/arch/arm/dts/tegra210-e2220-1170.dts 
b/arch/arm/dts/tegra210-e2220-1170.dts
index 75efbba1061e..c6e21762815f 100644
--- a/arch/arm/dts/tegra210-e2220-1170.dts
+++ b/arch/arm/dts/tegra210-e2220-1170.dts
@@ -31,6 +31,7 @@
sdhci@0,700b0600 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
i2c@0,7000d000 {
diff --git a/arch/arm/dts/tegra210-p2371-.dts 
b/arch/arm/dts/tegra210-p2371-.dts
index 10172a23ad70..3aa59d087bc8 100644
--- a/arch/arm/dts/tegra210-p2371-.dts
+++ b/arch/arm/dts/tegra210-p2371-.dts
@@ -31,6 +31,7 @@
sdhci@0,700b0600 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
i2c@0,7000d000 {
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts 
b/arch/arm/dts/tegra210-p2371-2180.dts
index bf35497d83f7..c4db2a45c561 100644
--- a/arch/arm/dts/tegra210-p2371-2180.dts
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
@@ -82,6 +82,7 @@
sdhci@0,700b0600 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
i2c@0,7000d000 {
diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts
index de35bba44bef..726c893aa500 100644
--- a/arch/arm/dts/tegra210-p2571.dts
+++ b/arch/arm/dts/tegra210-p2571.dts
@@ -84,6 +84,7 @@
sdhci@0,700b0600 {
status = "okay";
bus-width = <8>;
+   non-removable;
};
 
usb@0,7d00 {
diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index ae836363ab52..2ff7497a37ea 100644
--- 

[U-Boot] [PATCH 08/12] ARM: uniphier: remove IECTRL setup code of LD4 SoC

[Masahiro Yamada]

This should be handled by the pinctrl driver.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c 
b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c
index 625d40c..7ff85b6 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c
@@ -11,8 +11,6 @@
 
 void uniphier_ld4_pin_init(void)
 {
-   u32 tmp;
-
/* Comment format:PAD Name -> Function Name */
 
 #ifdef CONFIG_NAND_DENALI
@@ -34,8 +32,4 @@ void uniphier_ld4_pin_init(void)
sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */
sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
 #endif
-
-   tmp = readl(SG_IECTRL);
-   tmp |= 0x41;
-   writel(tmp, SG_IECTRL);
 }
-- 
1.9.1

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[U-Boot] [PATCH 06/12] pinctrl: uniphier: add System Bus pin-mux settings

[Masahiro Yamada]

This is needed to get access to UniPhier System Bus (external bus).

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c |  9 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c |  9 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c  | 18 ++
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 21 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 30 
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 30 
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c |  9 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 21 +
 8 files changed, 147 insertions(+)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index e42602b..1d318d8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -28,6 +28,12 @@ static const int i2c4_muxvals[] = {1, 1};
 static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 15, 16, 17};
 static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
0};
+static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
+  14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+2};
+static const unsigned system_bus_cs1_pins[] = {0};
+static const int system_bus_cs1_muxvals[] = {0};
 static const unsigned uart0_pins[] = {54, 55};
 static const int uart0_muxvals[] = {0, 0};
 static const unsigned uart1_pins[] = {58, 59};
@@ -52,6 +58,8 @@ static const struct uniphier_pinctrl_group 
uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
+   UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
+   UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@@ -69,6 +77,7 @@ static const char * const uniphier_ld11_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
+   UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index d6ae512..4ca39e6 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -34,6 +34,12 @@ static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 
10, 11, 12, 13, 14,
 static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
0};
 static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
 static const int sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3};  /* No SDVOLC */
+static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
+  14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+2};
+static const unsigned system_bus_cs1_pins[] = {0};
+static const int system_bus_cs1_muxvals[] = {0};
 static const unsigned uart0_pins[] = {54, 55};
 static const int uart0_muxvals[] = {0, 0};
 static const unsigned uart1_pins[] = {58, 59};
@@ -62,6 +68,8 @@ static const struct uniphier_pinctrl_group 
uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(sd),
+   UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
+   UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@@ -82,6 +90,7 @@ static const char * const uniphier_ld20_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+   UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 955858a..9b3db9d 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -51,6 +51,18 @@ static const unsigned nand_cs1_pins[] = {22, 23};
 static const int nand_cs1_muxvals[] = {0, 0};
 static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
 static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const 

[U-Boot] [PATCH 11/12] ARM: uniphier: fix DRAM size of LD21 SoC package

[Masahiro Yamada]

Each DRAM channel size of LD21 is half of that of LD20.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/boards.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 20093d8..f54f464 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -209,12 +209,12 @@ static const struct uniphier_board_data 
uniphier_ld21_data = {
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x8000,
-   .size = 0x4000,
+   .size = 0x2000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc000,
-   .size = 0x4000,
+   .size = 0x2000,
.width = 32,
},
.flags = UNIPHIER_BD_PACKAGE_LD21,
-- 
1.9.1

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[U-Boot] [PATCH 12/12] ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21

[Masahiro Yamada]

Unfortunately, this SoC needs per-board adjustment between clock
and address/command lines.  This flag will be passed to the DRAM
init function and used for compensating the difference of DRAM
timing parameters.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/boards.c | 25 -
 arch/arm/mach-uniphier/init.h   | 11 ---
 2 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index f54f464..1dececb 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -184,6 +184,27 @@ static const struct uniphier_board_data uniphier_ld11_data 
= {
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
+static const struct uniphier_board_data uniphier_ld20_ref_data = {
+   .dram_freq = 1866,
+   .dram_nr_ch = 3,
+   .dram_ch[0] = {
+   .base = 0x8000,
+   .size = 0x4000,
+   .width = 32,
+   },
+   .dram_ch[1] = {
+   .base = 0xc000,
+   .size = 0x4000,
+   .width = 32,
+   },
+   .dram_ch[2] = {
+   .base = 0x1UL,
+   .size = 0x4000,
+   .width = 32,
+   },
+   .flags = UNIPHIER_BD_BOARD_LD20_REF,
+};
+
 static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
@@ -202,6 +223,7 @@ static const struct uniphier_board_data uniphier_ld20_data 
= {
.size = 0x4000,
.width = 32,
},
+   .flags = UNIPHIER_BD_BOARD_LD20_GLOBAL,
 };
 
 static const struct uniphier_board_data uniphier_ld21_data = {
@@ -217,7 +239,7 @@ static const struct uniphier_board_data uniphier_ld21_data 
= {
.size = 0x2000,
.width = 32,
},
-   .flags = UNIPHIER_BD_PACKAGE_LD21,
+   .flags = UNIPHIER_BD_BOARD_LD21_GLOBAL,
 };
 #endif
 
@@ -255,6 +277,7 @@ static const struct uniphier_board_id uniphier_boards[] = {
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
{ "socionext,ph1-ld21", _ld21_data, },
+   { "socionext,ph1-ld20-ref", _ld20_ref_data, },
{ "socionext,ph1-ld20", _ld20_data, },
 #endif
 };
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index a2fedbc..406d5d0 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -23,9 +23,14 @@ struct uniphier_board_data {
unsigned int dram_nr_ch;
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
unsigned int flags;
-#define UNIPHIER_BD_DDR3PLUS   BIT(2)
-#define UNIPHIER_BD_PACKAGE_LD21   1
-#define UNIPHIER_BD_PACKAGE_TYPE(f)((f) & 0x3)
+
+#define UNIPHIER_BD_DDR3PLUS   BIT(2)
+
+#define UNIPHIER_BD_BOARD_GET_TYPE(f)  ((f) & 0x3)
+#define UNIPHIER_BD_BOARD_LD20_REF 0   /* LD20 reference */
+#define UNIPHIER_BD_BOARD_LD20_GLOBAL  1   /* LD20 TV Set */
+#define UNIPHIER_BD_BOARD_LD21_REF 2   /* LD21 reference */
+#define UNIPHIER_BD_BOARD_LD21_GLOBAL  3   /* LD21 TV Set */
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(void);
-- 
1.9.1

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[U-Boot] [PATCH 05/12] mmc: uniphier-sd: migrate to CONFIG_BLK

[Masahiro Yamada]

This is the state-of-the-art MMC driver implementation.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

 arch/arm/Kconfig  |  1 +
 drivers/mmc/Kconfig   |  1 +
 drivers/mmc/uniphier-sd.c | 50 +++
 3 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 512e326..498658d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -855,6 +855,7 @@ config TARGET_COLIBRI_PXA270
 
 config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
+   select BLK
select CLK_UNIPHIER
select DM
select DM_GPIO
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index a71afa5..ba9a723 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -80,6 +80,7 @@ config ROCKCHIP_SDHCI
 config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
+   depends on BLK
select DM_MMC_OPS
help
  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 701b26f..4af7fdb 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -119,9 +119,12 @@ DECLARE_GLOBAL_DATA_PTR;
 /* alignment required by the DMA engine of this controller */
 #define UNIPHIER_SD_DMA_MINALIGN   0x10
 
-struct uniphier_sd_priv {
+struct uniphier_sd_plat {
struct mmc_config cfg;
-   struct mmc *mmc;
+   struct mmc mmc;
+};
+
+struct uniphier_sd_priv {
void __iomem *regbase;
unsigned long mclk;
unsigned int version;
@@ -654,8 +657,16 @@ static void uniphier_sd_host_init(struct uniphier_sd_priv 
*priv)
}
 }
 
+static int uniphier_sd_bind(struct udevice *dev)
+{
+   struct uniphier_sd_plat *plat = dev_get_platdata(dev);
+
+   return mmc_bind(dev, >mmc, >cfg);
+}
+
 static int uniphier_sd_probe(struct udevice *dev)
 {
+   struct uniphier_sd_plat *plat = dev_get_platdata(dev);
struct uniphier_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
@@ -691,15 +702,15 @@ static int uniphier_sd_probe(struct udevice *dev)
return ret;
}
 
-   priv->cfg.name = dev->name;
-   priv->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
+   plat->cfg.name = dev->name;
+   plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
case 8:
-   priv->cfg.host_caps |= MMC_MODE_8BIT;
+   plat->cfg.host_caps |= MMC_MODE_8BIT;
break;
case 4:
-   priv->cfg.host_caps |= MMC_MODE_4BIT;
+   plat->cfg.host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
@@ -722,27 +733,13 @@ static int uniphier_sd_probe(struct udevice *dev)
 
uniphier_sd_host_init(priv);
 
-   priv->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
-   priv->cfg.f_min = priv->mclk /
+   plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+   plat->cfg.f_min = priv->mclk /
(priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
-   priv->cfg.f_max = priv->mclk;
-   priv->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
-
-   priv->mmc = mmc_create(>cfg, priv);
-   if (!priv->mmc)
-   return -EIO;
-
-   upriv->mmc = priv->mmc;
-   priv->mmc->dev = dev;
-
-   return 0;
-}
-
-static int uniphier_sd_remove(struct udevice *dev)
-{
-   struct uniphier_sd_priv *priv = dev_get_priv(dev);
+   plat->cfg.f_max = priv->mclk;
+   plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
 
-   mmc_destroy(priv->mmc);
+   upriv->mmc = >mmc;
 
return 0;
 }
@@ -756,8 +753,9 @@ U_BOOT_DRIVER(uniphier_mmc) = {
.name = "uniphier-mmc",
.id = UCLASS_MMC,
.of_match = uniphier_sd_match,
+   .bind = uniphier_sd_bind,
.probe = uniphier_sd_probe,
-   .remove = uniphier_sd_remove,
.priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
+   .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat),
.ops = _sd_ops,
 };
-- 
1.9.1

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[U-Boot] [PATCH 09/12] ARM: uniphier: use checkboard() instead of misc_init_f()

[Masahiro Yamada]

We can use checkboard() stub to show additional board information,
so misc_init_f() should not be used for this purpose.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile |  1 -
 arch/arm/mach-uniphier/micro-support-card.c |  2 +-
 arch/arm/mach-uniphier/micro-support-card.h | 12 +++-
 arch/arm/mach-uniphier/print_misc_info.c| 12 
 include/configs/uniphier.h  |  1 -
 5 files changed, 4 insertions(+), 24 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/print_misc_info.c

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 774ea99..2e92e15 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -11,7 +11,6 @@ else
 
 obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
-obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
 obj-y += dram_init.o
 obj-y += board_common.o
 obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
diff --git a/arch/arm/mach-uniphier/micro-support-card.c 
b/arch/arm/mach-uniphier/micro-support-card.c
index 6987d1e..04e6558 100644
--- a/arch/arm/mach-uniphier/micro-support-card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -49,7 +49,7 @@ static int support_card_show_revision(void)
return 0;
 }
 
-int check_support_card(void)
+int checkboard(void)
 {
printf("SC:Micro Support Card ");
return support_card_show_revision();
diff --git a/arch/arm/mach-uniphier/micro-support-card.h 
b/arch/arm/mach-uniphier/micro-support-card.h
index 5da0ada..630c98d 100644
--- a/arch/arm/mach-uniphier/micro-support-card.h
+++ b/arch/arm/mach-uniphier/micro-support-card.h
@@ -4,14 +4,13 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef ARCH_BOARD_H
-#define ARCH_BOARD_H
+#ifndef MICRO_SUPPORT_CARD_H
+#define MICRO_SUPPORT_CARD_H
 
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
 void support_card_reset(void);
 void support_card_init(void);
 void support_card_late_init(void);
-int check_support_card(void);
 void led_puts(const char *s);
 #else
 static inline void support_card_reset(void)
@@ -26,14 +25,9 @@ static inline void support_card_late_init(void)
 {
 }
 
-static inline int check_support_card(void)
-{
-   return 0;
-}
-
 static inline void led_puts(const char *s)
 {
 }
 #endif
 
-#endif /* ARCH_BOARD_H */
+#endif /* MICRO_SUPPORT_CARD_H */
diff --git a/arch/arm/mach-uniphier/print_misc_info.c 
b/arch/arm/mach-uniphier/print_misc_info.c
deleted file mode 100644
index 695b7ae..000
--- a/arch/arm/mach-uniphier/print_misc_info.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include "micro-support-card.h"
-
-int misc_init_f(void)
-{
-   return check_support_card();
-}
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index b3ca46b..1e601b9 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -31,7 +31,6 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_MISC_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_BOARD_LATE_INIT
-- 
1.9.1

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[U-Boot] [PATCH 07/12] pinctrl: uniphier: move register base macros from header to .c file

[Masahiro Yamada]

These macros are only referenced in pinctrl-uniphier-core.c, so
they need not reside in a header file.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 4 
 drivers/pinctrl/uniphier/pinctrl-uniphier.h  | 4 
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 3f891f1..f2fe313 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -13,6 +13,10 @@
 
 #include "pinctrl-uniphier.h"
 
+#define UNIPHIER_PINCTRL_PINMUX_BASE   0x1000
+#define UNIPHIER_PINCTRL_LOAD_PINMUX   0x1700
+#define UNIPHIER_PINCTRL_IECTRL0x1d00
+
 static const char *uniphier_pinctrl_dummy_name = "_dummy";
 
 static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h 
b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 4de5b03..76ea1be 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -13,10 +13,6 @@
 #include 
 #include 
 
-#define UNIPHIER_PINCTRL_PINMUX_BASE   0x1000
-#define UNIPHIER_PINCTRL_LOAD_PINMUX   0x1700
-#define UNIPHIER_PINCTRL_IECTRL0x1d00
-
 #define UNIPHIER_PIN_ATTR_PACKED(iectrl)   (iectrl)
 
 static inline unsigned int uniphier_pin_get_iectrl(unsigned long data)
-- 
1.9.1

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[U-Boot] [PATCH 02/12] usb: uniphier: remove UniPhier xHCI driver and select DM_USB

[Masahiro Yamada]

This driver has not been converted to Driver Model, and it is an
obstacle to migrate other block device drivers.  Remove it for now.

The UniPhier SoCs already use a DM-based EHCI driver, so now
ARCH_UNIPHIER can select DM_USB.

These two changes must be done atomically because removing the
legacy driver causes a build error.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Marek Vasut 
---

 arch/arm/Kconfig|  1 +
 configs/uniphier_ld4_sld8_defconfig |  1 -
 configs/uniphier_sld3_defconfig |  1 -
 drivers/usb/host/Kconfig|  7 ---
 drivers/usb/host/Makefile   |  1 -
 drivers/usb/host/xhci-uniphier.c| 85 -
 include/fdtdec.h|  1 -
 lib/fdtdec.c|  1 -
 8 files changed, 1 insertion(+), 97 deletions(-)
 delete mode 100644 drivers/usb/host/xhci-uniphier.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f7b6f0d..512e326 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -861,6 +861,7 @@ config ARCH_UNIPHIER
select DM_I2C
select DM_MMC
select DM_SERIAL
+   select DM_USB
select OF_CONTROL
select OF_LIBFDT
select SPL
diff --git a/configs/uniphier_ld4_sld8_defconfig 
b/configs/uniphier_ld4_sld8_defconfig
index e3ad160..89d3de4 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -32,7 +32,6 @@ CONFIG_SPL_NAND_DENALI=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index 1c5cece..8781fe6 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index e0699d4..42e8a9f 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -15,13 +15,6 @@ config USB_XHCI_HCD
 
 if USB_XHCI_HCD
 
-config USB_XHCI_UNIPHIER
-   bool "Support for UniPhier on-chip xHCI USB controller"
-   depends on ARCH_UNIPHIER
-   default y
-   ---help---
- Enables support for the on-chip xHCI controller on UniPhier SoCs.
-
 config USB_XHCI_DWC3
bool "DesignWare USB3 DRD Core Support"
help
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 620d114..55190bb 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -62,7 +62,6 @@ obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
-obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
 
 # designware
 obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c
deleted file mode 100644
index 1b3f3d2..000
--- a/drivers/usb/host/xhci-uniphier.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include "xhci.h"
-
-static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
-{
-   DECLARE_GLOBAL_DATA_PTR;
-   int node_list[2];
-   fdt_addr_t addr;
-   int count;
-
-   count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
-  COMPAT_SOCIONEXT_XHCI, node_list,
-  ARRAY_SIZE(node_list));
-
-   if (index >= count)
-   return -ENODEV;
-
-   addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
-   if (addr == FDT_ADDR_T_NONE)
-   return -ENODEV;
-
-   *base = (struct xhci_hccr *)addr;
-
-   return 0;
-}
-
-#define USB3_RST_CTRL  0x00100040
-#define IOMMU_RST_N(1 << 5)
-#define LINK_RST_N (1 << 4)
-
-static void uniphier_xhci_reset(void __iomem *base, int on)
-{
-   u32 tmp;
-
-   tmp = readl(base + USB3_RST_CTRL);
-
-   if (on)
-   tmp &= ~(IOMMU_RST_N | LINK_RST_N);
-   else
-   tmp |= IOMMU_RST_N | LINK_RST_N;
-
-   writel(tmp, base + USB3_RST_CTRL);
-}
-
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
-{
-   int ret;
-   struct xhci_hccr *cr;
-   struct xhci_hcor *or;
-
-   ret = get_uniphier_xhci_base(index, );
-   if (ret < 0)
-   return ret;
-
-   uniphier_xhci_reset(cr, 0);
-
-   or = (void *)cr + HC_LENGTH(xhci_readl(>cr_capbase));
-
-   *hccr = cr;
-   *hcor = or;
-
-   return 0;
-}
-
-void xhci_hcd_stop(int 

[U-Boot] [PATCH 04/12] ARM: uniphier: enable Generic EHCI driver for Pro4 SoC

[Masahiro Yamada]

This SoC is equipped with two EHCI cores and two xHCI cores.
Enable the generic EHCI driver for the former.

Signed-off-by: Masahiro Yamada 
---

 configs/uniphier_pro4_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index a7dcc56..ddc582d 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -32,4 +32,6 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-- 
1.9.1

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[U-Boot] [PATCH 10/12] ARM: uniphier: merge board init functions into board_init()

[Masahiro Yamada]

Currently, the UniPhier platform calls several init functions in the
following order:

  [1] spl_board_init()
  [2] board_early_init_f()
  [3] board_init()
  [4] board_early_init_r()
  [5] board_late_init()

The serial console is not ready at the point of [2], so we want to
avoid using [2] from the view point of debuggability.  Fortunately,
all of the initialization in [2] can be delayed until [3].  I see no
good reason to split into [3] and [4].  So, merge [2] through [4].

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile  |  4 +---
 arch/arm/mach-uniphier/board_common.c| 20 
 arch/arm/mach-uniphier/board_early_init_r.c  | 15 ---
 .../{board_early_init_f.c => board_init.c}   | 12 +++-
 arch/arm/mach-uniphier/init.h|  1 +
 include/configs/uniphier.h   |  2 --
 6 files changed, 13 insertions(+), 41 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/board_common.c
 delete mode 100644 arch/arm/mach-uniphier/board_early_init_r.c
 rename arch/arm/mach-uniphier/{board_early_init_f.c => board_init.c} (94%)

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 2e92e15..1fe5199 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -9,11 +9,9 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
 
 else
 
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
 obj-y += dram_init.o
-obj-y += board_common.o
-obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
+obj-y += board_init.o
 obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
 obj-y += reset.o
 
diff --git a/arch/arm/mach-uniphier/board_common.c 
b/arch/arm/mach-uniphier/board_common.c
deleted file mode 100644
index 330d690..000
--- a/arch/arm/mach-uniphier/board_common.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-
-#include "micro-support-card.h"
-
-void uniphier_smp_kick_all_cpus(void);
-
-int board_init(void)
-{
-   led_puts("Uboo");
-#ifdef CONFIG_ARM64
-   uniphier_smp_kick_all_cpus();
-#endif
-   return 0;
-}
diff --git a/arch/arm/mach-uniphier/board_early_init_r.c 
b/arch/arm/mach-uniphier/board_early_init_r.c
deleted file mode 100644
index b26da36..000
--- a/arch/arm/mach-uniphier/board_early_init_r.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-
-#include "micro-support-card.h"
-
-int board_early_init_r(void)
-{
-   support_card_late_init();
-   return 0;
-}
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c 
b/arch/arm/mach-uniphier/board_init.c
similarity index 94%
rename from arch/arm/mach-uniphier/board_early_init_f.c
rename to arch/arm/mach-uniphier/board_init.c
index d35d38d..754e2c8 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -45,7 +45,7 @@ static void uniphier_setup_xirq(void)
writel(tmp, 0x5590);
 }
 
-int board_early_init_f(void)
+int board_init(void)
 {
led_puts("U0");
 
@@ -122,5 +122,15 @@ int board_early_init_f(void)
 
led_puts("U2");
 
+   support_card_late_init();
+
+   led_puts("U3");
+
+#ifdef CONFIG_ARM64
+   uniphier_smp_kick_all_cpus();
+#endif
+
+   led_puts("Uboo");
+
return 0;
 }
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index db80074..a2fedbc 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -115,6 +115,7 @@ void uniphier_pxs2_clk_init(void);
 void uniphier_ld11_clk_init(void);
 void uniphier_ld20_clk_init(void);
 
+void uniphier_smp_kick_all_cpus(void);
 void cci500_init(int nr_slaves);
 
 #define pr_err(fmt, args...)   printf(fmt, ##args)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 1e601b9..f835ff1 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -31,8 +31,6 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_BOARD_LATE_INIT
 
 #define CONFIG_SYS_MALLOC_LEN  (4 * 1024 * 1024)
-- 
1.9.1

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[U-Boot] [PATCH 01/12] ARM: uniphier: sort select:s alphabetically

[Masahiro Yamada]

ARCH_UNIPHIER is having more and more select:s.  Sort them in case
a select is accidentally duplicated.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/Kconfig | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e63309a..f7b6f0d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -856,17 +856,17 @@ config TARGET_COLIBRI_PXA270
 config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select CLK_UNIPHIER
-   select SUPPORT_SPL
-   select SPL
-   select OF_CONTROL
-   select SPL_OF_CONTROL
-   select OF_LIBFDT
select DM
-   select SPL_DM
select DM_GPIO
-   select DM_SERIAL
select DM_I2C
select DM_MMC
+   select DM_SERIAL
+   select OF_CONTROL
+   select OF_LIBFDT
+   select SPL
+   select SPL_DM
+   select SPL_OF_CONTROL
+   select SUPPORT_SPL
help
  Support for UniPhier SoC family developed by Socionext Inc.
  (formerly, System LSI Business Division of Panasonic Corporation)
-- 
1.9.1

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[U-Boot] [PATCH 03/12] ARM: uniphier: delete unnecessary xHCI pin-mux settings

[Masahiro Yamada]

These ad-hoc pinmux settings were used for the legacy xHCI driver,
which has gone now.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 12 
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c | 11 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c |  7 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c |  7 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c | 11 ---
 5 files changed, 48 deletions(-)

diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c 
b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
index 645b901..ec4c414 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
@@ -32,18 +32,6 @@ void uniphier_ld20_pin_init(void)
sg_set_iectrl_range(3, 17);
 #endif
 
-#ifdef CONFIG_USB_XHCI_UNIPHIER
-   sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
-   sg_set_pinsel(47, 0, 8, 4); /* USB0OD   -> USB0OD */
-   sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
-   sg_set_pinsel(49, 0, 8, 4); /* USB1OD   -> USB1OD */
-   sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
-   sg_set_pinsel(51, 0, 8, 4); /* USB2OD   -> USB2OD */
-   sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
-   sg_set_pinsel(53, 0, 8, 4); /* USB3OD   -> USB3OD */
-   sg_set_iectrl_range(46, 53);
-#endif
-
sg_set_pinsel(149, 14, 8, 4);   /* XIRQ0-> XIRQ0 */
sg_set_iectrl(149);
sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4-> XIRQ4 */
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c 
b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c
index 913722b..f3b7115 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c
@@ -32,15 +32,4 @@ void uniphier_ld6b_pin_init(void)
sg_set_pinsel(45, 0, 8, 4); /* NFD6   -> NFD6 */
sg_set_pinsel(46, 0, 8, 4); /* NFD7   -> NFD7 */
 #endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
-   sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
-   sg_set_pinsel(57, 0, 8, 4); /* USB0OD   -> USB0OD */
-   sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
-   sg_set_pinsel(59, 0, 8, 4); /* USB1OD   -> USB1OD */
-   sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
-   sg_set_pinsel(61, 0, 8, 4); /* USB2OD   -> USB2OD */
-   sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
-   sg_set_pinsel(63, 0, 8, 4); /* USB3OD   -> USB3OD */
-#endif
 }
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c 
b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c
index 3796491..871d3ef 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c
@@ -33,12 +33,5 @@ void uniphier_pro4_pin_init(void)
/* sg_set_pinsel(132, 1, 4, 8); */  /* TXD2   -> XNFCE1 */
 #endif
 
-#ifdef CONFIG_USB_XHCI_UNIPHIER
-   sg_set_pinsel(180, 0, 4, 8);/* USB0VBUS -> USB0VBUS */
-   sg_set_pinsel(181, 0, 4, 8);/* USB0OD   -> USB0OD */
-   sg_set_pinsel(182, 0, 4, 8);/* USB1VBUS -> USB1VBUS */
-   sg_set_pinsel(183, 0, 4, 8);/* USB1OD   -> USB1OD */
-#endif
-
writel(1, SG_LOADPINCTRL);
 }
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c 
b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c
index 32ba923..58dff18 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c
@@ -33,12 +33,5 @@ void uniphier_pro5_pin_init(void)
sg_set_pinsel(35, 0, 4, 8); /* NFD7   -> NFD7 */
 #endif
 
-#ifdef CONFIG_USB_XHCI_UNIPHIER
-   sg_set_pinsel(124, 0, 4, 8);/* USB0VBUS -> USB0VBUS */
-   sg_set_pinsel(125, 0, 4, 8);/* USB0OD   -> USB0OD */
-   sg_set_pinsel(126, 0, 4, 8);/* USB1VBUS -> USB1VBUS */
-   sg_set_pinsel(127, 0, 4, 8);/* USB1OD   -> USB1OD */
-#endif
-
writel(1, SG_LOADPINCTRL);
 }
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c 
b/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c
index 2d62ab3..fc59205 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c
@@ -32,15 +32,4 @@ void uniphier_pxs2_pin_init(void)
sg_set_pinsel(45, 8, 8, 4); /* NFD6   -> NFD6 */
sg_set_pinsel(46, 8, 8, 4); /* NFD7   -> NFD7 */
 #endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
-   sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */
-   sg_set_pinsel(57, 8, 8, 4); /* USB0OD   -> USB0OD */
-   sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */
-   sg_set_pinsel(59, 8, 8, 4); /* USB1OD   -> USB1OD */
-   sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */
-   sg_set_pinsel(61, 8, 8, 4); /* USB2OD   -> USB2OD */
-   sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */
-   sg_set_pinsel(63, 8, 8, 4); 

[U-Boot] [PATCH 00/12] ARM: uniphier: UniPhier SoC updates for v2016.11-rc1

[Masahiro Yamada]

I want to get this series in during this merge window.

  - DM migration
  * remove legacy xHCI driver
  * convert MMC driver to CONFIG_BLOCK
  - Pinctrl driver improvements
  * New pin-group
  * Macro cleanup
  - Misc fixes, cleanups
  * Fix DRAM size of LD21 SoC
  * Consolidate board init functions



Masahiro Yamada (12):
  ARM: uniphier: sort select:s alphabetically
  usb: uniphier: remove UniPhier xHCI driver and select DM_USB
  ARM: uniphier: delete unnecessary xHCI pin-mux settings
  ARM: uniphier: enable Generic EHCI driver for Pro4 SoC
  mmc: uniphier-sd: migrate to CONFIG_BLK
  pinctrl: uniphier: add System Bus pin-mux settings
  pinctrl: uniphier: move register base macros from header to .c file
  ARM: uniphier: remove IECTRL setup code of LD4 SoC
  ARM: uniphier: use checkboard() instead of misc_init_f()
  ARM: uniphier: merge board init functions into board_init()
  ARM: uniphier: fix DRAM size of LD21 SoC package
  ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21

 arch/arm/Kconfig   | 16 ++--
 arch/arm/mach-uniphier/Makefile|  5 +-
 arch/arm/mach-uniphier/board_common.c  | 20 -
 arch/arm/mach-uniphier/board_early_init_r.c| 15 
 .../{board_early_init_f.c => board_init.c} | 12 ++-
 arch/arm/mach-uniphier/boards.c| 29 +++-
 arch/arm/mach-uniphier/init.h  | 12 ++-
 arch/arm/mach-uniphier/micro-support-card.c|  2 +-
 arch/arm/mach-uniphier/micro-support-card.h| 12 +--
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c  | 12 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c   |  6 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c  | 11 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c  |  7 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c  |  7 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c  | 11 ---
 arch/arm/mach-uniphier/print_misc_info.c   | 12 ---
 configs/uniphier_ld4_sld8_defconfig|  1 -
 configs/uniphier_pro4_defconfig|  2 +
 configs/uniphier_sld3_defconfig|  1 -
 drivers/mmc/Kconfig|  1 +
 drivers/mmc/uniphier-sd.c  | 50 ++---
 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c   |  4 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c   |  9 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c   |  9 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c| 18 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c   | 21 ++
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c   | 30 
 drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c   | 30 
 drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c   |  9 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c   | 21 ++
 drivers/pinctrl/uniphier/pinctrl-uniphier.h|  4 -
 drivers/usb/host/Kconfig   |  7 --
 drivers/usb/host/Makefile  |  1 -
 drivers/usb/host/xhci-uniphier.c   | 85 --
 include/configs/uniphier.h |  3 -
 include/fdtdec.h   |  1 -
 lib/fdtdec.c   |  1 -
 37 files changed, 238 insertions(+), 259 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/board_common.c
 delete mode 100644 arch/arm/mach-uniphier/board_early_init_r.c
 rename arch/arm/mach-uniphier/{board_early_init_f.c => board_init.c} (94%)
 delete mode 100644 arch/arm/mach-uniphier/print_misc_info.c
 delete mode 100644 drivers/usb/host/xhci-uniphier.c

-- 
1.9.1

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[U-Boot] [PATCH] imx: s/docs\/README.imximage/doc\/README.imximage/g

[Jagan Teki]

Fixed typo for doc/README.imximage on respective imximage.cfg files.

Cc: Tom Rini 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Signed-off-by: Jagan Teki 
---
 board/barco/titanium/imximage.cfg   | 2 +-
 board/ccv/xpress/imximage.cfg   | 2 +-
 board/denx/m53evk/imximage.cfg  | 2 +-
 board/freescale/mx6sabresd/mx6dlsabresd.cfg | 2 +-
 board/freescale/mx6slevk/imximage.cfg   | 2 +-
 board/freescale/mx6ullevk/imximage.cfg  | 2 +-
 board/freescale/mx7dsabresd/imximage.cfg| 2 +-
 board/freescale/s32v234evb/s32v234evb.cfg   | 2 +-
 board/freescale/vf610twr/imximage.cfg   | 2 +-
 board/phytec/pcm052/imximage.cfg| 2 +-
 board/technexion/pico-imx6ul/imximage.cfg   | 2 +-
 board/toradex/colibri_imx7/imximage.cfg | 2 +-
 board/toradex/colibri_vf/imximage.cfg   | 2 +-
 board/warp/imximage.cfg | 2 +-
 board/warp7/imximage.cfg| 2 +-
 15 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/board/barco/titanium/imximage.cfg 
b/board/barco/titanium/imximage.cfg
index 7219256..4fb6982 100644
--- a/board/barco/titanium/imximage.cfg
+++ b/board/barco/titanium/imximage.cfg
@@ -7,7 +7,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg
index 92167c9..d98bc36 100644
--- a/board/ccv/xpress/imximage.cfg
+++ b/board/ccv/xpress/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg
index 4cd002c..c0e2602 100644
--- a/board/denx/m53evk/imximage.cfg
+++ b/board/denx/m53evk/imximage.cfg
@@ -4,7 +4,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg 
b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
index f35f22e..be9f87f 100644
--- a/board/freescale/mx6sabresd/mx6dlsabresd.cfg
+++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6slevk/imximage.cfg 
b/board/freescale/mx6slevk/imximage.cfg
index c77bbde..024de9c 100644
--- a/board/freescale/mx6slevk/imximage.cfg
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6ullevk/imximage.cfg 
b/board/freescale/mx6ullevk/imximage.cfg
index 4604b62..3ae4912 100644
--- a/board/freescale/mx6ullevk/imximage.cfg
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx7dsabresd/imximage.cfg 
b/board/freescale/mx7dsabresd/imximage.cfg
index 76574ff..c2b3a8c 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/s32v234evb/s32v234evb.cfg 
b/board/freescale/s32v234evb/s32v234evb.cfg
index 6017a40..6449ef2 100644
--- a/board/freescale/s32v234evb/s32v234evb.cfg
+++ b/board/freescale/s32v234evb/s32v234evb.cfg
@@ -5,7 +5,7 @@
  */
 
 /*
- * Refer docs/README.imxmage for more details about 

[U-Boot] [PATCH 0/5] imx: Add Engicam i.CoreM6 QDL modules support

[Jagan Teki]

This series supports Engicam i.CoreM6 QDL modules on top of
u-boot-imx.git/next and test on the respective starter kits as well.

Jagan Teki (5):
  imx: iomux-v3: Fix build error with snvs base
  serial: Kconfig: Add MXC_UART entry
  thermal: Kconfig: Add IMX_THERMAL entry
  Kconfig: Add DEFAULT_FDT_FILE entry
  arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support

 arch/arm/cpu/armv7/mx6/Kconfig|   8 +
 arch/arm/imx-common/iomux-v3.c|   2 +-
 board/engicam/icorem6/Kconfig |  12 ++
 board/engicam/icorem6/MAINTAINERS |   6 +
 board/engicam/icorem6/Makefile|   6 +
 board/engicam/icorem6/README  |  28 +++
 board/engicam/icorem6/icorem6.c   | 403 ++
 common/Kconfig|   6 +
 configs/imx6qdl_icore_defconfig   |  26 +++
 drivers/serial/Kconfig|   7 +
 drivers/thermal/Kconfig   |  13 ++
 include/configs/imx6qdl_icore.h   | 116 +++
 12 files changed, 632 insertions(+), 1 deletion(-)
 create mode 100644 board/engicam/icorem6/Kconfig
 create mode 100644 board/engicam/icorem6/MAINTAINERS
 create mode 100644 board/engicam/icorem6/Makefile
 create mode 100644 board/engicam/icorem6/README
 create mode 100644 board/engicam/icorem6/icorem6.c
 create mode 100644 configs/imx6qdl_icore_defconfig
 create mode 100644 include/configs/imx6qdl_icore.h

-- 
2.7.4

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[U-Boot] [PATCH 3/5] thermal: Kconfig: Add IMX_THERMAL entry

[Jagan Teki]

Added kconfig for IMX_THERMAL driver.

Cc: Simon Glass 
Cc: Fabio Estevam 
Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 drivers/thermal/Kconfig | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 8e22ea7..f0ffbb3 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -5,3 +5,16 @@ config DM_THERMAL
  temperature sensors to permit warnings, speed throttling or even
  automatic power-off when the temperature gets too high or low. Other
  devices may be discrete but connected on a suitable bus.
+
+if DM_THERMAL
+
+config IMX_THERMAL
+   bool "Temperature sensor driver for Freescale i.MX SoCs"
+   depends on MX6
+   help
+ Support for Temperature Monitor (TEMPMON) found on Freescale i.MX 
SoCs.
+  It supports one critical trip point and one passive trip point.  The
+  cpufreq is used as the cooling device to throttle CPUs when the
+  passive trip is crossed.
+
+endif # if DM_THERMAL
-- 
2.7.4

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[U-Boot] [PATCH 5/5] arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support

[Jagan Teki]

Boot Log for i.CoreM6 Quad/Dual Starter Kit:

U-Boot SPL 2016.09-rc2-30745-gd99a2be (Sep 13 2016 - 18:28:43)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30745-gd99a2be (Sep 13 2016 - 18:28:43 +0530)

CPU:   Freescale i.MX6Q rev1.2 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
icorem6qdl>

Boot Log for i.CoreM6 DualLite/Solo Starter Kit:

U-Boot 2016.09-rc2-30745-gb4198e9 (Sep 13 2016 - 18:48:53 +0530)

CPU:   Freescale i.MX6SOLO rev1.3 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 40C
Reset cause: POR
DRAM:  256 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
253 bytes read in 10 ms (24.4 KiB/s)
Running bootscript from mmc ...
reading zImage
6741080 bytes read in 340 ms (18.9 MiB/s)
reading imx6dl-icore.dtb
28519 bytes read in 19 ms (1.4 MiB/s)
   Booting using the fdt blob at 0x1800
   Using Device Tree in place at 1800, end 18009f66

Starting kernel ...

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig|   8 +
 board/engicam/icorem6/Kconfig |  12 ++
 board/engicam/icorem6/MAINTAINERS |   6 +
 board/engicam/icorem6/Makefile|   6 +
 board/engicam/icorem6/README  |  28 +++
 board/engicam/icorem6/icorem6.c   | 403 ++
 configs/imx6qdl_icore_defconfig   |  26 +++
 include/configs/imx6qdl_icore.h   | 116 +++
 8 files changed, 605 insertions(+)
 create mode 100644 board/engicam/icorem6/Kconfig
 create mode 100644 board/engicam/icorem6/MAINTAINERS
 create mode 100644 board/engicam/icorem6/Makefile
 create mode 100644 board/engicam/icorem6/README
 create mode 100644 board/engicam/icorem6/icorem6.c
 create mode 100644 configs/imx6qdl_icore_defconfig
 create mode 100644 include/configs/imx6qdl_icore.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index d851b26..5d549bd 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -95,6 +95,13 @@ config TARGET_MX6CUBOXI
 config TARGET_MX6QARM2
bool "mx6qarm2"
 
+config TARGET_MX6Q_ICORE
+   bool "Support Engicam i.Core"
+   select MX6QDL
+   select DM
+   select DM_THERMAL
+   select SUPPORT_SPL
+
 config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
select DM
@@ -225,6 +232,7 @@ source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
+source "board/engicam/icorem6/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
diff --git a/board/engicam/icorem6/Kconfig b/board/engicam/icorem6/Kconfig
new file mode 100644
index 000..6d62f0e
--- /dev/null
+++ b/board/engicam/icorem6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE
+
+config SYS_BOARD
+   default "icorem6"
+
+config SYS_VENDOR
+   default "engicam"
+
+config SYS_CONFIG_NAME
+   default "imx6qdl_icore"
+
+endif
diff --git a/board/engicam/icorem6/MAINTAINERS 
b/board/engicam/icorem6/MAINTAINERS
new file mode 100644
index 000..3e06c6b
--- /dev/null
+++ b/board/engicam/icorem6/MAINTAINERS
@@ -0,0 +1,6 @@
+ICOREM6QDL BOARD
+M: Jagan Teki 
+S: Maintained
+F: board/engicam/icorem6
+F: include/configs/icorem6qdl.h
+F: configs/icorem6qdl_defconfig
diff --git a/board/engicam/icorem6/Makefile b/board/engicam/icorem6/Makefile
new file mode 100644
index 000..9ec9ecd
--- /dev/null
+++ b/board/engicam/icorem6/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := icorem6.o
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
new file mode 100644
index 000..c9001bc
--- /dev/null
+++ b/board/engicam/icorem6/README
@@ -0,0 +1,28 @@
+How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit:
+-
+
+- Build U-Boot for Engicam i.CoreM6 QDL:
+
+$ make mrproper
+$ make icorem6qdl_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k 

[U-Boot] [PATCH 1/5] imx: iomux-v3: Fix build error with snvs base

[Jagan Teki]

snvs base is added only for i.MX6ULL but the code is
added for common, so firing build error while compiling
other i.MX6 SOC's

Issue observed with the below patch
"imx: mx6ull: Update memory map address"
(sha1: e8eac1b5b3a98a06426bc4867c03c38329841e5c)

Build log:
  CC  arch/arm/imx-common/iomux-v3.o
arch/arm/imx-common/iomux-v3.c: In function 'imx_iomux_v3_setup_pad':
arch/arm/imx-common/iomux-v3.c:56:19: error: 'IOMUXC_SNVS_BASE_ADDR' undeclared 
(first use in this function)
base = (void *)IOMUXC_SNVS_BASE_ADDR;

Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/imx-common/iomux-v3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 78f667e..efb884c 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -50,7 +50,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
if (sel_input_ofs)
sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
}
-#else
+#elif defined(CONFIG_MX6ULL)
if (is_mx6ull()) {
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_SNVS_BASE_ADDR;
-- 
2.7.4

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