Generated by "tools/moveconfig -s".
This will make config moves easier.
Signed-off-by: Masahiro Yamada
---
configs/A10-OLinuXino-Lime_defconfig | 2 +-
configs/A20-OLinuXino-Lime2_defconfig | 2 +-
While I moved the options, I also renamed them so that they are all
prefixed with MMC_SDHCI_.
This commit was created in the following steps.
[1] Rename with the following command
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
This is an user-unconfigurable option that is selected by the
drivers that need to overwrite SDHCI IO memory accessors.
(BCM2835 SDHCI seems the only driver that needs to do so.)
Signed-off-by: Masahiro Yamada
---
drivers/mmc/Kconfig | 8
Currently, CONFIG_MMC is not related to any other options by
"depends on" or "select". One of big advantages of using Kconfig
is automatic dependency tracking, but the current state is lacking
it. As the first step, make the existing MMC driver entries depend
on MMC.
This commit was created by
On Sun, Dec 04, 2016 at 09:58:42AM +0200, Uri Mashiach wrote:
> Hello Tom,
>
> On 12/01/2016 05:36 PM, Tom Rini wrote:
> > On Thu, Dec 01, 2016 at 10:28:12AM +0200, Uri Mashiach wrote:
> >
> >> From: Dmitry Lifshitz
> >>
> >> Features supported :
> >>
> >> * Serial
From: Konstantin Porotchkin
This set of patches is adding more features for bards based on new
Marvell MoChi platforms - Armada-70x0 and Armada-80x0.
The patches were applied on top of Stefan's mvebu-related patch set v2
with the last patch named
"dm: core: Add
From: Konstantin Porotchkin
Add support for mvebu bubt command for flash image
load, check and burn on boot device.
Changes for v2:
- Add "bubt" documentation
- Fix code syntax
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc:
From: Konstantin Porotchkin
Align the Armada-8040-db and Armada-7040-db SPI and I2C
DTS settings with latest DB settings:
- 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO)
- 8040-db: disable cps_i2c0 on CP1
- 8040-db: enable spi1 on CP1 (the new location of
From: Konstantin Porotchkin
Enable mvebu "bubt" command support in the default configuration
file for Armada-7040 and Armada-8040 development boards
Changes for v2:
- Remove Gerrit Change ID
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
From: Konstantin Porotchkin
Add pin control nodes to APN806, CP-master, CP-slave and
Armada-7040 and Armada-8040 boards DTS files
Changes for v2:
- Remove Gerrit Change ID
- Fix comments
- Fix wrong function values
- Add missing cpm_i2c0 node to armada-7040-db.dts
From: Konstantin Porotchkin
Enable mvebu pin control support in the default configuration
files for Armada-7040 and Armada-8040 development boards
Changes for v2:
- Remove Gerrit Change ID
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
From: Konstantin Porotchkin
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in
I wrote a new SDHCI driver for my new SoCs, but before posting it,
I just want to make a clean-base for my driver entry.
Of course, I could enable some needed options in my header file
(for options in the "white-list"), but I just thought it is a good
habit to contribute to Kconfig moves in the
Move CONFIG_SDHCI to Kconfig and rename it to CONFIG_MMC_SDHCI.
My motivation for the rename is, ultimately, to make all the MMC
options prefixed with MMC_ and SDHCI options with MMC_SDHCI_,
like Linux.
This commit was created as follows:
[1] Rename the config option with the following command:
From: Konstantin Porotchkin
Enable PCIe bus support in Armada-7040 DB default configuration
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta Zur Hershkovits
Cc: Omri
From: Konstantin Porotchkin
Add missing L3 cache flush functionality which absence prevents
Linux kernel from normal boot in case the L3 cache is enabled
by ATF.
The L3 cache is named the "last level" cache in order to keep
the terminology similar to the ATF code.
This cache
From: Konstantin Porotchkin
Enable hush parser in Armada-7040 and Armada-8040 DB default
configurations.
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta Zur Hershkovits
From: Konstantin Porotchkin
This set of patches adds features for allowing Linux kernel boot
and root on NFS for Marvell A8K family boards.
These changes were tested when applied on top of previously sent
series of patches named:
"arm64: mvebu: Armada-8K family patches"
On Tue, Nov 22, 2016 at 02:42:56PM +0530, Vignesh R wrote:
> Commit 4c4e3b37750f3("ARM: AM43xx: Enable FIT") accidentally disabled
> DM_SPI and DM_SPI_FLASH. Add back DM_SPI and DM_SPI_FLASH to
> am43xx_evm_defconfig in order to make use of DM framework for QSPI.
>
> Signed-off-by: Vignesh R
On Wed, Nov 23, 2016 at 01:25:24PM +0530, Lokesh Vutla wrote:
> The dra71x-evm is a board based on TI's DRA718 processor targeting
> BOM-optimized
> entry infotainment systems such as display audio and is a software compatible
> derivative of the highly successful DRA74 and DRA72 processor
On Wed, Nov 23, 2016 at 01:25:25PM +0530, Lokesh Vutla wrote:
> Add mux and iodelay settings for dra71x-evm.
> Data generated using PCT_DRA71x_SR2.0_v1.0.0.0 version (June 2016).
>
> Signed-off-by: Lokesh Vutla
> Reviewed-by: Tom Rini
Applied to
On Wed, Nov 23, 2016 at 12:54:41PM +0530, Lokesh Vutla wrote:
> From: Suman Anna
>
> This patch adds support to update the device-tree blob to adjust the
> DSP and IVA DPLL clocks pertinent to the selected OPP choice, with
> the default being OPP_NOM. The voltage settings are
Hi Jagan,
Ping!
> -Original Message-
> From: Siva Durga Prasad Paladugu
> Sent: Tuesday, November 29, 2016 10:30 AM
> To: 'Jagan Teki'
> Cc: u-boot@lists.denx.de; Michal Simek (michal.si...@xilinx.com)
>
> Subject: RE: [U-Boot] Query on
Hi Ronny,
On 1 December 2016 at 04:53, Ronny Ko wrote:
> Hi Simon,
>
> I received the following reply from Minnowboard enginer from intel:
>
>> fTPM is implemented in firmware. Firmware will capture IO transition and
>> show same behavior like dTPM. From user point of view,
Hi,
On 1 December 2016 at 01:39, Stefan Roese wrote:
> (Adding Simon and Maxim to Cc)
>
> On 23.11.2016 16:12, Mario Six wrote:
>>
>> Certain boards come in different variations by way of utilizing daughter
>> boards, for example. These boards might contain additional chips, which
On 1 December 2016 at 01:42, Stefan Roese wrote:
> (Adding Simon to Cc)
>
> On 23.11.2016 16:12, Mario Six wrote:
>>
>> This patch adds a function to the TPM library, which allows U-Boot to
>> flush resources, e.g. keys, from the TPM.
>>
>> Signed-off-by: Mario Six
Hi Markus,
On 1 December 2016 at 01:58, Markus Valentin wrote:
> Hi Simon,
> Am Mittwoch, den 30.11.2016, 19:20 -0700 schrieb Simon Glass:
>> Hi Markus,
>>
>> On 30 November 2016 at 04:32, Markus Valentin wrote:
>> >
>> > Hi,
>> >
>> > im trying to run u-boot as
On 1 December 2016 at 03:23, Jaehoon Chung wrote:
> On 12/01/2016 07:09 PM, Michal Simek wrote:
>> The patch
>> "dm: spl: mmc: Support CONFIG_BLK in SPL MMC"
>> (sha1: 87bce4e5c0b55452d70830928b2d7b98fa24d4e3)
>> converted FAT part of spl_mmc_do_fs_boot() but forget to
On 1 December 2016 at 00:40, Marcel Ziswiler wrote:
>
>
> On December 1, 2016 3:20:55 AM GMT+01:00, Simon Glass
> wrote:
>>Hi Marcel,
>>
>>On 30 November 2016 at 09:47, Marcel Ziswiler
>>wrote:
>>> From: Marcel Ziswiler
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> For boards that call s_init() when the SPL runs, we are expected to
> setup an early stack before calling this C function.
> Implement the proper AArch64 version of this based on the ARMv7 code.
> This allows
The predominantely 32-bit ARM targets try to compile the SPL in Thumb
mode to reduce code size.
The 64-bit AArch64 instruction set does not know an alternative, concise
encoding, so the Thumb build option should only be set for 32-bit
targets.
Likewise -marm machine options are only valid for
These days many Allwinner SoCs use clock_sun6i.c, although out of them
only the (original sun6i) A31 has a second MBUS clock register.
Also the requirement for setting up the PRCM PLL_CTLR1 register to provide
the proper voltage seems to be a property of older SoCs only as well.
Restrict the MBUS
From: Jens Kuske
The A64 DRAM controller is very similar to the H3 one,
so the code can be reused with some small changes.
[Andre: fixed up typo, merged in fixes from Jens]
Signed-off-by: Jens Kuske
Signed-off-by: Andre Przywara
According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.
Reported-by: Jens Kuske
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
1 file changed, 1
Now that the SPL is ready to be compiled in AArch64 and the DRAM
init code is ready, enable SPL support for the A64 SoC and in the
Pine64 defconfig.
For now we keep the boot0 header in the U-Boot proper, as this allows
to still use boot0 as an SPL replacement without hurting the SPL use
case.
We
From: Jens Kuske
The IOCR registers got renamed to BDLR to match the public
documentation of similar controllers.
Signed-off-by: Jens Kuske
Signed-off-by: Andre Przywara
---
arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 43
From: Jens Kuske
Instead of setting the delay for whole bytes allow setting
it for each individual bit. Also add support for
address/command lane delays.
Signed-off-by: Jens Kuske
Signed-off-by: Andre Przywara
---
The ARMv8 capable Allwinner A64 SoC comes out of reset in AArch32 mode.
To run AArch64 code, we have to trigger a warm reset via the RMR register,
which proceeds with code execution at the address stored in the RVBAR
register.
If the bootable payload in the FIT image is using a different
Fix the output of the DRAM size on AArch64 SPLs.
Signed-off-by: Andre Przywara
Reviewed-by: Alexander Graf
---
arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c
The Allwinner A64 SoC starts execution in AArch32 mode, and both
the boot ROM and Allwinner's boot0 keep running in this mode.
So U-Boot gets entered in 32-bit, although we want it to run in AArch64.
By using a "magic" instruction, which happens to be an almost-NOP in
AArch64 and a branch in
To avoid enumerating the very same DRAM values in defconfig files
for each and every Allwinner A64 board out there, let's put some sane
default values in the Kconfig file.
Boards with different needs can override them at any time.
Signed-off-by: Andre Przywara
---
Read the specified "arch" value from a legacy or FIT U-Boot image and
store it in our SPL data structure.
This allows loaders to take the target architecture in account for
custom loading procedures.
Having the complete string -> arch mapping for FIT based images in the
SPL would be too big, so we
The boot0 hook we have so far is applied _after_ the initial branch
to the "reset" entry point. An upcoming change requires even this
branch to be changed, so we apply the hook macro at the earliest
point, and have the branch in the hook file as well.
This is no functional change at this point,
Hi Stefan,
On 12/02/2016 10:24 PM, stefan.herbrechtsme...@weidmueller.de wrote:
> From: Stefan Herbrechtsmeier
>
>
> The sdhci controller assumes that the base clock frequency is fully
> supported by the peripheral and doesn't support hardware
On 1 December 2016 at 08:14, wrote:
> From: Yehuda Yitschak
>
> Currently the PCI command only allows to see the BAR register
> values but not the size and actual base address.
> This little extension parses the BAR registers and displays
> the base,
Hi Stephen,
On 2 December 2016 at 12:19, Stephen Warren wrote:
> On 11/30/2016 07:19 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 29 November 2016 at 21:09, Stephen Warren
>> wrote:
>>>
>>> On 11/28/2016 03:09 PM, Simon Glass wrote:
On 2 December 2016 at 12:26, Stephen Warren wrote:
> From: Stephen Warren
>
> Some users may wish to pass the cboot-supplied DTB to the booted kernel
> rather than having U-Boot load the DTB itself. To allow this, expose the
> address of the
Hi Oliver,
On 2 December 2016 at 03:16, Olliver Schinagl wrote:
> Hey Joe,
>
>
>
> On 30-11-16 21:40, Joe Hershberger wrote:
>>
>> On Fri, Nov 25, 2016 at 9:30 AM, Olliver Schinagl
>> wrote:
>>>
>>> This patch adds a method for the board to set the MAC
Hi Tomas,
On 1 December 2016 at 05:21, Tomas Melin wrote:
> Enable support for loading a splash image from within a FIT image.
> The image is assumed to be generated with mkimage -E flag to hold
> the data external to the FIT.
>
> Signed-off-by: Tomas Melin
Hi Jagan,
On 1 December 2016 at 05:45, Jagan Teki wrote:
> On Wed, Nov 30, 2016 at 8:30 AM, Simon Glass wrote:
>> At present an invalid bus width prints a message but does not return an
>> error. This is the opposite of the correct behaviour. Adjust it to
On 1 December 2016 at 05:21, Tomas Melin wrote:
> Sort include files in accordance to u-boot coding style.
>
> Signed-off-by: Tomas Melin
> ---
> common/splash_source.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
On Wed, Nov 16, 2016 at 12:50:16AM +, Andre Przywara wrote:
> The shortname variable isn't referenced anywhere in the code, so just
> remove it.
>
> Pointed out by a GCC 6.2 default warning option.
>
> Signed-off-by: Andre Przywara
> Reviewed-by: Marek Vasut
On Mon, Nov 21, 2016 at 02:37:09PM -0600, Andrew F. Davis wrote:
> After an image is selected out of a FIT blob for further processing we
> run an optional, platform specific, post-processing function on this
> component. This post-processing may modify the position and size of the
> image, so
On Wed, Nov 23, 2016 at 01:25:27PM +0530, Lokesh Vutla wrote:
> From: Keerthy
>
> Add the pmic_data for LP873x PMIC which is used to power
> up dra71x-evm.
>
> Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating
> the efuse registers only to use OPP_NOM
On Wed, Nov 23, 2016 at 01:25:30PM +0530, Lokesh Vutla wrote:
> Add DT support for dra71-evm and built it as part of FIT image.
>
> Signed-off-by: Lokesh Vutla
> Reviewed-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
On Wed, Nov 23, 2016 at 01:25:29PM +0530, Lokesh Vutla wrote:
> Sync all dra7xx based dts files with latest Linux
>
> Signed-off-by: Lokesh Vutla
> Reviewed-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital
On Wed, Nov 23, 2016 at 01:25:26PM +0530, Lokesh Vutla wrote:
> From: Nishanth Menon
>
> Rev C version of EVM does require IODelay to be configured for RGMII
> pins in MANUAL_1 configuration. Update the same based on PG2.0 initial
> simulation values.
> Data based on
On Wed, Nov 23, 2016 at 01:25:28PM +0530, Lokesh Vutla wrote:
> Palmas driver assumes it is always TPS659xx regulator on all DRA7xx based
> boards to enable mmc regulator. This is not true always like in case of
> DRA71x-evm. So get this information based on the board.
>
> Signed-off-by: Lokesh
On Sun, Dec 04, 2016 at 05:21:14PM -0500, Tom Rini wrote:
> We are tight on space on this board so drop SPL_OS_BOOT
>
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
On Fri, Nov 25, 2016 at 11:14:26AM +0530, Lokesh Vutla wrote:
> There are certain environment variables whose length is greater than
> the defined IO buffer size. So, increase the IO buffer size to print the
> entire variables.
>
> Signed-off-by: Lokesh Vutla
> Reviewed-by:
For boards that call s_init() when the SPL runs, we are expected to
setup an early stack before calling this C function.
Implement the proper AArch64 version of this based on the ARMv7 code.
This allows sunxi boards to setup the basic peripherals even on with a
64-bit SPL.
Signed-off-by: Andre
Hi,
this is the second spin of the SPL support series for the Allwinner A64
SoC. Thanks for the review comments, I hope I addressed all of them.
As v1, this one includes support for both AArch64 and AArch32 SPL
builds. The FIT support is still missing, which means the functionality is
limited.
The UL() macro is pretty useful in sharing constants between assembly
and C files while still being able to specify a type for C.
Move the macro from an armv8 specific header into a common header file
to be able to use it by arm code (for instance) as well.
Signed-off-by: Andre Przywara
tiny-printf does not know about the "l" modifier so far, which breaks
the crash dump on AArch64, because it uses %lx to print the registers.
Add an easy way of handling longs correctly. Also there are printfs
using the '-' modifier, which we choose to ignore for simplicity.
Using a relatively
Since entry_point and load_addr are addresses, they should be
represented as longs to cover the whole address space and to avoid
warning when compiling the SPL in 64-bit.
Also adjust debug prints to add the 'l' specifier, where needed.
Signed-off-by: Andre Przywara
For prepending some board specific header area to U-Boot images we
were so far including a header file with a macro definition containing
the actual header specification.
This works fine if there are just a few statements and if there is only
one alternative.
However adding more complex code
The sunxi DRAM setup code needs an sdelay() implementation, which
wasn't defined for armv8 so far.
Shamelessly copy the armv7 version and adjust it to work in AArch64.
Signed-off-by: Andre Przywara
---
arch/arm/cpu/armv8/cpu.c | 13 +
1 file changed, 13
The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with
other boards. To allow alternative code to be inserted, we create
another, now function specific config symbol on top of it to simplify
later additions. No functional change at this time.
Signed-off-by: Andre Przywara
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> The UL() macro is pretty useful in sharing constants between assembly
> and C files while still being able to specify a type for C.
> Move the macro from an armv8 specific header into a common header file
> to
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> The sunxi DRAM setup code needs an sdelay() implementation, which
> wasn't defined for armv8 so far.
> Shamelessly copy the armv7 version and adjust it to work in AArch64.
>
> Signed-off-by: Andre Przywara
On 4 December 2016 at 18:52, Andre Przywara wrote:
> Since entry_point and load_addr are addresses, they should be
> represented as longs to cover the whole address space and to avoid
> warning when compiling the SPL in 64-bit.
> Also adjust debug prints to add the 'l'
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> The Allwinner A64 SoC starts execution in AArch32 mode, and both
> the boot ROM and Allwinner's boot0 keep running in this mode.
> So U-Boot gets entered in 32-bit, although we want it to run in AArch64.
>
>
On 4 December 2016 at 18:52, Andre Przywara wrote:
> For prepending some board specific header area to U-Boot images we
> were so far including a header file with a macro definition containing
> the actual header specification.
> This works fine if there are just a few
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> The boot0 hook we have so far is applied _after_ the initial branch
> to the "reset" entry point. An upcoming change requires even this
> branch to be changed, so we apply the hook macro at the earliest
>
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> From: Jens Kuske
>
> The IOCR registers got renamed to BDLR to match the public
> documentation of similar controllers.
>
> Signed-off-by: Jens Kuske
>
Hi Kostya,
On 4 December 2016 at 09:12, wrote:
> From: Konstantin Porotchkin
>
> Add a DM port of Marvell pin control driver.
> The A8K SoC family contains several silicone dies interconnected
> in a single package. Every die is normally equipped with
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> From: Jens Kuske
>
> Instead of setting the delay for whole bytes allow setting
> it for each individual bit. Also add support for
> address/command lane delays.
>
> Signed-off-by: Jens
On 4 December 2016 at 18:52, Andre Przywara wrote:
> tiny-printf does not know about the "l" modifier so far, which breaks
> the crash dump on AArch64, because it uses %lx to print the registers.
> Add an easy way of handling longs correctly. Also there are printfs
> using
On 4 December 2016 at 18:52, Andre Przywara wrote:
> The predominantely 32-bit ARM targets try to compile the SPL in Thumb
> mode to reduce code size.
> The 64-bit AArch64 instruction set does not know an alternative, concise
> encoding, so the Thumb build option should
On 4 December 2016 at 18:52, Andre Przywara wrote:
> These days many Allwinner SoCs use clock_sun6i.c, although out of them
> only the (original sun6i) A31 has a second MBUS clock register.
> Also the requirement for setting up the PRCM PLL_CTLR1 register to provide
> the
On 4 December 2016 at 18:52, Andre Przywara wrote:
> The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with
> other boards. To allow alternative code to be inserted, we create
> another, now function specific config symbol on top of it to simplify
> later
On 4 December 2016 at 18:52, Andre Przywara wrote:
> To avoid enumerating the very same DRAM values in defconfig files
> for each and every Allwinner A64 board out there, let's put some sane
> default values in the Kconfig file.
> Boards with different needs can override
At the moment we use the arch/arm directory for arm64 boards as well,
so the Makefile will pick up the "arm" name for the architecture to use
for tagging binaries in U-Boot image files.
Differentiate between the two by looking at the CPU variable being defined
to "armv8", and use the arm64
Since the SPL FIT loader can now differentiate between different
architectures, teach it how to tell arm and arm64 apart when a FIT
image is used.
We just support those two for now, as these are so far the only sensible
alternatives.
Signed-off-by: Andre Przywara
When compiling the SPL for the Allwinner A64 in AArch64 mode, we can't
use the more compact Thumb2 encoding, which only exists for AArch32
code. This makes the SPL rather big, up to a point where any code
additions or even a different compiler may easily exceed the 32KB limit
that the Allwinner
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> From: Jens Kuske
>
> The A64 DRAM controller is very similar to the H3 one,
> so the code can be reused with some small changes.
Yes but it makes the code a mess. Can you avoid putting
On 4 December 2016 at 18:52, Andre Przywara wrote:
> Now that the SPL is ready to be compiled in AArch64 and the DRAM
> init code is ready, enable SPL support for the A64 SoC and in the
> Pine64 defconfig.
> For now we keep the boot0 header in the U-Boot proper, as this
On 4 December 2016 at 18:52, Andre Przywara wrote:
> Fix the output of the DRAM size on AArch64 SPLs.
>
> Signed-off-by: Andre Przywara
> Reviewed-by: Alexander Graf
> ---
> arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
> 1 file
On 4 December 2016 at 18:52, Andre Przywara wrote:
> According to Jens disabling the on-die-termination should set bit 5,
> not bit 1 in the respective register. Fix this.
>
> Reported-by: Jens Kuske
> Signed-off-by: Andre Przywara
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> The ARMv8 capable Allwinner A64 SoC comes out of reset in AArch32 mode.
> To run AArch64 code, we have to trigger a warm reset via the RMR register,
> which proceeds with code execution at the address stored
Hi Andre,
On 4 December 2016 at 18:52, Andre Przywara wrote:
> When compiling the SPL for the Allwinner A64 in AArch64 mode, we can't
> use the more compact Thumb2 encoding, which only exists for AArch32
> code. This makes the SPL rather big, up to a point where any code
On Mon, Dec 05, 2016 at 01:52:09AM +, Andre Przywara wrote:
> The predominantely 32-bit ARM targets try to compile the SPL in Thumb
> mode to reduce code size.
> The 64-bit AArch64 instruction set does not know an alternative, concise
> encoding, so the Thumb build option should only be set
Enable support for loading a splash image from within a FIT image.
The image is assumed to be generated with mkimage -E flag to hold
the data external to the FIT.
Signed-off-by: Tomas Melin
---
Changes in v4:
- Added missing changelog
Changes in v3:
- Add documentation
Sort include files in accordance to u-boot coding style.
Signed-off-by: Tomas Melin
---
Changes in v4:
- Added missing changelog
Changes in v3:
- Change patch order so that include sort patch comes prior to adding
new include
Changes in v2:
- Add separate patch for
On Mon, Dec 05, 2016 at 01:52:08AM +, Andre Przywara wrote:
> These days many Allwinner SoCs use clock_sun6i.c, although out of them
> only the (original sun6i) A31 has a second MBUS clock register.
> Also the requirement for setting up the PRCM PLL_CTLR1 register to provide
> the proper
On Mon, Dec 5, 2016 at 2:26 PM, Simon Glass wrote:
> Hi Andre,
>
> On 4 December 2016 at 18:52, Andre Przywara wrote:
>> From: Jens Kuske
>>
>> Instead of setting the delay for whole bytes allow setting
>> it for each individual
Hi.
Recently a check was added to if new ad-hoc CONFIG options where added
and produced an error. The exact commit is [1].
While building (2016.11) with some out of tree files in include folder
I get the following error:
Build error:
| Error: You must add new CONFIG options using Kconfig
| The
On Wed, Nov 23, 2016 at 01:26:10AM -0500, Walt Feasel wrote:
> Make checkpatch style modification for
> CHECK: Alignment should match open parenthesis
>
> Signed-off-by: Walt Feasel
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Nov 23, 2016 at 01:25:33PM +0530, Lokesh Vutla wrote:
> Enable pmic/regulator config options.
>
> Signed-off-by: Lokesh Vutla
> Reviewed-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Nov 23, 2016 at 01:25:32PM +0530, Lokesh Vutla wrote:
> Enable DM_ETH for hs boards.
>
> Signed-off-by: Lokesh Vutla
> Reviewed-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
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