Re: [U-Boot] am335x based board nand boot crashes to ubi0 error

It seems that http://www.denx.de/wiki/publish/DULG/DULG-enbw_cmc.html#Section_9.1.5.2. Chapter 9.1.5.3.4. Installing UBI images (if no UBI Volumes exist): is mentioning a problem like this. Figures in error message are swapped, though. Anyhow, the root problem could be the fact that my ubiformat

[U-Boot] [PATCHv2 2/2] ARMv8/fsl-layerscape: Enable data coherency between cores in cluster

From: Hou Zhiqiang Signed-off-by: Hou Zhiqiang --- V2: - No change arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig

[U-Boot] [PATCHv2 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

From: Mingkai Hu For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables

[U-Boot] [v3 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10

From: Tien Fong Chee Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Reviewed-by: Stefan Roese Cc: Marek Vasut Cc:

[U-Boot] [v3 02/30] arm: socfpga: arria10: add sdram defines for Arria10

From: Tien Fong Chee Add the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc:

Re: [U-Boot] [PATCHv2 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

Hi. 2017-01-06 18:41 GMT+09:00 Zhiqiang Hou : > From: Mingkai Hu > > For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is > set. The SMPEN bit should be set before enabling the data cache. > If not enabled, the cache is not coherent

[U-Boot] [v3 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Tien Fong Chee Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut

[U-Boot] [v3 08/30] arm: socfpga: arria10: add config option build for arria10

From: Tien Fong Chee Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [v3 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Tien Fong Chee Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut Cc: Dinh

[U-Boot] [v3 09/30] arm: socfpga: add define for bootinfo bsel bit shift

From: Tien Fong Chee On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by: Dinh

[U-Boot] [v3 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits

From: Tien Fong Chee There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee

[U-Boot] [v3 10/30] arm: socfpga: arria10: add reset manager for Arria10

From: Tien Fong Chee Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v3 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10

From: Tien Fong Chee The Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen

[U-Boot] [v3 13/30] arm: socfpga: arria10 fpga does not have bridges mapped

From: Tien Fong Chee On the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v3 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices

From: Tien Fong Chee The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut

[U-Boot] [v3 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

From: Tien Fong Chee Add base address header file for Stratix10 SoC Signed-off-by: Chin Liang See Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ley Foon

[U-Boot] [v3 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10

From: Tien Fong Chee On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset

[U-Boot] [v3 16/30] arm: socfpga: add reset manager defines for Arria10

From: Tien Fong Chee Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong

[U-Boot] [v3 14/30] arm: socfpga: arria10: remove board_init and s_init

From: Tien Fong Chee These functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

Re: [U-Boot] rockchip: rk3288: Possible regression in sdram setup

Add Rockchip Engineers to Cc: Le 06/01/2017 à 11:28, Romain Perier a écrit : Hello, I have a strange behaviour with the SPL on rk3288. When I build u-boot-rockchip master for the rock2 (rock2_defconfig), I can easily start u-boot SPL and u-boot from an sdcard (the emmc boot partition is

[U-Boot] [v3 04/30] arm: socfpga: arria10: add system manager defines

From: Tien Fong Chee Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v3 05/30] arm: socfpga: arria10: add misc functions for Arria10

From: Tien Fong Chee Add arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen Signed-off-by: Tien

[U-Boot] [v3 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK

From: Tien Fong Chee Add minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v3 20/30] arm: socfpga: arria10: Enable SPL for Arria 10

From: Tien Fong Chee This patch enables SPL build and implementation for Arria 10. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [v3 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

From: Tien Fong Chee This is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v3 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for v3 - no changes changes

[U-Boot] [v3 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions. and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh

[U-Boot] [v3 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

From: Tien Fong Chee Drivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively. Signed-off-by: Tien Fong Chee

[U-Boot] [v3 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro

From: Tien Fong Chee These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [v3 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V3 - no changes Changes

[U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

From: Tien Fong Chee Enhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v3 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek

[U-Boot] [v3 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

From: Tien Fong Chee This patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang

[U-Boot] [v3 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V3 - no changes Changes

[U-Boot] [v3 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL.

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V3 - no changes Changes

Re: [U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig

On 01/05/2017 05:28 AM, Tom Rini wrote: > On Wed, Dec 28, 2016 at 08:43:26AM -0800, York Sun wrote: > >> In this set, more mpc85xx config options are moved into Kconfig, including >> some shared configuration for DDR, crypto, mmc, etc. >> >> York Sun (24): >> powerpc: E500: Move CONFIG_E500 and

[U-Boot] [PATCH] powerpc: Enable flush and invalidate dcache by range for MPC85xx

Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-ops for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues in some drivers when the dcache was flushed. While the root cause was under

[U-Boot] usb start hangs

Hi - We recently updated our U-Boot release to v2016.11 and now our USB devices don't work. When usb start is executed with a device inserted it hangs at 'scanning bus 0 for devices...' and doesn't recover. Our product uses an NXP T2081 and I can reproduce this issue on the T2080RDB

Re: [U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig

On 01/05/2017 05:28 AM, Tom Rini wrote: > > There were a few minor problems in this series which I fixed up. The > only remaining "issue" here is that sbc8641d has a ~3KiB size increase. > This is due to the issue that previously it did _not_ define > CONFIG_SYS_FSL_DDR2 but only

[U-Boot] Create ramdisk image

Hello, In order to create a ram disk image I'm running: genext2fs -d /local/rootfs -b 16384 -D rootfs_devices.tab ramdisk.img gzip -v9 ramdisk.img mkimage -A ARM -T ramdisk -C gzip -n 'Ramdisk Image' -d ramdisk.img.gz uRootfs.gz Am I right ? I'm asking because upon boot I'm getting:

Re: [U-Boot] [PATCHv2 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

On 01/06/2017 03:19 AM, Masahiro Yamada wrote: > Hi. > > > 2017-01-06 18:41 GMT+09:00 Zhiqiang Hou : >> From: Mingkai Hu >> >> For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is >> set. The SMPEN bit should be set before enabling the

Re: [U-Boot] [v3 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

On 01/06/2017 05:19 AM, Chee Tien Fong wrote: From: Tien Fong Chee Enhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh

[U-Boot] [PATCH v2 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

Revision 1.0 of this IP has a couple of issues, such as not supporting repeated start conditions for read transfers. So scan through the list of i2c messages for these conditions and report an error if they are attempted. This has been fixed for revision 1.4 of the IP, so only report the error

[U-Boot] [PATCH v2 3/4] i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0

Revision 1.0 of this IP has a quirk where if during a long read transfer the transfer_size register will go to 0, the master will send a NACK to the slave prematurely. The way to work around this is to reprogram the transfer_size register mid-transfer when the only the receive fifo is known full,

[U-Boot] [PATCH 1/2] spl: Move check for SPL_LIBCOMMON support to header

Print statements in SPL depend on lib/common support, so many such statements are ifdef'd, move the check to the common.h header and remove these inline checks. Signed-off-by: Andrew F. Davis --- common/spl/spl.c | 2 -- common/spl/spl_ext.c | 8

[U-Boot] [PATCH] mkimage: Add support for signing with pkcs11

Add support for signing with the pkcs11 engine. This allows FIT images to be signed with keys securely stored on a smartcard, hardware security module, etc without exposing the keys. Support for other engines can be added in the future by modifying rsa_engine_get_pub_key() and

Re: [U-Boot] [PATCH 1/2] spl: Move check for SPL_LIBCOMMON support to header

This is not based on the latest upstream, please ignore. Sorry for the noise. Andrew On 01/06/2017 01:09 PM, Andrew F. Davis wrote: > Print statements in SPL depend on lib/common support, so many such > statements are ifdef'd, move the check to the common.h header and > remove these inline

[U-Boot] [PATCH 2/2] spl: Remove inline ifdef check for EXT and FAT support

These files are only included for build by the make system when CONFIG_SPL_{EXT,FAT}_SUPPORT is enabled, remove the unneed checks for these in the source files. Signed-off-by: Andrew F. Davis --- common/spl/spl_ext.c | 2 -- common/spl/spl_fat.c | 2 -- 2 files changed, 4

[U-Boot] [PATCH 1/2] spl: Move check for SPL_LIBCOMMON support to header

Print statements in SPL depend on lib/common support, so many such statements are ifdef'd, move the check to the common.h header and remove these inline checks. Signed-off-by: Andrew F. Davis --- common/spl/spl.c | 2 -- common/spl/spl_ext.c | 8

[U-Boot] [PATCH 2/2] spl: Remove inline ifdef check for EXT and FAT support

These files are only included for build by the make system when CONFIG_SPL_{EXT,FAT}_SUPPORT is enabled, remove the unneed checks for these in the source files. Signed-off-by: Andrew F. Davis --- common/spl/spl_ext.c | 2 -- common/spl/spl_fat.c | 2 -- 2 files changed, 4

Re: [U-Boot] [PATCH] powerpc: mpc83xx: Enable pre-relocation malloc

On Fri, 2017-01-06 at 14:56 +0100, Mario Six wrote: > To enable DM on MPC83xx, we need pre-relocation malloc, which is > implemented in this patch. > Would be nice if you could avoid using r1, each time you modify r1 gdb will be upset/confused if you ever try to debug start.S with gdb. I guess

[U-Boot] [PATCH v2 2/4] i2c: i2c-cdns: Reorder timeout loop for interrupt waiting

Reorder the timeout loop such that we first check if the condition is already true, and then call udelay() so if the condition is already true, break early. Reviewed-by: Michal Simek Signed-off-by: Moritz Fischer Cc: Heiko Schocher

[U-Boot] [PATCH v2 4/4] i2c: i2c-cdns: No need for dedicated probe function

The generic probe code in dm works, so get rid of the leftover cruft. Signed-off-by: Moritz Fischer Cc: Heiko Schocher Cc: Michal Simek Cc: u-boot@lists.denx.de --- Changes from v1: - None --- drivers/i2c/i2c-cdns.c | 21

[U-Boot] [PATCH] Makefile: Make EFI build quiet

Make building EFI example less noisy. Signed-off-by: Andrew F. Davis --- scripts/Makefile.lib | 16 +++- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 13c975b8a4..81ac7eb12c 100644 ---

[U-Boot] [PATCH] am335x: configs: Use ISW_ENTRY_ADDR to set SPL_TEXT_BASE

The SPL load address changes based on boot type in HS devices, ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs for similar reasons. Add this same logic for AM33xx devices. Also make the default value for ISW_ENTRY_ADDR correct for GP devices based on SoC, HS devices already pick

[U-Boot] [PATCH 1/1] arm: mach-omap2: Fix secure file generation

When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was not generated but generate an unsigned one anyway, first fix this warning to say that it was generated but not secured. When the user then exports TI_SECURE_DEV_PKG after getting this warning, and tries to re-build, 'make'

Re: [U-Boot] [v3 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

On 01/06/2017 05:19 AM, Chee Tien Fong wrote: From: Tien Fong Chee Drivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively.

Re: [U-Boot] [PATCH] README: mxc_hab: Adapt the CONFIG_SECURE_BOOT text to Kconfig

Hi Fabio On Thu, Jan 05, 2017 at 09:33:08PM -0200, Fabio Estevam wrote: > From: Fabio Estevam > > Commit 6e1f4d2652e79 ("arm: imx-common: add SECURE_BOOT option to > Kconfig") moved the CONFIG_SECURE_BOOT option to Kconfig, so update > the mxc_hab README file to reflect

[U-Boot] [PATCH] powerpc: mpc83xx: Enable pre-relocation malloc

To enable DM on MPC83xx, we need pre-relocation malloc, which is implemented in this patch. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/cpu_init.c| 3 +-- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 4 +--- arch/powerpc/cpu/mpc83xx/start.S | 23

[U-Boot] [PATCH] arm: PSCI: remove CONFIG_MP to support LS1012A

To support PSCI on LS1012A, remove the macro CONFIG_MP. And, do code cleanup. Signed-off-by: Chenhui Zhao --- arch/arm/cpu/armv8/cpu-dt.c | 14 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 33 +--

Re: [U-Boot] [PATCH v4] BOARD: MCCMON6: Provide support for iMX6q based mccmon6 board

Hi Stefano, Thank you for the review. > Hi Lukasz, > > On 02/01/2017 15:51, Lukasz Majewski wrote: > > This patch provides u-boot support for Liebherr (LWN) mccmon6 board. > > > > Signed-off-by: Lukasz Majewski > > --- > > Changes for v4: > > - Update

[U-Boot] rockchip: rk3288: Possible regression in sdram setup

Hello, I have a strange behaviour with the SPL on rk3288. When I build u-boot-rockchip master for the rock2 (rock2_defconfig), I can easily start u-boot SPL and u-boot from an sdcard (the emmc boot partition is erased so my board starts in maskrom mode by default) without any issues. Now,

Re: [U-Boot] [PATCH][v3] armv8: fsl-layerscape: Add support of GPIO structure

Hi York > -Original Message- > From: york sun > Sent: Thursday, January 05, 2017 1:28 AM > To: Prabhakar Kushwaha ; u- > b...@lists.denx.de > Cc: Mingkai Hu ; Pratiyush Srivastava > > Subject: Re: [PATCH][v3]

Re: [U-Boot] [u-boot-release] [PATCH] arm: PSCI: remove CONFIG_MP to support LS1012A

On 01/06/2017 02:16 AM, Chenhui Zhao wrote: > To support PSCI on LS1012A, remove the macro CONFIG_MP. > And, do code cleanup. > > Signed-off-by: Chenhui Zhao > --- > arch/arm/cpu/armv8/cpu-dt.c | 14 > arch/arm/cpu/armv8/fsl-layerscape/cpu.c

Re: [U-Boot] [PATCH][v3] armv8: fsl-layerscape: Add support of GPIO structure

On 01/06/2017 04:02 AM, Prabhakar Kushwaha wrote: >> Prabhakar, >> >> My comment to your v1 still stands. You didn't use this structure for >> lsch2. Do you have follow-up patches? >> > > This structure is required while supporting Ethernet in LS1012AFRDM. > Ethernet support will be added in

Re: [U-Boot] [PATCH] powerpc: mpc83xx: Enable pre-relocation malloc

On 01/06/2017 05:57 AM, Mario Six wrote: > To enable DM on MPC83xx, we need pre-relocation malloc, which is > implemented in this patch. > > Signed-off-by: Mario Six > --- > arch/powerpc/cpu/mpc83xx/cpu_init.c| 3 +-- > arch/powerpc/cpu/mpc83xx/spl_minimal.c | 4 +--- >