On Mon, Jan 9, 2017 at 7:45 AM, Wolfgang Denk wrote:
> Dear Chris,
>
> In message
> you
> wrote:
>>
>> > The old code was forgiving and would accept 192,168,1,2 as well.
>>
>> Technically you can't enter that. The env_flags.c code prevents that
>> from being added to environment variables that
Using enum simplify handling of different bitstream command
types.
Signed-off-by: Michal Simek
---
cmd/fpga.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/cmd/fpga.c b/cmd/fpga.c
index 8956eb1b654a..016349f56086 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga
Hi Boris,
On Wed, Jan 04, 2017 at 10:10:56AM +0100, Boris Brezillon wrote:
> Hi Maxime,
>
> On Tue, 22 Nov 2016 13:38:36 +0100
> Maxime Ripard wrote:
>
> > CMD_MTDPARTS is something the user might or might not want to select, and
> > might depends on (or be selected by) other options too.
> >
I made two trials with NANDARGS/nandroot variable in
include/configs/am335x_evm.h that made booting work:
nandroot 'ubi0:rootfs rw ubi.mtd=NAND.file-system,512'
and
nandroot 'ubi0:rootfs rw ubi.mtd=NAND.file-system'
However, nandroot 'ubi0:rootfs rw ubi.mtd=NAND.file-system,2048' did not
work as VI
Xilinx ATF extending options for passing images from BL2(FSBL)
to BL31. U-Boot SPL is FSBL replacement that's why it should generate
handoff structure the same. Support only one entry which is U-Boot in
EL2 itself. When FIT image is adopted structure generate should be data
driven.
Currently ATF i
On Fri, Jan 06, 2017 at 06:55:05AM +0800, Icenowy Zheng wrote:
> > > + MCTL_CR_32BIT /* fixme, thats wrong but what boot0 does */ |
> >
> > What's wrong about it?
>
> V3s DRAM seems to be 16-bit.
>
> However, boot0 has this bit set, and without this bit, it cannot work.
>
> According to
Right now the SPL is trying to load u-boot based on defines, i.e. one
has to define CONFIG_SPL_NAND_SIMPLE to boot from NAND,
or CONFIG_SPL_SPI_LOAD to boot from SPI FLASH, etc...
This prevent us from having a single SPL image that is able to boot from
all media, and one need to build an image for
Right now the SPL is trying to load u-boot based on defines, i.e. one has to
define CONFIG_SPL_NAND_SIMPLE to boot from NAND, or CONFIG_SPL_SPI_LOAD to boot
from SPI FLASH, etc...
This prevent us from having a single SPL image that is able to boot from all
media, and one need to build an image for
Enable SPL MMC support in order to allow to build a single u-boot image
that is able to boot from MMC and NAND devices.
Signed-off-by: Fabien Parent
---
configs/omapl138_lcdk_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_def
Small clean-up.
Signed-off-by: Fabien Parent
---
include/configs/omapl138_lcdk.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index cdc93c38c8..15e900f6e2 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs
Replace hardcoded value with defined constant SECTOR_BYTES.
Signed-off-by: Ladislav Michl
---
drivers/mtd/nand/omap_gpmc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index d1e1bdda28..f4f0de395b 100644
-
fdt_fixup_mtdparts currently does nothing when partitin info is
runtime generated or compiled-in defaults are used.
Signed-off-by: Ladislav Michl
---
common/fdt_support.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index c9f7019e38..a57a575
SPL partition size depends on sector size and we want kernel to use
the same layout, so let U-Boot modify FDT accordingly.
Signed-off-by: Ladislav Michl
---
board/isee/igep00x0/igep00x0.c | 17 +
configs/igep0020_defconfig | 2 ++
configs/igep0030_defconfig | 2 ++
conf
Hi,
On 05/01/17 22:55, Icenowy Zheng wrote:
>
> 2017年1月6日 06:37于 Maxime Ripard 写道：
>>
>> On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote:
>>> H3-like DRAM controller needs some special code to operate a DDR2 DRAM
>>> chip. Add the logic to probe such a chip.
Out of curiosity, ho
Boards with NAND and OneNAND are supported by single configuration,
thus remove now obsolete IGEP0020_NAND BOARD entry.
Signed-off-by: Ladislav Michl
---
board/isee/igep00x0/MAINTAINERS | 6 --
1 file changed, 6 deletions(-)
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0
Signed-off-by: Ladislav Michl
---
lib/efi_loader/.gitignore | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/efi_loader/.gitignore b/lib/efi_loader/.gitignore
new file mode 100644
index 00..634a600f84
--- /dev/null
+++ b/lib/efi_loader/.gitignore
@@ -0,0 +1,2 @@
+*.efi
+*.so
--
On Fri, Jan 06, 2017 at 07:13:17AM +0800, Icenowy Zheng wrote:
>
>
> 06.01.2017, 06:16, "Maxime Ripard" :
> > On Thu, Dec 29, 2016 at 02:50:48AM +0800, Icenowy Zheng wrote:
> >> Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
> >> DesignWare DRAM controller, which do not have of
On Jum, 2017-01-06 at 17:03 -0600, Dinh Nguyen wrote:
>
> On 01/06/2017 05:19 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee
> >
> > Drivers for reset manager is restructured such that common
> > functions,
> > gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> > reset_man
From: Tien Fong Chee
Add remaining 3 I2C base addresses for the Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Reviewed-by: Stefan Roese
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h |3 +++
From: Tien Fong Chee
Add the structures for the SDRAM controller on Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380
1 file
From: Tien Fong Chee
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
.../arm/mach-socfpga/include/mach/system_manager.h | 122
1 files changed, 122 i
From: Tien Fong Chee
Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang S
From: Tien Fong Chee
Add minimal support for the Arria10 SoCDK.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
board/altera/arria10-socdk/Kconfig | 18 ++
board/altera/arria10-socdk/Makefile
From: Tien Fong Chee
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
include/configs/socfpga_arria10_socdk.h | 94
From: Tien Fong Chee
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
configs/socfpga_arria10_defconfig | 24 +++
From: Tien Fong Chee
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc:
From: Tien Fong Chee
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/Kconfig |4 ++--
arch/arm/mach-socfpga/Kconfig | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
From: Tien Fong Chee
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++
From: Tien Fong Chee
The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/system_m
From: Tien Fong Chee
These functions are already in arch/arm/mach-socfpga/board.c
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
board/altera/arria10-socdk/socfpga.c | 17 -
1 files changed, 0
From: Tien Fong Chee
The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
C
From: Tien Fong Chee
There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arc
From: Tien Fong Chee
Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
On the Arria10 device, the bridges are not mapped through the interconnect.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
drivers/fpga/socfpga.c |2 ++
1 files changed, 2 insertions(+)
From: Tien Fong Chee
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset function to support both GEN5 and
From: Tien Fong Chee
Add base address header file for Stratix10 SoC
Signed-off-by: Chin Liang See
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48
1 files changed, 48 insertion
From: Tien Fong Chee
This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/dts/Makefile |3 +-
arch/arm/dt
From: Tien Fong Chee
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
include/fdtdec.h |8
From: Tien Fong Chee
This patch enables SPL build and implementation for Arria 10.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfi
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_add
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/system_manager.c |4 ++-
drivers/fpga/socfpga.c |7 +++-
include/configs/socfpga_arria10_socdk.h | 56 +++
From: Tien Fong Chee
Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
Cc: Tien Fong
---
arch/arm/mach-socf
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/pinmux.h | 17 +
arch/arm/mach-socfpga/pinmux.c | 104 +++
2 files changed, 121 insertions(+
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
Cc: Tien Fo
From: Tien Fong Chee
This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/spl.c | 79 ++
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
drivers/Makefile |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/
On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add remaining 3 I2C base addresses for the Arria10.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Reviewed-by: Stefan Roese
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
Hi!
I tried to useing falcom mode from nand flash:
ti-u-boot,
am335x based board using modified am335x_evm.
include/configs/am335x_evm.h falcon mode variables untouched.
I ran manually commands presented in:
https://git.ti.com/ti-u-boot/ti-u-boot/blobs/ti-u-boot-2016.05/board/ti/am335x/README
with
2017年1月9日 下午6:30于 Andre Przywara 写道：
>
> Hi,
>
> On 05/01/17 22:55, Icenowy Zheng wrote:
> >
> > 2017年1月6日 06:37于 Maxime Ripard 写道：
> >>
> >> On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote:
> >>> H3-like DRAM controller needs some special code to operate a DDR2 DRAM
> >>> chi
2017年1月9日 下午7:06于 Maxime Ripard 写道：
>
> On Fri, Jan 06, 2017 at 07:13:17AM +0800, Icenowy Zheng wrote:
> >
> >
> > 06.01.2017, 06:16, "Maxime Ripard" :
> > > On Thu, Dec 29, 2016 at 02:50:48AM +0800, Icenowy Zheng wrote:
> > >> Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
EFI loader generates two types of binaries that usually are not a part of
source tree. Ignore them globally based on extension.
Signed-off-by: Andy Shevchenko
---
.gitignore | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.gitignore b/.gitignore
index 7fac5b3c74..b9fa0354dd 100644
--- a/.g
The Sinovoip BPI-M2+ is a SBC board based on the H3 SoC. It has 1G of RAM,
8G eMMC, a microSD slot, USB, gigabit Ethernet, AP6212 WiFi, HDMI, etc.
---
configs/Sinovoip_BPI_M2_plus_defconfig | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 configs/Sinovoip_BPI_M2_plus_
Using \n in a substitution is a GNU extension. Use the 'G" command instead
to insert the desired line.
Signed-off-by: Mark Kettenis
---
scripts/Makefile.lib | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 13c975b8a4..4413e9f9
Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific.
Signed-off-by: Andy Shevchenko
---
arch/x86/include/asm/bootparam.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index a373
Hi,
Le 09/01/2017 à 08:20, Kever Yang a écrit :
On 01/06/2017 06:52 PM, Romain Perier wrote:
Add Rockchip Engineers to Cc:
Le 06/01/2017 à 11:28, Romain Perier a écrit :
Hello,
I have a strange behaviour with the SPL on rk3288.
When I build u-boot-rockchip master for the rock2 (rock2_def
On Thu, Jan 05, 2017 at 03:32:50PM +0100, Jagan Teki wrote:
> Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig
> which is missing in below commit
> "imx: mx6ull_14x14_evk: add plugin defconfig"
> (sha1: b90ebf49bb8f74afe68f696f59a0e24cc79f2031)
>
> Cc: Stefano Babic
> R
On Fri, Jan 06, 2017 at 04:32:12PM -0600, Andrew F. Davis wrote:
> The SPL load address changes based on boot type in HS devices,
> ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
> for similar reasons. Add this same logic for AM33xx devices.
>
> Also make the default value for I
On Fri, Jan 06, 2017 at 04:20:02PM -0600, Andrew F. Davis wrote:
> When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
> not generated but generate an unsigned one anyway, first fix this
> warning to say that it was generated but not secured.
>
> When the user then exports TI_S
On Thu, 5 Jan 2017 16:44:43 -0700
Stephen Warren wrote:
> On 01/03/2017 03:39 AM, Tuomas Tynkkynen wrote:
> > The directory structure of device tree files produced by the kernel's
> > 'make dtbs_install' is different on ARM64, the RPi3 device tree file is
> > in a 'broadcom' subdirectory there. M
(adding Simon and Bin to cc)
On 08.01.2017 21:51, Andy Shevchenko wrote:
Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific.
Signed-off-by: Andy Shevchenko
---
arch/x86/include/asm/bootparam.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/ar
On 01/09/2017 05:31 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add base address header file for Stratix10 SoC
>
> Signed-off-by: Chin Liang See
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/include/mach/base
On a Raspberry Pi 2 disagreements on cell endianness can be observed:
U-Boot> fdt print /soc/gpio@7e20 phandle
phandle = <0x000d>
U-Boot> fdt get value myvar /soc/gpio@7e20 phandle; printenv myvar
myvar=0x0D00
Fix this by always treating the pointer as BE and converting it
On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut wrote:
> On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
>> From: Tien Fong Chee
>>
>> Add remaining 3 I2C base addresses for the Arria10.
>>
>> Signed-off-by: Dinh Nguyen
>> Signed-off-by: Tien Fong Chee
>> Reviewed-by: Stefan Roese
>> Cc: Marek Vasut
On Mon, Jan 09, 2017 at 11:33:28AM +0100, Ladislav Michl wrote:
> Signed-off-by: Ladislav Michl
Applied to u-boot/master, thanks!
--
Tom
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Hey all,
I've released v2017.01 and it's now live on git and FTP and ACD (along
with PGP sig file).
This release I think is a good way to start out a new year. There's the
usual level of forward progress on the things that've been in progress
for a while.
I'll leave pointing out big changes to
From: Adam Ford
On the OMAP36xx (and 37xx) the CONTROL_WKUP_CTRL register has
a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which
are related to the MMC are disabled. After the PBIAS is configured,
this bit should be set high to enable the MMC port.
Signed-off-by: Adam Ford
diff
On 2 January 2017 at 01:40, Michal Simek wrote:
>
> New scan should unbind all block devices not to be listed again.
> Without this patch if scsi reset or scan is called new block devices are
> created which point to the same id and lun.
>
> For example:
> ZynqMP> scsi scan
> scsi_scan: if_type=2,
From: Meng Yi
Unfortunately version 2 of this patch was applied which was missing some
changes. Fix this.
Signed-off-by: Meng Yi
Acked-by: Simon Glass
Signed-off-by: Simon Glass
---
drivers/rtc/Kconfig | 6 +-
drivers/rtc/pcf2127.c | 42 ++
2 f
Hi,
Am 25.11.2016 um 19:56 schrieb Breno Lima:
> diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
> new file mode 100644
> index 000..81e0481
> --- /dev/null
> +++ b/include/configs/udoo_neo.h
[...]
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "console=ttymxc0,115200\0" \
On 17 November 2016 at 02:08, Mugunthan V N wrote:
> Add usb ether gadget device with usb_ether_init() when
> CONFIG_DM_ETH and CONFIG_USB_ETHER are defined.
>
> Signed-off-by: Mugunthan V N
> Reviewed-by: Tom Rini
> ---
> arch/arm/cpu/armv7/am33xx/board.c | 8
> 1 file changed, 8 inse
On 17 November 2016 at 02:08, Mugunthan V N wrote:
> Since usb ether gadget have support for driver model, so enable
> usb ether gadget.
>
> Signed-off-by: Mugunthan V N
> Reviewed-by: Tom Rini
> ---
> include/configs/am335x_evm.h | 3 ---
> 1 file changed, 3 deletions(-)
Applied to u-boot-dm,
On 9 January 2017 at 11:13, Simon Glass wrote:
> On 2 January 2017 at 01:40, Michal Simek wrote:
>>
>> New scan should unbind all block devices not to be listed again.
>> Without this patch if scsi reset or scan is called new block devices are
>> created which point to the same id and lun.
>>
>>
On 21 November 2016 at 07:06, Tom Rini wrote:
> On Thu, Nov 17, 2016 at 02:38:15PM +0530, Mugunthan V N wrote:
>
>> enable usb driver model for am335x bbb as musb supports
>> driver model
>>
>> Signed-off-by: Mugunthan V N
>
> Reviewed-by: Tom Rini
Applied to u-boot-dm, thanks!
Hi Tom,
The following changes since commit a705ebc81b7f91bbd0ef7c634284208342901149:
Prepare v2017.01 (2017-01-09 11:57:05 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-dm.git
for you to fetch changes up to f8f41ae668040d58271e03bc85b58e13becb14af:
scsi: dm: Un
On 01/09/2017 09:45 PM, Simon Glass wrote:
> On 17 November 2016 at 02:08, Mugunthan V N wrote:
>> Since usb ether gadget have support for driver model, so enable
>> usb ether gadget.
>>
>> Signed-off-by: Mugunthan V N
>> Reviewed-by: Tom Rini
>> ---
>> include/configs/am335x_evm.h | 3 ---
>>
On Mon, Jan 09, 2017 at 09:58:03PM +0100, Marek Vasut wrote:
> On 01/09/2017 09:45 PM, Simon Glass wrote:
> > On 17 November 2016 at 02:08, Mugunthan V N wrote:
> >> Since usb ether gadget have support for driver model, so enable
> >> usb ether gadget.
> >>
> >> Signed-off-by: Mugunthan V N
> >>
Hi Tom or Any,
Any idea how to trigger travis-ci with multiple commit (build all of
them) at same push, say for example when I push 10 commits in one push
and if the middle commit is an error commit but travis-ci doesn't show
the build issue. Do I need to do any specific setting on travis-ci
linke
On Tue, Jan 10, 2017 at 12:34:47AM +0100, Jagan Teki wrote:
> Hi Tom or Any,
>
> Any idea how to trigger travis-ci with multiple commit (build all of
> them) at same push, say for example when I push 10 commits in one push
> and if the middle commit is an error commit but travis-ci doesn't show
>
The file arch/arm/include/asm/mach-types.h comes from the Linux kernel
and contains a number of CONFIG_ symbols that we have no control over
nor do we wish to do anything with. Ignore that file and re-generate
the whitelist.
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
scripts/build-whiteli
Hi Tom,
2017-01-10 9:46 GMT+09:00 Tom Rini :
> The file arch/arm/include/asm/mach-types.h comes from the Linux kernel
> and contains a number of CONFIG_ symbols that we have no control over
> nor do we wish to do anything with. Ignore that file and re-generate
> the whitelist.
>
> Cc: Masahiro Y
Hi Jagan,
On 01/01/2017 09:11 PM, Masahiro Yamada wrote:
> The bare default entry is wrong. Just remove it since the (real)
> entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".
Do you have any opinion about this patch?
I want to know your ack or review.
If there is no objection,
On Tue, Jan 10, 2017 at 09:50:42AM +0900, Masahiro Yamada wrote:
> Hi Tom,
>
>
> 2017-01-10 9:46 GMT+09:00 Tom Rini :
> > The file arch/arm/include/asm/mach-types.h comes from the Linux kernel
> > and contains a number of CONFIG_ symbols that we have no control over
> > nor do we wish to do anyth
On Mon, Jan 09, 2017 at 07:59:29PM -0500, Tom Rini wrote:
> On Tue, Jan 10, 2017 at 09:50:42AM +0900, Masahiro Yamada wrote:
> > Hi Tom,
> >
> >
> > 2017-01-10 9:46 GMT+09:00 Tom Rini :
> > > The file arch/arm/include/asm/mach-types.h comes from the Linux kernel
> > > and contains a number of CON
Hi Jaehoon,
2017-01-10 9:55 GMT+09:00 Jaehoon Chung :
> Hi Jagan,
>
> On 01/01/2017 09:11 PM, Masahiro Yamada wrote:
>> The bare default entry is wrong. Just remove it since the (real)
>> entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".
>
> Do you have any opinion about this pat
Hi Masahiro,
On 01/10/2017 10:32 AM, Masahiro Yamada wrote:
> Hi Jaehoon,
>
>
> 2017-01-10 9:55 GMT+09:00 Jaehoon Chung :
>> Hi Jagan,
>>
>> On 01/01/2017 09:11 PM, Masahiro Yamada wrote:
>>> The bare default entry is wrong. Just remove it since the (real)
>>> entry in drivers/mmc/Kconfig has "
---
Changes in v2: None
Changes in v1:
- Merge together all patches related to ast2500 boards common
functions/configs
- Add copyright statement to ast2500-board.c
Signed-off-by: Maxim Sloyko
---
arch/arm/mach-aspeed/Makefile| 2 +-
arch/arm/mach-aspeed/ast2500-board.c | 78 +
Add support for Watchdog Timer, which is compatible with AST2400 and
AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver
does not follow the driver model. It also uses fixed clock, so no clock
driver is needed.
Add support for timer for Aspeed ast2400/ast2500 devices.
The driver
On 01/09/2017 06:34 AM, Tuomas Tynkkynen wrote:
On Thu, 5 Jan 2017 16:44:43 -0700
Stephen Warren wrote:
On 01/03/2017 03:39 AM, Tuomas Tynkkynen wrote:
The directory structure of device tree files produced by the kernel's
'make dtbs_install' is different on ARM64, the RPi3 device tree file is
On Isn, 2017-01-09 at 10:54 -0600, Dinh Nguyen wrote:
> On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut wrote:
> >
> > On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> > >
> > > From: Tien Fong Chee
> > >
> > > Add remaining 3 I2C base addresses for the Arria10.
> > >
> > > Signed-off-by: Dinh Ngu
Hi Andreas,
There are several patches I sent two months ago using the your older mail
address,
I am not sure if you received them successfully. If not, I will resent them.
Sorry for the inconvenience caused.
Best Regards,
Wenyou Yang
> -Original Message-
> From: Wenyou Yang [mailto:we
On Isn, 2017-01-09 at 13:43 +0100, Marek Vasut wrote:
> On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee
> >
> > Add remaining 3 I2C base addresses for the Arria10.
> >
> > Signed-off-by: Dinh Nguyen
> > Signed-off-by: Tien Fong Chee
> > Reviewed-by: Stefan Roese
>
On Isn, 2017-01-09 at 08:47 -0600, Dinh Nguyen wrote:
>
> On 01/09/2017 05:31 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee
> >
> > Add base address header file for Stratix10 SoC
> >
> > Signed-off-by: Chin Liang See
> > Signed-off-by: Tien Fong Chee
> > Cc: Marek Vasut
> > Cc: Din
Guys,
U-Boot 2017.01 has been released. The merge window is open. If you need
to update your patches, please do so ASAP. I will start to test and
merge existing patches soon.
York
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailm
Sorry for spamming the list. I meant to sent to our internal teams. My
apologies.
On 01/09/2017 08:02 PM, york sun wrote:
> Guys,
>
> U-Boot 2017.01 has been released. The merge window is open. If you need
> to update your patches, please do so ASAP. I will start to test and
> merge existing patc
Move (and rename) the following CONFIG options to Kconfig:
CONFIG_EXYNOS_DWMMC (renamed to CONFIG_MMC_DW_EXYNOS)
CONFIG_HIKEY_DWMMC (renamed to CONFIG_MMC_DW_K3)
CONFIG_SOCFPGA_DWMMC (renamed to CONFIG_MMC_DW_SOCFPGA)
The "HIKEY" is a board name, so it is not suitable for the MMC
control
I am trying to make all DesignWare-based driver options prefixed
with CONFIG_MMC_DW_.
This commit was generated as follows:
find . -name .git -prune -o -type f -print | \
xargs sed -i -e 's/ROCKCHIP_DWMMC/MMC_DW_ROCKCHIP/g'
Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
---
Changes i
Move (and rename) the following CONFIG options to Kconfig:
CONFIG_DAVINCI_MMC (renamed to CONFIG_MMC_DAVINCI)
CONFIG_OMAP_HSMMC (renamed to CONFIG_MMC_OMAP_HS)
CONFIG_MXC_MMC (renamed to CONFIG_MMC_MXC)
CONFIG_MXS_MMC (renamed to CONFIG_MMC_MXS)
CONFIG_TEGRA_MMC(renamed
The bare default entry is wrong. Just remove it since the (real)
entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX".
Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
---
Changes in v2: None
board/sunxi/Kconfig | 4
1 file changed, 4 deletions(-)
diff --git a/board/
This series is based on commit 3d3a74cc8c.
Each git-log describes how to re-generate it.
Buildman test passed.
Changes in v2:
- Re-generate based on v2017.01
Masahiro Yamada (7):
ARM: socfpga: remove unused CONFIG option and cleanup README.socfpga
mmc: rename CONFIG_ROCKCHIP_DWMMC to CONFI
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