[U-Boot] Please pull u-boot-marvell/master

[Stefan Roese]

Hi Tom,

please pull the following Marvell patches mainly adding
support for some new boards, like the ARMv8 community
boards MACCHIATOBin and ESPRESSBin.

Thanks,
Stefan

The following changes since commit 5877d8f398de26617be6f1f57bc30c49e9f90ebb:

  Merge branch 'master' of git://git.denx.de/u-boot-mmc (2017-03-21 14:10:15 
-0400)

are available in the git repository at:

  git://www.denx.de/git/u-boot-marvell.git 

for you to fetch changes up to 60083261a1b33b492ddb5335c125f1223087068b:

  arm: mvebu: Add gdsys ControlCenter-Compact board (2017-03-23 15:48:28 +0100)


Dirk Eibach (1):
  arm: mvebu: Add gdsys ControlCenter-Compact board

Konstantin Porotchkin (17):
  arm64: mvebu: gpio: Add GPIO nodes to A8K family devices
  arm64: mvebu: dts: Add i2c1 pin definitions to CPM
  mvebu: pcie: Add support for GPIO reset for PCIe device
  arm64: mvebu: Add default configuraton for MACCHIATOBin board
  mvebu: usb: xhci: Add VBUS regulator supply to the host driver
  arm64: mvebu: Rename the db-88f3720 to armada-37xx platform
  arm64: a37xx: Enable Marvell ETH PHY support
  arm64: a37xx: Enable bubt command support on A3720-DB
  arm64: a37xx: dts: Add pin control nodes to DT
  arm64: a37xx: Handle pin controls in early board init
  mvebu: neta: Add support for board init function
  mvebu: neta: a37xx: Add fixed link support to neta driver
  mvebu: a37xx: Add init for ESPRESSBin Topaz switch
  arm64: dts: Add device tree for ESPRESSOBin board
  arm64: mvebu: Add default config for ESPRESSOBin board
  arm64: a37xx: Disable DB configurations on ESPRESSOBin board
  arm64: a37xx: Remove DM_I2C_COMPAT from the board config

Rabeeh Khoury (1):
  arm64: mvebu: dts: Add DTS file for MACCHIATOBin board

Stefan Roese (3):
  arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width
  arm: mvebu: theadorable: Add board-specific PEX detection pulse width
  arm: mvebu: theadorable: Add 'pcie' test command

mario@gdsys.cc (1):
  dm: Add callback to modify the device tree

 arch/arm/Kconfig   |   1 +
 arch/arm/dts/Makefile  |   5 +-
 arch/arm/dts/armada-3720-espressobin.dts   | 135 +
 arch/arm/dts/armada-37xx.dtsi  |  14 +
 arch/arm/dts/armada-38x-controlcenterdc.dts| 589 +
 arch/arm/dts/armada-7040.dtsi  |   1 +
 arch/arm/dts/armada-8040-mcbin.dts | 293 ++
 arch/arm/dts/armada-8040.dtsi  |   1 +
 arch/arm/dts/armada-ap806.dtsi |   8 +
 arch/arm/dts/armada-cp110-master.dtsi  |  22 +
 arch/arm/dts/armada-cp110-slave.dtsi   |  18 +
 arch/arm/mach-mvebu/Kconfig|  14 +-
 .../arm/mach-mvebu/serdes/axp/high_speed_env_lib.c |  31 ++
 .../MAINTAINERS|   4 +-
 .../Makefile   |   0
 board/Marvell/mvebu_armada-37xx/board.c| 258 +
 board/Marvell/mvebu_db-88f3720/board.c | 134 -
 board/gdsys/a38x/.gitignore|   1 +
 board/gdsys/a38x/Kconfig   |  36 ++
 board/gdsys/a38x/MAINTAINERS   |   7 +
 board/gdsys/a38x/Makefile  |  44 ++
 board/gdsys/a38x/controlcenterdc.c | 279 ++
 board/gdsys/a38x/dt_helpers.c  |  43 ++
 board/gdsys/a38x/dt_helpers.h  |  16 +
 board/gdsys/a38x/hre.c | 516 ++
 board/gdsys/a38x/hre.h |  38 ++
 board/gdsys/a38x/hydra.c   | 138 +
 board/gdsys/a38x/hydra.h   |  14 +
 board/gdsys/a38x/ihs_phys.c| 355 +
 board/gdsys/a38x/ihs_phys.h|   2 +
 board/gdsys/a38x/keyprogram.c  | 158 ++
 board/gdsys/a38x/keyprogram.h  |  14 +
 board/gdsys/a38x/kwbimage.cfg.in   |  12 +
 board/gdsys/a38x/spl.c |  21 +
 board/theadorable/theadorable.c|  48 ++
 common/board_f.c   |  10 +
 configs/controlcenterdc_defconfig  |  58 ++
 configs/mvebu_db-88f3720_defconfig |   6 +-
 configs/mvebu_espressobin-88f3720_defconfig|  66 +++
 configs/mvebu_mcbin-88f8040_defconfig  |  74 +++
 doc/device-tree-bindings/pci/armada8k-pcie.txt |  49 ++
 doc/device-tree-bindings/usb/marvell.xhci-usb.txt  |  28 +
 doc/driver-model/fdt-fixup.txt | 132 +
 drivers/net/mvneta.c   | 125 -
 drivers/pci/pcie_dw_mvebu.c|  20 +
 drivers/usb/host/Kconfig 

Re: [U-Boot] [PATCH 2/3 v3] arm: mvebu: Add gdsys ControlCenter-Compact board

[Stefan Roese]

On 22.02.2017 16:07, Mario Six wrote:

From: Dirk Eibach 

The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.

It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.

On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM

Signed-off-by: Dirk Eibach 
Signed-off-by: Mario Six 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 1/3 v3] dm: Add callback to modify the device tree

[Stefan Roese]

On 22.02.2017 16:07, Mario Six wrote:

Certain boards come in different variations by way of utilizing daughter
boards, for example. These boards might contain additional chips, which
are added to the main board's busses, e.g. I2C.

The device tree support for such boards would either, quite naturally,
employ the overlay mechanism to add such chips to the tree, or would use
one large default device tree, and delete the devices that are actually
not present.

Regardless of approach, even on the U-Boot level, a modification of the
device tree is a prerequisite to have such modular families of boards
supported properly.

Therefore, we add an option to make the U-Boot device tree (the actual
copy later used by the driver model) writeable, and add a callback
method that allows boards to modify the device tree at an early stage,
at which, hopefully, also the application of device tree overlays will
be possible.

Signed-off-by: Mario Six 


Applied to u-boot-marvell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH v3 1/6] arm64: mvebu: gpio: Add GPIO nodes to A8K family devices

[Stefan Roese]

On 08.02.2017 16:34, kos...@marvell.com wrote:

From: Konstantin Porotchkin 

Add GPIO nodes to AP-806 and CP-110-master DTSI files.

Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c
Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Nadav Haklai 
Cc: Igal Liberman 
Cc: Haim Boot 


Complete series applied to u-boot-mavell/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH v2 01/12] arm64: mvebu: Rename the db-88f3720 to armada-37xx platform

[Stefan Roese]

On 16.02.2017 12:52, kos...@marvell.com wrote:

From: Konstantin Porotchkin 

Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.

Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Igal Liberman 
Cc: Nadav Haklai 


Complete series applied to u-boot-mavell/master.

Thanks,
Stefan
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Re: [U-Boot] [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node

[Ken Ma]

+ Hua, Wilson

From: Ken Ma
Sent: 2017年3月24日 11:04
To: 'Stefan Roese'; u-boot@lists.denx.de
Cc: Simon Glass; Michal Simek; Kostya Porotchkin
Subject: RE: [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node


Hi Stefan



Thanks a lot for your kind advice and help!

Please see my reply inline.



Yours,

Ken



-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: 2017年3月23日 22:06
To: Ken Ma; u-boot@lists.denx.de
Cc: Simon Glass; Michal Simek
Subject: [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node



External Email



--

Hi Ken,



On 23.03.2017 10:29, m...@marvell.com wrote:

> From: Ken Ma >

>

> - Add scsi node which acts as a bus for scsi devices, armada3700 has

>   only 1 scsi interface, so max-id is 1, and the logic unit number is

>   also 1 for armada3700;

> - Since a3700's scsi is sas(serial attached scsi) which is compatible

>   for sata and sata hard disk is a sas device, so move sata node to be

>   under scsi node.

>

> Signed-off-by: Ken Ma >

> Cc: Simon Glass >

> Cc: Stefan Roese >

> Cc: Michal Simek >

> Reviewed-on: http://vgitil04.il.marvell.com:8080/35303

> Tested-by: iSoC Platform CI >

> Reviewed-by: Kostya Porotchkin >

> Reviewed-by: Omri Itach >

> ---

>  arch/arm/dts/armada-3720-db.dts |  4 

>  arch/arm/dts/armada-37xx.dtsi   | 16 

>  2 files changed, 16 insertions(+), 4 deletions(-)

>

> diff --git a/arch/arm/dts/armada-3720-db.dts

> b/arch/arm/dts/armada-3720-db.dts index 85761af..9fc60f6 100644

> --- a/arch/arm/dts/armada-3720-db.dts

> +++ b/arch/arm/dts/armada-3720-db.dts

> @@ -89,6 +89,10 @@

> status = "okay";

>  };

>

> + {

> +   status = "okay";

> +};

> +

>  /* CON3 */

>   {

> status = "okay";

> diff --git a/arch/arm/dts/armada-37xx.dtsi

> b/arch/arm/dts/armada-37xx.dtsi index 062f2a6..de5d3a1 100644

> --- a/arch/arm/dts/armada-37xx.dtsi

> +++ b/arch/arm/dts/armada-37xx.dtsi

> @@ -149,11 +149,19 @@

>   status = "disabled";

> };

>

> -   sata: sata@e {

> - compatible = "marvell,armada-3700-ahci";

> - reg = <0xe 0x2000>;

> - interrupts = ;

> +   scsi: scsi {

> + compatible = "marvell,mvebu-scsi";

> + #address-cells = <1>;

> + #size-cells = <1>;

> + max-id = <1>;

> + max-lun = <1>;

>   status = "disabled";

> + sata: sata@e {

> +   compatible = "marvell,armada-3700-ahci";

> +   reg = <0xe 0x2000>;

> +   interrupts = ;

> +   status = "disabled";

> + };

> };

>

> gic: interrupt-controller@1d0 {

>



I see that you introduce a "scsi" DT node and move the SATA controller one 
"level up". I'm not sure if such a change is acceptable as we try to re-use the 
DT from Linux. Or thinking more about this, I'm pretty sure that such a change 
is not acceptable in general.



Can't you use the existing DT layout and use the "marvell,armada-3700-ahci" 
(and other perhaps?) compatible property instead for driver probing? Not sure 
how to handle the "max-id" and "max-lun" properties though. We definitely can't 
just add some ad-hoc properties here in U-Boot which have no chance for Linux 
upstream acceptance.



[Ken] Because scsi is a bus, for example, if there are 2 scsi buses, each bus 
has some scsi device controllers connected as below.



Scsi ID 0 Scsi ID 1 Scsi ID 2 Scsi ID 3



HDD0  HDD1   tape0  cd-rom0

||||||||

===

SCSI BUS1



HDD2  HDD3   tape1  cd-rom2

||||||||

===

SCSI BUS2





Then in my opinion, since now scsi has its own class id and its compatible 
string, then the scsi device controllers dts node should be above the scsi node.

If we keep existing DT layout and keep "marvell,armada-3700-ahci"’s uclass id 
as UCLASS_AHCI(there are no scsi nodes but only ahci nodes), then scsi_scan() 
can not find a3700’s sata at 

[U-Boot] [PATCH v2 3/4] ARM: spl: atmel: move mem_init() advance in SPL init.

[Wenyou Yang]

Because the MMC SPL puts the bbs section in the ddr memory, move
calling mem_init() before calling spl_init().

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 arch/arm/mach-at91/spl_atmel.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 847a30b9a9..b75c2ccefd 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -101,6 +101,8 @@ void board_init_f(ulong dummy)
 
board_early_init_f();
 
+   mem_init();
+
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
@@ -109,5 +111,4 @@ void board_init_f(ulong dummy)
 
preloader_console_init();
 
-   mem_init();
 }
-- 
2.11.0

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[U-Boot] [PATCH v2 4/4] ARM: at91: lds: use "_image_binary_end" for DT location

[Wenyou Yang]

The MMC SPL locates the BSS section to a different memory region
from text, then use "_image_binary_end" variable to point to the
correct device tree location.

Signed-off-by: Wenyou Yang 
---

Changes in v2:
 - Drop [PATCH] ARM: at91: lds: add test SPL binary size and bbs size.

 arch/arm/mach-at91/armv7/u-boot-spl.lds | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds 
b/arch/arm/mach-at91/armv7/u-boot-spl.lds
index c667cb..d2e41a026c 100644
--- a/arch/arm/mach-at91/armv7/u-boot-spl.lds
+++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds
@@ -47,6 +47,8 @@ SECTIONS
*(.__end)
} >.sram
 
+   _image_binary_end = .;
+
.bss :
{
. = ALIGN(4);
-- 
2.11.0

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[U-Boot] [PATCH v2 2/4] ARM: spl: atmel: bring in serial device before init

[Wenyou Yang]

Before setting up the serial communications, bring in the serial
device from the device tree file.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 arch/arm/mach-at91/spl_atmel.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 688289e7cf..847a30b9a9 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -77,6 +77,8 @@ void s_init(void)
 
 void board_init_f(ulong dummy)
 {
+   int ret;
+
switch_to_main_crystal_osc();
 
 #ifdef CONFIG_SAMA5D2
@@ -99,6 +101,12 @@ void board_init_f(ulong dummy)
 
board_early_init_f();
 
+   ret = spl_init();
+   if (ret) {
+   debug("spl_init() failed: %d\n", ret);
+   hang();
+   }
+
preloader_console_init();
 
mem_init();
-- 
2.11.0

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[U-Boot] [PATCH v2 1/4] ARM: at91: spl: specify MMC and NAND boot device

[Wenyou Yang]

When OF_CONTROL is enabled, MMC boot device should not be detected
automatically, it should be MMC1 fixedly only the status "enabled"
is available.

Add NAND Flash boot device as well.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 arch/arm/mach-at91/spl.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index 98f280cbf7..e113336b7b 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -39,12 +39,16 @@ u32 spl_boot_device(void)
 
 #if defined(CONFIG_SYS_USE_MMC)
if (dev == ATMEL_SAMA5_BOOT_FROM_MCI) {
+#if defined(CONFIG_SPL_OF_CONTROL)
+   return BOOT_DEVICE_MMC1;
+#else
if (off == 0)
return BOOT_DEVICE_MMC1;
if (off == 1)
return BOOT_DEVICE_MMC2;
printf("ERROR: MMC controller %i not present!\n", dev);
hang();
+#endif
}
 #endif
 
@@ -53,6 +57,9 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_SPI;
 #endif
 
+   if (dev == ATMEL_SAMA5_BOOT_FROM_SMC)
+   return BOOT_DEVICE_NAND;
+
if (dev == ATMEL_SAMA5_BOOT_FROM_SAMBA)
return BOOT_DEVICE_USB;
 
-- 
2.11.0

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[U-Boot] [PATCH v2 0/4] ARM: SPL: at91: update to support DM/DT

[Wenyou Yang]

To support the driver model and device tree in SPL, fix the boot
device, bring in the serial device from device tree, and use
"_image_binary_end" variable to point to the correct device tree
location when CONFIG_SPL_SEPARATE_BSS is enabled.

Changes in v2:
 - Drop [PATCH] ARM: at91: lds: add test SPL binary size and bbs size.

Wenyou Yang (4):
  ARM: at91: spl: specify MMC and NAND boot device
  ARM: spl: atmel: bring in serial device before init
  ARM: spl: atmel: move mem_init() advance in SPL init.
  ARM: at91: lds: use "_image_binary_end" for DT location

 arch/arm/mach-at91/armv7/u-boot-spl.lds |  2 ++
 arch/arm/mach-at91/spl.c|  7 +++
 arch/arm/mach-at91/spl_atmel.c  | 11 ++-
 3 files changed, 19 insertions(+), 1 deletion(-)

-- 
2.11.0

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Re: [U-Boot] [PATCH] rockchip: spl: RK3399: add COUNTER_FREQUENCY define to rk3399_common.h

[Kever Yang]

Hi Philipp,

On 03/24/2017 06:27 AM, Philipp Tomsich wrote:

The BootROM of the RK3399 SoC does not initialise the cntfrq_el0 (which
holds the value 0 (zero) on entry into the SPL. This causes the timebase
for U-Boot not to advance (and will cause a hang where a timeout would
be expected... e.g. if something goes wrong during MMC/SD card startup).

This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0 (if necessary).

Signed-off-by: Philipp Tomsich 
---

  include/configs/rk3399_common.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index aeee805..c44f8ad 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -19,6 +19,8 @@
  #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  #define CONFIG_SPL_SERIAL_SUPPORT
  
+#define COUNTER_FREQUENCY   2400

+
  #define CONFIG_SYS_NS16550_MEM32
  
  #define CONFIG_SYS_TEXT_BASE		0x0020


Reveiwed-by: Kever Yang 

Thanks,
- Kever

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Re: [U-Boot] [PATCH 5/8] rockchip: rk3188: Setup the armclk in spl

[Simon Glass]

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot
> startup taking a lot of time (U-Boot itself, but also the rc4 decoding done
> in the bootrom).
>
> With default pmic settings we can always reach a safe frequency of 600MHz
> which is also the frequency the proprietary loader left the armclk at,
> without needing access to the systems pmic.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  arch/arm/mach-rockchip/rk3188-board-spl.c | 24 
>  1 file changed, 24 insertions(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 0/8] rockchip: rk3188: fixups and armclk speedup

[Simon Glass]

Hi Heiko,

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup
> unnecessary slow. We can easily switch to 600MHz without involving
> the pmic and thus do this in the SPL to also make the rc4-decoding
> of the U-Boot image faster.
>
> Some smaller fixes also turned up while adding the ARMCLK-support.
>
> It's currently based on Simon's spl-working branch and Kever's
> spl_early_init patch, as that includes the last missing rk3188
> patches and also keeps uboot starting on rk3188.

This should be in mainline now so can you also please test against that?

>
> Tested on a rk3188 radxarock.
>
>
> Heiko Stuebner (8):
>   rockchip: rk3188: sdram: Set correct sdram base
>   rockchip: rk3188: Decode the actual amount of ram
>   rockchip: rk3188: Cleanup some SPL/TPL rename leftovers
>   rockchip: clk: rk3188: Allow configuration of the armclk
>   rockchip: rk3188: Setup the armclk in spl
>   rockchip: rk3188: Switch to new i2c IP blocks
>   rockchip: i2c: Add compatibles for Rockchip Cortex-A9 socs
>   rockchip: Enable pmic options and act8846 driver on rk3188 rock boards
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3188.h |  1 +
>  arch/arm/mach-rockchip/rk3188-board-spl.c   | 45 ++
>  arch/arm/mach-rockchip/rk3188-board-tpl.c   |  6 +--
>  arch/arm/mach-rockchip/rk3188-board.c   | 18 ++-
>  arch/arm/mach-rockchip/rk3188/sdram_rk3188.c|  2 +-
>  configs/rock_defconfig  |  4 ++
>  drivers/clk/rockchip/clk_rk3188.c   | 63 
> +
>  drivers/i2c/rk_i2c.c|  2 +
>  8 files changed, 135 insertions(+), 6 deletions(-)
>
> --
> 2.11.0
>

Regards,
Simon
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Re: [U-Boot] [PATCH 7/8] rockchip: i2c: Add compatibles for Rockchip Cortex-A9 socs

[Simon Glass]

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> The Cortex-A9 socs rk3066 and rk3188 share the IP but have their own
> compatible values, so add them to make the i2c on these platforms accessible.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  drivers/i2c/rk_i2c.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 4/8] rockchip: clk: rk3188: Allow configuration of the armclk

[Simon Glass]

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
> startup take a lot of time. We therefore want to at least move to the safe
> 600MHz value we can use with default pmic settings.
> This is also the freqency the proprietary sdram-init leaves the cpu at.
>
> For boards that have pmic control later in u-boot, we also add the option
> to set the maximum frequency of 1.6GHz, if they so desire.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  arch/arm/include/asm/arch-rockchip/cru_rk3188.h |  1 +
>  drivers/clk/rockchip/clk_rk3188.c   | 63 
> +
>  2 files changed, 64 insertions(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 6/8] rockchip: rk3188: Switch to new i2c IP blocks

[Simon Glass]

Hi Heiko,

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> The rk3066/rk3188 introduced new i2c IP blocks but kept the old ones
> around just in case. The default also points to these old controllers.
>
> The "new" blocks proved stable and nobody ever used the old ones anywhere,
> not in the kernel and not in U-Boot, so to be able to reuse the already
> existing driver make the rk3188 switch to the new ones in U-Boot as well.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  arch/arm/mach-rockchip/rk3188-board-spl.c | 21 +
>  1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c 
> b/arch/arm/mach-rockchip/rk3188-board-spl.c
> index affd959f86..14847a7b1b 100644
> --- a/arch/arm/mach-rockchip/rk3188-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
> @@ -17,6 +17,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -102,6 +103,7 @@ void board_init_f(ulong dummy)
>  {
> struct udevice *pinctrl, *dev;
> struct rk3188_pmu *pmu;
> +   struct rk3188_grf *grf;
> int ret;
>
> /* Example code showing how to enable the debug UART on RK3188 */
> @@ -154,6 +156,25 @@ void board_init_f(ulong dummy)
> error("pmu syscon returned %ld\n", PTR_ERR(pmu));
> SAVE_SP_ADDR = readl(>sys_reg[2]);
>
> +   /* init common grf settings */
> +   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +   if (IS_ERR(grf)) {
> +   error("grf syscon returned %ld\n", PTR_ERR(grf));
> +   } else {
> +   /* make i2c controllers use the new IP */
> +   rk_clrsetreg(>soc_con1,
> +   RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |
> +   RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |
> +   RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |
> +   RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |
> +   RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT,
> +   RKI2C4_SEL_MASK << RKI2C4_SEL_SHIFT |
> +   RKI2C3_SEL_MASK << RKI2C3_SEL_SHIFT |
> +   RKI2C2_SEL_MASK << RKI2C2_SEL_SHIFT |
> +   RKI2C1_SEL_MASK << RKI2C1_SEL_SHIFT |
> +   RKI2C0_SEL_MASK << RKI2C0_SEL_SHIFT);
> +   }

Can you move this to the pinctrl driver?

> +
> ret = uclass_get_device(UCLASS_PINCTRL, 0, );
> if (ret) {
> debug("Pinctrl init failed: %d\n", ret);
> --
> 2.11.0
>

Regards,
Simon
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Re: [U-Boot] [PATCH 8/8] rockchip: Enable pmic options and act8846 driver on rk3188 rock boards

[Simon Glass]

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> The rock board uses the already existing act8846 as pmic, so enable the
> driver and needed pmic options for it.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  configs/rock_defconfig | 4 
>  1 file changed, 4 insertions(+)

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Re: [U-Boot] [PATCH 2/8] rockchip: rk3188: Decode the actual amount of ram

[Simon Glass]

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> There was still a static ram value set in the rk3188-board from the
> time where we didn't have actual sdram init code.
> Now the sdram init leaves the ram information in SYS_REG2 and we can
> decode it similarly to the rk3288.
>
> Right now we have two duplicates of that code, which is still ok and
> doesn't really count as common code yet, but if we get a third copy
> at some point from a newer soc, we should think about moving that to
> a more general position.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  arch/arm/mach-rockchip/rk3188-board.c | 18 --
>  1 file changed, 16 insertions(+), 2 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 3/8] rockchip: rk3188: Cleanup some SPL/TPL rename leftovers

[Simon Glass]

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> In the beginning, we did SPL -> TPL -> U-Boot, but after clarification
> of the real ordering swapped SPL and TPL.
> It seems some renames were forgotten and may confuse future readers, so
> also swap these to reflect the actual ordering.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  arch/arm/mach-rockchip/rk3188-board-tpl.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 1/8] rockchip: rk3188: sdram: Set correct sdram base

[Simon Glass]

On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> Right now we're setting the wrong value of 0 as base in the ram_info struct,
> which is obviously wrong for the rk3188. So instead set the correct value
> we already have in CONFIG_SYS_SDRAM_BASE.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  arch/arm/mach-rockchip/rk3188/sdram_rk3188.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

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Re: [U-Boot] [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node

[Ken Ma]

Hi Stefan



Thanks a lot for your kind advice and help!

Please see my reply inline.



Yours,

Ken



-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: 2017年3月23日 22:06
To: Ken Ma; u-boot@lists.denx.de
Cc: Simon Glass; Michal Simek
Subject: [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node



External Email



--

Hi Ken,



On 23.03.2017 10:29, m...@marvell.com wrote:

> From: Ken Ma >

>

> - Add scsi node which acts as a bus for scsi devices, armada3700 has

>   only 1 scsi interface, so max-id is 1, and the logic unit number is

>   also 1 for armada3700;

> - Since a3700's scsi is sas(serial attached scsi) which is compatible

>   for sata and sata hard disk is a sas device, so move sata node to be

>   under scsi node.

>

> Signed-off-by: Ken Ma >

> Cc: Simon Glass >

> Cc: Stefan Roese >

> Cc: Michal Simek >

> Reviewed-on: http://vgitil04.il.marvell.com:8080/35303

> Tested-by: iSoC Platform CI >

> Reviewed-by: Kostya Porotchkin >

> Reviewed-by: Omri Itach >

> ---

>  arch/arm/dts/armada-3720-db.dts |  4 

>  arch/arm/dts/armada-37xx.dtsi   | 16 

>  2 files changed, 16 insertions(+), 4 deletions(-)

>

> diff --git a/arch/arm/dts/armada-3720-db.dts

> b/arch/arm/dts/armada-3720-db.dts index 85761af..9fc60f6 100644

> --- a/arch/arm/dts/armada-3720-db.dts

> +++ b/arch/arm/dts/armada-3720-db.dts

> @@ -89,6 +89,10 @@

> status = "okay";

>  };

>

> + {

> +   status = "okay";

> +};

> +

>  /* CON3 */

>   {

> status = "okay";

> diff --git a/arch/arm/dts/armada-37xx.dtsi

> b/arch/arm/dts/armada-37xx.dtsi index 062f2a6..de5d3a1 100644

> --- a/arch/arm/dts/armada-37xx.dtsi

> +++ b/arch/arm/dts/armada-37xx.dtsi

> @@ -149,11 +149,19 @@

>   status = "disabled";

> };

>

> -   sata: sata@e {

> - compatible = "marvell,armada-3700-ahci";

> - reg = <0xe 0x2000>;

> - interrupts = ;

> +   scsi: scsi {

> + compatible = "marvell,mvebu-scsi";

> + #address-cells = <1>;

> + #size-cells = <1>;

> + max-id = <1>;

> + max-lun = <1>;

>   status = "disabled";

> + sata: sata@e {

> +   compatible = "marvell,armada-3700-ahci";

> +   reg = <0xe 0x2000>;

> +   interrupts = ;

> +   status = "disabled";

> + };

> };

>

> gic: interrupt-controller@1d0 {

>



I see that you introduce a "scsi" DT node and move the SATA controller one 
"level up". I'm not sure if such a change is acceptable as we try to re-use the 
DT from Linux. Or thinking more about this, I'm pretty sure that such a change 
is not acceptable in general.



Can't you use the existing DT layout and use the "marvell,armada-3700-ahci" 
(and other perhaps?) compatible property instead for driver probing? Not sure 
how to handle the "max-id" and "max-lun" properties though. We definitely can't 
just add some ad-hoc properties here in U-Boot which have no chance for Linux 
upstream acceptance.



[Ken] Because scsi is a bus, for example, if there are 2 scsi buses, each bus 
has some scsi device controllers connected as below.



Scsi ID 0 Scsi ID 1 Scsi ID 2 Scsi ID 3



HDD0  HDD1   tape0  cd-rom0

||||||||

===

SCSI BUS1



HDD2  HDD3   tape1  cd-rom2

||||||||

===

SCSI BUS2





Then in my opinion, since now scsi has its own class id and its compatible 
string, then the scsi device controllers dts node should be above the scsi node.

If we keep existing DT layout and keep "marvell,armada-3700-ahci"’s uclass id 
as UCLASS_AHCI(there are no scsi nodes but only ahci nodes), then scsi_scan() 
can not find a3700’s sata at all since there are no UCLASS_SCSI devices;



If we keep existing DT layout and set scsi devices’ uclass id to be 
UCLASS_SCSI, how can we know that hdd0 and hdd1 are in scsi bus1 but hdd2 and 
hdd3 are in scsi bus2?  For each scsi bus, 

Re: [U-Boot] [PATCH 3/3] rockchip: rk3188: add README.rockchip paragraph describing sd boot

[Kever Yang]

Hi Heiko,

On 03/24/2017 07:41 AM, Heiko Stuebner wrote:

Building sd images for rk3188 requires more steps due to the needed split
into TPL and SPL as loaders. Describe how to build an image for it in a
separate paragraph in the READER.rockchip file.

Signed-off-by: Heiko Stuebner 
---
  doc/README.rockchip | 26 ++
  1 file changed, 26 insertions(+)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index 186a1a007e..cb81efd4bf 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -147,6 +147,32 @@ For evb_rk3036 board:
  Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, 
the
debug uart must be disabled
  
+

+Booting from an SD card on RK3188
+=
+
+For rk3188 boards the general storage onto the card stays the same as
+described above, but the image creation needs a bit more care.
+
+The bootrom of rk3188 expects to find a small 1kb loader which returns
+control to the bootrom, after which it will load the real loader, which
+can then be up to 29kb in size and does the regular ddr init.
+
+Additionally the rk3188 requires everything the bootrom loads to be
+rc4-encrypted. Except for the very first stage the bootrom always reads
+and decodes 2kb pages, so files should be sized accordingly.
+
+# copy tpl, pad to 1020 bytes and append spl
+cat tpl/u-boot-tpl.bin > tplspl.bin
+truncate -s 1020 tplspl.bin
+cat spl/u-boot-spl.bin >> tplspl.bin
+tools/mkimage -n rk3188 -T rksd -d tplspl.bin out
+
+# truncate, encode and append u-boot.bin
+truncate -s %2048 u-boot.bin
+cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 
7C4E0304550509072D2C7B38170D1711' >> out
+
+
  Using fastboot on rk3288
  
  - Write GPT partition layout to mmc device which fastboot want to use it to


Reviewed-by: Kever Yang 

Thanks,
- Kever

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Re: [U-Boot] [PATCH] rockchip: Add support for MiQi rk3288 board

[Kever Yang]

Hi Jernej,

On 03/24/2017 08:11 AM, Jernej Skrabec wrote:

MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.

Signed-off-by: Jernej Skrabec 
---

  arch/arm/dts/Makefile   |   1 +
  arch/arm/dts/rk3288-miqi.dts|  46 
  arch/arm/dts/rk3288-miqi.dtsi   | 459 
  arch/arm/mach-rockchip/rk3288/Kconfig   |  11 +
  board/mqmaker/miqi_rk3288/Kconfig   |  15 ++
  board/mqmaker/miqi_rk3288/MAINTAINERS   |   6 +
  board/mqmaker/miqi_rk3288/Makefile  |   7 +
  board/mqmaker/miqi_rk3288/miqi-rk3288.c |  15 ++
  configs/miqi-rk3288_defconfig   |  73 +
  doc/README.rockchip |   5 +-
  include/configs/miqi_rk3288.h   |  22 ++
  11 files changed, 658 insertions(+), 2 deletions(-)
  create mode 100644 arch/arm/dts/rk3288-miqi.dts
  create mode 100644 arch/arm/dts/rk3288-miqi.dtsi
  create mode 100644 board/mqmaker/miqi_rk3288/Kconfig
  create mode 100644 board/mqmaker/miqi_rk3288/MAINTAINERS
  create mode 100644 board/mqmaker/miqi_rk3288/Makefile
  create mode 100644 board/mqmaker/miqi_rk3288/miqi-rk3288.c
  create mode 100644 configs/miqi-rk3288_defconfig
  create mode 100644 include/configs/miqi_rk3288.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index afeb43ff66..60a9aeb698 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-fennec.dtb \
rk3288-tinker.dtb \
rk3288-popmetal.dtb \
+   rk3288-miqi.dtb \


Should be alphabet order, so before tinker and after fennec.

rk3328-evb.dtb \
rk3399-evb.dtb
  dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts
new file mode 100644
index 00..7b92caf024
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi.dts
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-miqi.dtsi"
+
+/ {
+   model = "mqmaker MiQi";
+   compatible = "mqmaker,miqi", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+};
+
+ {
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
new file mode 100644
index 00..12e584f242
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi.dtsi
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2016 Heiko Stuebner 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ 

Re: [U-Boot] [PATCH v2 2/2] rockchip: config: rk3399: update defconfigs and rk3399_common

[Kever Yang]

Hi Philipp,

On 03/24/2017 06:24 AM, Philipp Tomsich wrote:

With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB and for the RK3399-Q7 can be updated.

Signed-off-by: Philipp Tomsich 

---

Changes in v2: None

  configs/evb-rk3399_defconfig| 2 ++
  configs/puma_defconfig  | 4 +++-
  include/configs/rk3399_common.h | 1 -
  3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 22405ce..7a82869 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -43,7 +43,9 @@ CONFIG_DM_REGULATOR_FIXED=y
  CONFIG_PWM_ROCKCHIP=y
  CONFIG_RAM=y
  CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=150
  CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
  CONFIG_DEBUG_UART_BASE=0xFF1A
  CONFIG_DEBUG_UART_CLOCK=2400
  CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/puma_defconfig b/configs/puma_defconfig
index 515185e..8e29d96 100644
--- a/configs/puma_defconfig
+++ b/configs/puma_defconfig
@@ -43,8 +43,10 @@ CONFIG_DM_REGULATOR_FIXED=y
  CONFIG_PWM_ROCKCHIP=y
  CONFIG_RAM=y
  CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=115200
  CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xFF18
  CONFIG_DEBUG_UART_CLOCK=2400
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_SYS_NS16550=y
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index bc91eb6..c1ea616 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -12,7 +12,6 @@
  #define CONFIG_NR_DRAM_BANKS  1
  #define CONFIG_ENV_SIZE   0x2000
  #define CONFIG_SYS_MAXARGS16
-#define CONFIG_BAUDRATE150
  #define CONFIG_SYS_MALLOC_LEN (32 << 20)
  #define CONFIG_SYS_CBSIZE 1024
  #define CONFIG_SKIP_LOWLEVEL_INIT


Looks good to me.

Reviewed-by: Kever Yang 

Thanks,
- Kever

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Re: [U-Boot] [PATCH v2 1/2] rockchip: rk3399: spl: add UART0 support for SPL

[Kever Yang]

Hi Philipp,

On 03/24/2017 06:24 AM, Philipp Tomsich wrote:

The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).

To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.

As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.

Signed-off-by: Philipp Tomsich 
---

Changes in v2:
- Changed hex constant to lowercase

  arch/arm/include/asm/arch-rockchip/grf_rk3399.h |  8 +++
  arch/arm/mach-rockchip/rk3399-board-spl.c   | 29 ++---
  2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 62d8496..4701cfb 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -333,6 +333,14 @@ enum {
GRF_GPIO2B4_SEL_MASK= 3 << GRF_GPIO2B4_SEL_SHIFT,
GRF_SPI2TPM_CSN0= 1,
  
+	/* GRF_GPIO2C_IOMUX */

+   GRF_GPIO2C0_SEL_SHIFT   = 0,
+   GRF_GPIO2C0_SEL_MASK= 3 << GRF_GPIO2C0_SEL_SHIFT,
+   GRF_UART0BT_SIN = 1,
+   GRF_GPIO2C1_SEL_SHIFT   = 2,
+   GRF_GPIO2C1_SEL_MASK= 3 << GRF_GPIO2C1_SEL_SHIFT,
+   GRF_UART0BT_SOUT= 1,
+
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A4_SEL_SHIFT   = 8,
GRF_GPIO3A4_SEL_MASK= 3 << GRF_GPIO3A4_SEL_SHIFT,
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c 
b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 7b4e0a1..c212143 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -57,19 +57,22 @@ void secure_timer_init(void)
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
  }
  
-#define GRF_EMMCCORE_CON11 0xff77f02c

-void board_init_f(ulong dummy)
+void board_debug_uart_init(void)
  {
-   struct udevice *pinctrl;
-   struct udevice *dev;
-   int ret;
-
-   /* Example code showing how to enable the debug UART on RK3288 */
  #include 
-   /* Enable early UART2 channel C on the RK3399 */
  #define GRF_BASE  0xff77
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff18)

+   /* Enable early UART0 on the RK3399 */
+   rk_clrsetreg(>gpio2c_iomux,
+GRF_GPIO2C0_SEL_MASK,
+GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+   rk_clrsetreg(>gpio2c_iomux,
+GRF_GPIO2C1_SEL_MASK,
+GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#else
+   /* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(>gpio4c_iomux,
 GRF_GPIO4C3_SEL_MASK,
 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
@@ -80,6 +83,16 @@ void board_init_f(ulong dummy)
rk_clrsetreg(>soc_con7,
 GRF_UART_DBG_SEL_MASK,
 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
+
+#define GRF_EMMCCORE_CON11 0xff77f02c
+void board_init_f(ulong dummy)
+{
+   struct udevice *pinctrl;
+   struct udevice *dev;
+   int ret;
+
  #define EARLY_UART
  #ifdef EARLY_UART
/*


Reviewed-by: Kever Yang 

Thanks,
- Kever

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Re: [U-Boot] FIT image for falcon boot

[york sun]

Simon,

I made it work. A patch set will be sent later (much later) after I 
clean up and finish the project on hand.

York

On 03/22/2017 04:40 PM, york@nxp.com wrote:
> Guys,
>
> You were discussing loading FIT image for falcon boot about a year ago.
> I wonder if there is any follow-up on this topic?
>
> York
>

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Re: [U-Boot] [PATCH] ti: clocks: Fix do_enable_clocks() to accept NULL pointers as input parameters

[Lokesh Vutla]

On 3/24/2017 3:54 AM, Lukasz Majewski wrote:
> Up till this commit passing NULL as input parameter was allowed, but not
> handled properly.
> 
> When one passed NULL to one of this function parameters, the code was
> executed causing data abort.
> 
> However, what is more interesting, the abort was not caught because of code
> execution in HYP mode with masked CPSR A bit ("Imprecise Data Abort mask bit).
> The TI's AM57xx SoC switch to HYP mode with A bit masked in lowlevel_init.S
> due to SMC call. Such operation (by default) is performed in SoC ROM code.
> 
> The problem would pop up when one:
> - Switch back to SVC mode after disabling LPAE support
> - Somebody enables A bit (by executing cpsie a asm instruction)
> 
> and then the previously described exception would be caught.
> 
> Signed-off-by: Lukasz Majewski 
> ---
>  arch/arm/cpu/armv7/omap-common/clocks-common.c | 10 ++

This has been moved to arch/arm/mach-omap2/clocks-common.c
Please use the latest U-Boot.

>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c 
> b/arch/arm/cpu/armv7/omap-common/clocks-common.c
> index 097b8e3..157155a 100644
> --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
> +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
> @@ -822,27 +822,29 @@ void do_enable_clocks(u32 const *clk_domains,
>   u32 i, max = 100;
>  
>   /* Put the clock domains in SW_WKUP mode */
> - for (i = 0; (i < max) && clk_domains[i]; i++) {
> + for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {

Instead of checking for clk_domains every time, can we use max as
ARRAY_SIZE(clk_domains)? Similarly other places.

Thanks and regards,
Lokesh

>   enable_clock_domain(clk_domains[i],
>   CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
>   }
>  
>   /* Clock modules that need to be put in HW_AUTO */
> - for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
> + for (i = 0; (i < max) && clk_modules_hw_auto &&
> +  clk_modules_hw_auto[i]; i++) {
>   enable_clock_module(clk_modules_hw_auto[i],
>   MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
>   wait_for_enable);
>   };
>  
>   /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
> - for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
> + for (i = 0; (i < max) && clk_modules_explicit_en &&
> +  clk_modules_explicit_en[i]; i++) {
>   enable_clock_module(clk_modules_explicit_en[i],
>   MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
>   wait_for_enable);
>   };
>  
>   /* Put the clock domains in HW_AUTO mode now */
> - for (i = 0; (i < max) && clk_domains[i]; i++) {
> + for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
>   enable_clock_domain(clk_domains[i],
>   CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
>   }
> 
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[U-Boot] [PATCH v2] ARM: socfpga: add fpga build and bsp handoff instructions to readme

[Stephen Arnold]

This patch adds the steps to manually (re)build a Quartus FPGA project,
generate the required BSP glue, and update u-boot handoff files for
mainline SPL support. Requires Quartus toolchain and current U-Boot.

Signed-off-by: Steve Arnold 
Cc: Dinh Nguyen 
Cc: Stefan Roese 
Cc: Marek Vasut 
---
Changes for v2:
   - Addressed comments by marex
   - Added some clarification
   - Made formatting a bit more rst-ish

 doc/README.socfpga | 141 +++--
 1 file changed, 136 insertions(+), 5 deletions(-)

diff --git a/doc/README.socfpga b/doc/README.socfpga
index cb805cfd3a..cae0ef1a21 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -1,18 +1,149 @@
-
-
+
 SOCFPGA Documentation for U-Boot and SPL
-
+
 
 This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
 based SOCFPGA. To know more about the hardware itself, please refer to
 www.altera.com.
 
 
-
 socfpga_dw_mmc
-
+--
+
 Here are macro and detailed configuration required to enable DesignWare SDMMC
 controller support within SOCFPGA
 
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256
 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
+
+--
+Generating the handoff header files for U-Boot SPL
+--
+
+This text is assuming quartus 16.1, but newer versions will probably work just 
fine too;
+verified with DE1_SOC_Linux_FB demo project 
(https://github.com/VCTLabs/DE1_SOC_Linux_FB).
+Updated/working projects should build using either process below.
+
+Note: it *should* work from Quartus 14.0.200 onwards, however, the current 
vendor demo
+projects must have the IP cores updated as shown below.
+
+Rebuilding your Quartus project
+---
+
+Choose one of the follwing methods, either command line or GUI.
+
+Using the comaand line
+~~
+
+First run the embedded command shell, using your path to the Quartus install:
+
+  $ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh
+
+Then (if necessary) update the IP cores in the project, generate HDL code, and
+build the project:
+
+  $ cd path/to/project/dir
+  $ qsys-generate soc_system.qsys --upgrade-ip-cores
+  $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL]
+  $ quartus_sh --flow compile 
+
+Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit file):
+
+  $ quartus_cpf -c .sof soc_system.rbf
+
+
+Generate BSP handoff files
+~~
+
+You can run the bsp editor GUI below, or run the following command from the
+project directory:
+
+  $ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \
+  --preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \
+  --settings build/settings.bsp
+
+You should use the bsp "build" directory above (ie, where the settings.bsp 
file is)
+in the following u-boot command to update the board headers.  Once these 
headers
+are updated for a given project build, u-boot should be configured for the
+project board (eg, de0-nano-sockit) and then build the normal spl build.
+
+Now you can skip the GUI section.
+
+
+Using the Qsys GUI
+~~
+
+1. Navigate to your project directory
+2. Run Quartus II
+3. Open Project (Ctrl+J), select .qpf
+4. Run QSys [Tools->QSys]
+  4.1 In the Open dialog, select '.qsys'
+  4.2 In the Open System dialog, wait until completion and press 'Close'
+  4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner
+ 4.3.1 In the 'Generation' window, click 'Generate'
+ 4.3.2 In the 'Generate' dialog, wait until completion and click 'Close'
+  4.4 In the QSys window, click 'Finish'
+ 4.4.1 In the 'Quartus II' pop up window, click 'OK'
+5. Back in Quartus II main window, do the following
+  5.1 Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
+  5.2 Use Processing -> Start Compilation (Ctrl+L)
+
+... this may take some time, have patience ...
+
+6. Start the embedded command shell as shown in the previous section
+  6.1 Change directory to 'software/spl_bsp'
+  6.2 Prepare BSP by launching the BSP editor from ECS
+   => bsp-editor
+  6.3 In BSP editor
+  6.3.1 Use File -> Open
+  6.3.2 Select 'settings.bsp' file
+  6.3.3 Click Generate
+  6.3.4 Click Exit
+
+
+Post handoff generation
+~~~
+
+Now that the handoff files are generated, U-Boot can be used to process
+the handoff files generated by the bsp-editor. For this, please use the
+following script from the u-boot source tree:
+
+  $ ./arch/arm/mach-socfpga/qts-filter.sh \
+  

Re: [U-Boot] Please pull u-boot-dm

[Tom Rini]

On Thu, Mar 23, 2017 at 09:41:34AM -0600, Simon Glass wrote:

> Hi Tom,
> 
> Here are the patches that survived testing so far. More to come next week.
> 
> 
> The following changes since commit 5877d8f398de26617be6f1f57bc30c49e9f90ebb:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-mmc (2017-03-21
> 14:10:15 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-dm.git
> 
> for you to fetch changes up to 55bc080e799ac18802a791bd5ce5d83a136da6e3:
> 
>   dtoc: make ScanTree recurse into subnodes (2017-03-22 07:27:19 -0600)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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[U-Boot] [PATCH v2] configs: sama5d3xek: add default config for CMP board

[Wenyou Yang]

The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and
some power rails. The board is mainly used to measure the power
consumption. As all those changes are done in at91bootstrap,
in U-Boot, only use another device tree file, no code needed
to change.

As there is additional power consumption when enbling the USB
Host and USB device, for the power consumption measurement
intention, disable the USB host and device.

Signed-off-by: Wenyou Yang 
---
The patch is based on
[PATCH v4 0/6] board: sama5d3: convert boards to support DM/DT
https://lists.denx.de/pipermail/u-boot/2017-March/284732.html

Changes in v2:
 - Remove the SPL config options.
 - Convert MACB to support driver model.
 - Use CONFIG_DEBUG_UART_CLOCK as the input clock for the early debug UART.

 configs/sama5d36ek_cmp_mmc_defconfig   | 51 ++
 configs/sama5d36ek_cmp_nandflash_defconfig | 51 ++
 configs/sama5d36ek_cmp_spiflash_defconfig  | 51 ++
 3 files changed, 153 insertions(+)
 create mode 100644 configs/sama5d36ek_cmp_mmc_defconfig
 create mode 100644 configs/sama5d36ek_cmp_nandflash_defconfig
 create mode 100644 configs/sama5d36ek_cmp_spiflash_defconfig

diff --git a/configs/sama5d36ek_cmp_mmc_defconfig 
b/configs/sama5d36ek_cmp_mmc_defconfig
new file mode 100644
index 00..32a21f9294
--- /dev/null
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=13200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_LCD=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig 
b/configs/sama5d36ek_cmp_nandflash_defconfig
new file mode 100644
index 00..34c4de17b9
--- /dev/null
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=13200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_LCD=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig 
b/configs/sama5d36ek_cmp_spiflash_defconfig
new file mode 100644
index 00..42c3a1
--- /dev/null
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y

[U-Boot] [PATCH v6 4/4] ARM: dts: at91: add dts file for sama5d4ek

[Wenyou Yang]

Add the device tree file for sama5d4ek board.

The dts file is copied from Linux-4.4, do the following changes.
 - add the "u-boot,dm-pre-reloc" property to determine which nodes
   which are needed by SPL and by the board_init_f stage.
 - fix the compilation warning.

Signed-off-by: Wenyou Yang 
---

Changes in v6: None
Changes in v5:
 - Integrate the dts patches for sama5d3 to one.
 - Add the "u-boot,dm-pre-reloc" property for SPL.
 - Update the commit log.
 - Rebase on v2017.03.

Changes in v4:
 - Rebase on the master branch on git://git.denx.de/u-boot-atmel.git
   commit: 0ff27d4a94637d4b1937c625d33212375bd118d9

Changes in v3:
 - Fix the compatible of spi flash, use "spi-flash".

Changes in v2:
 - Remove unneeded the pinctrl node for cs pin of spi0.

 arch/arm/dts/Makefile   |   3 +
 arch/arm/dts/at91-sama5d4ek.dts | 341 
 2 files changed, 344 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d4ek.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3d661fda69..4b6215aa32 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -339,6 +339,9 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
at91-sama5d3_xplained.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
+   at91-sama5d4ek.dtb
+
 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
at91-sama5d4_xplained.dtb
 
diff --git a/arch/arm/dts/at91-sama5d4ek.dts b/arch/arm/dts/at91-sama5d4ek.dts
new file mode 100644
index 00..b965f5b39d
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d4ek.dts
@@ -0,0 +1,341 @@
+/*
+ * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ *  Copyright (C) 2014 Atmel,
+ *2014 Nicolas Ferre 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+   model = "Atmel SAMA5D4-EK";
+   compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
+
+   aliases {
+   spi0 = 
+   };
+
+   chosen {
+   u-boot,dm-pre-reloc;
+   stdout-path = 
+   };
+
+
+   memory {
+   reg = <0x2000 0x2000>;
+   };
+
+   clocks {
+   slow_xtal {
+   clock-frequency = <32768>;
+   };
+
+   main_xtal {
+   clock-frequency = <1200>;
+   };
+   };
+
+   ahb {
+   apb {
+   adc0: adc@fc034000 {
+   pinctrl-names = "default";
+   pinctrl-0 = <
+   /* external trigger conflicts with 
USBA_VBUS */
+   _adc0_ad0
+   _adc0_ad1
+   _adc0_ad2
+   _adc0_ad3
+   _adc0_ad4
+   >;
+   /* The 

[U-Boot] [PATCH v6 3/4] ARM: dts: at91: add dts files for sama5d4 Xplained

[Wenyou Yang]

Add the device tree files for sama5d4 Xplained board.

The dts files are copied from Linux-4.4, do the following changes.
 - add reg property for pinctrl node.
 - move the gpio nodes(pioA, pioB, pioC ...) from the pinctrl child's
   nodes to its slibling nodes.
 - add the "u-boot,dm-pre-reloc" property to determine which nodes
   which are needed by SPL and by the board_init_f stage.
 - fix the compilation warnings.

Signed-off-by: Wenyou Yang 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
 - Fix the compatible of spi flash, use "spi-flash".

Changes in v2:
 - Remove unneeded the pinctrl node for cs pin of spi0.

 arch/arm/dts/Makefile  |3 +
 arch/arm/dts/at91-sama5d4_xplained.dts |  286 +
 arch/arm/dts/sama5d4.dtsi  | 1935 
 3 files changed, 2224 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d4_xplained.dts
 create mode 100644 arch/arm/dts/sama5d4.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1273767ac0..3d661fda69 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -339,6 +339,9 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
at91-sama5d3_xplained.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
+   at91-sama5d4_xplained.dtb
+
 dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2835-rpi-a-plus.dtb \
bcm2835-rpi-a.dtb \
diff --git a/arch/arm/dts/at91-sama5d4_xplained.dts 
b/arch/arm/dts/at91-sama5d4_xplained.dts
new file mode 100644
index 00..ca6aff28e5
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d4_xplained.dts
@@ -0,0 +1,286 @@
+/*
+ * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
+ *
+ *  Copyright (C) 2015 Atmel,
+ *2015 Josh Wu 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+   model = "Atmel SAMA5D4 Xplained";
+   compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
+
+   aliases {
+   spi0 = 
+   };
+
+   chosen {
+   u-boot,dm-pre-reloc;
+   stdout-path = 
+   };
+
+   memory {
+   reg = <0x2000 0x2000>;
+   };
+
+   clocks {
+   slow_xtal {
+   clock-frequency = <32768>;
+   };
+
+   main_xtal {
+   clock-frequency = <1200>;
+   };
+   };
+
+   ahb {
+   apb {
+   spi0: spi@f801 {
+   u-boot,dm-pre-reloc;
+   cs-gpios = < 3 0>, <0>, <0>, <0>;
+   status = "okay";
+   spi_flash@0 {
+   u-boot,dm-pre-reloc;
+   compatible = "spi-flash";
+   spi-max-frequency = <5000>;
+   reg = <0>;
+ 

[U-Boot] [PATCH v6 2/4] ARM: at91: dt: add dts file for sama5d3 Xplained

[Wenyou Yang]

Add the device tree file for sama5d3 Xplained board.

The dts files are copied from the Linux-4.9, do changes as below.
 - add the "u-boot,dm-pre-reloc" property to determine which nodes
   which are needed by SPL and by the board_init_f stage.
 - fix the compile warning.

Signed-off-by: Wenyou Yang 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/at91-sama5d3_xplained.dts | 348 +
 2 files changed, 351 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index afed460ac9..1273767ac0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -336,6 +336,9 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
sama5d36ek.dtb \
sama5d36ek_cmp.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
+   at91-sama5d3_xplained.dtb
+
 dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2835-rpi-a-plus.dtb \
bcm2835-rpi-a.dtb \
diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts 
b/arch/arm/dts/at91-sama5d3_xplained.dts
new file mode 100644
index 00..69597102fb
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d3_xplained.dts
@@ -0,0 +1,348 @@
+/*
+ * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
+ *
+ *  Copyright (C) 2014 Atmel,
+ *   2014 Nicolas Ferre 
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "sama5d36.dtsi"
+
+/ {
+   model = "SAMA5D3 Xplained";
+   compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
+
+   chosen {
+   u-boot,dm-pre-reloc;
+   stdout-path = 
+   };
+
+   aliases {
+   spi0 = 
+   };
+
+   memory {
+   reg = <0x2000 0x1000>;
+   };
+
+   clocks {
+   slow_xtal {
+   clock-frequency = <32768>;
+   };
+
+   main_xtal {
+   clock-frequency = <1200>;
+   };
+   };
+
+   ahb {
+   apb {
+   mmc0: mmc@f000 {
+   u-boot,dm-pre-reloc;
+   pinctrl-0 = <_mmc0_clk_cmd_dat0 
_mmc0_dat1_3 _mmc0_dat4_7 _mmc0_cd>;
+   vmmc-supply = <_mmc0_reg>;
+   vqmmc-supply = <_3v3_reg>;
+   status = "okay";
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   cd-gpios = < 0 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   mmc1: mmc@f800 {
+   u-boot,dm-pre-reloc;
+   vmmc-supply = <_3v3_reg>;
+   vqmmc-supply = <_3v3_reg>;
+   status = "disabled";
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   cd-gpios = < 1 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   spi0: spi@f0004000 {
+   cs-gpios = < 13 0>, <0>, <0>, < 16 0>;
+   status = "okay";
+   };
+
+   can0: can@f000c000 {
+   status = "okay";
+   };
+
+   i2c0: i2c@f0014000 {
+   pinctrl-0 = <_i2c0_pu>;
+   status = "okay";
+   };
+
+   i2c1: i2c@f0018000 {
+   status = "okay";
+
+   pmic: act8865@5b {
+   compatible = "active-semi,act8865";
+   reg = <0x5b>;
+   status = "disabled";
+
+   regulators {
+   vcc_1v8_reg: DCDC_REG1 {
+   regulator-name = 
"VCC_1V8";
+   regulator-min-microvolt 
= <180>;
+   regulator-max-microvolt 
= <180>;
+   regulator-always-on;
+   };
+
+   vcc_1v2_reg: DCDC_REG2 {
+   regulator-name = 
"VCC_1V2";
+   

[U-Boot] [PATCH v6 1/4] ARM: at91: dt: add dts files for sama5d3xek board

[Wenyou Yang]

Add the device tree files for sama5d3xek board.

The dts files are copied from Linux-4.9, do the changes as below.
 - add reg property for the pinctrl node.
 - move the gpio nodes (pioA, pioB, pioC ...) as the pinctrl's
   slibling nodes.
 - add the "u-boot,dm-pre-reloc" property to determine which nodes
   which are needed by SPL and by the board_init_f stage.
 - fix the compile warning.
 - add spi0 node aliases.

Signed-off-by: Wenyou Yang 
---

Changes in v6:
 - Fix the missing "u-boot,dm-pre-reloc" property for sama5d36ek_cmp board.

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
 - Fix spi flash compatible using "spi-flash".

 arch/arm/dts/Makefile|8 +
 arch/arm/dts/sama5d3.dtsi| 1539 ++
 arch/arm/dts/sama5d31.dtsi   |   16 +
 arch/arm/dts/sama5d31ek.dts  |   56 ++
 arch/arm/dts/sama5d33.dtsi   |   14 +
 arch/arm/dts/sama5d33ek.dts  |   49 ++
 arch/arm/dts/sama5d34.dtsi   |   16 +
 arch/arm/dts/sama5d34ek.dts  |   66 ++
 arch/arm/dts/sama5d35.dtsi   |   18 +
 arch/arm/dts/sama5d35ek.dts  |   59 ++
 arch/arm/dts/sama5d36.dtsi   |   20 +
 arch/arm/dts/sama5d36ek.dts  |   57 ++
 arch/arm/dts/sama5d36ek_cmp.dts  |   55 ++
 arch/arm/dts/sama5d3_can.dtsi|   74 ++
 arch/arm/dts/sama5d3_emac.dtsi   |   55 ++
 arch/arm/dts/sama5d3_gmac.dtsi   |   88 +++
 arch/arm/dts/sama5d3_lcd.dtsi|  215 ++
 arch/arm/dts/sama5d3_mci2.dtsi   |   59 ++
 arch/arm/dts/sama5d3_tcb1.dtsi   |   39 +
 arch/arm/dts/sama5d3_uart.dtsi   |   79 ++
 arch/arm/dts/sama5d3xcm.dtsi |  123 +++
 arch/arm/dts/sama5d3xcm_cmp.dtsi |  166 
 arch/arm/dts/sama5d3xdm.dtsi |   41 +
 arch/arm/dts/sama5d3xmb.dtsi |  234 ++
 arch/arm/dts/sama5d3xmb_cmp.dtsi |  236 ++
 25 files changed, 3382 insertions(+)
 create mode 100644 arch/arm/dts/sama5d3.dtsi
 create mode 100644 arch/arm/dts/sama5d31.dtsi
 create mode 100644 arch/arm/dts/sama5d31ek.dts
 create mode 100644 arch/arm/dts/sama5d33.dtsi
 create mode 100644 arch/arm/dts/sama5d33ek.dts
 create mode 100644 arch/arm/dts/sama5d34.dtsi
 create mode 100644 arch/arm/dts/sama5d34ek.dts
 create mode 100644 arch/arm/dts/sama5d35.dtsi
 create mode 100644 arch/arm/dts/sama5d35ek.dts
 create mode 100644 arch/arm/dts/sama5d36.dtsi
 create mode 100644 arch/arm/dts/sama5d36ek.dts
 create mode 100644 arch/arm/dts/sama5d36ek_cmp.dts
 create mode 100644 arch/arm/dts/sama5d3_can.dtsi
 create mode 100644 arch/arm/dts/sama5d3_emac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_gmac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_lcd.dtsi
 create mode 100644 arch/arm/dts/sama5d3_mci2.dtsi
 create mode 100644 arch/arm/dts/sama5d3_tcb1.dtsi
 create mode 100644 arch/arm/dts/sama5d3_uart.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm_cmp.dtsi
 create mode 100644 arch/arm/dts/sama5d3xdm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb_cmp.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eb68c204bb..afed460ac9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -328,6 +328,14 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
+   sama5d31ek.dtb \
+   sama5d33ek.dtb \
+   sama5d34ek.dtb \
+   sama5d35ek.dtb \
+   sama5d36ek.dtb \
+   sama5d36ek_cmp.dtb
+
 dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2835-rpi-a-plus.dtb \
bcm2835-rpi-a.dtb \
diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
new file mode 100644
index 00..84ee089202
--- /dev/null
+++ b/arch/arm/dts/sama5d3.dtsi
@@ -0,0 +1,1539 @@
+/*
+ * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
+ *applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 
SoC
+ *
+ *  Copyright (C) 2013 Atmel,
+ *2013 Ludovic Desroches 
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "Atmel SAMA5D3 family SoC";
+   compatible = "atmel,sama5d3", "atmel,sama5";
+   interrupt-parent = <>;
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   serial5 = 
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   gpio4 = 
+   tcb0 = 
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   ssc0 = 
+   ssc1 = 
+   pwm0 = 
+   };
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   

[U-Boot] [PATCH v6 0/4] ARM: dts: at91: add dts files for the boards of SAMA5D3/4

[Wenyou Yang]

The purpose of the patchset is add the device tree files for boards,
sama5d3/sama5d4 Xplained board and sama5d3/sama5d4 EK board.

Changes in v6:
 - Fix the missing "u-boot,dm-pre-reloc" property for sama5d36ek_cmp board.

Changes in v5:
 - Integrate the dts patches for sama5d3 to one.
 - Add the "u-boot,dm-pre-reloc" property for SPL.
 - Update the commit log.
 - Rebase on v2017.03.

Changes in v4:
 - Rebase on the master branch on git://git.denx.de/u-boot-atmel.git
   commit: 0ff27d4a94637d4b1937c625d33212375bd118d9

Changes in v3:
 - Fix the compatible of spi flash, use "spi-flash".
 - Fix the compatible of spi flash, use "spi-flash".

Changes in v2:
 - Fix spi flash compatible using "spi-flash".
 - Remove unneeded the pinctrl node for cs pin of spi0.
 - Remove unneeded the pinctrl node for cs pin of spi0.

Wenyou Yang (4):
  ARM: at91: dt: add dts files for sama5d3xek board
  ARM: at91: dt: add dts file for sama5d3 Xplained
  ARM: dts: at91: add dts files for sama5d4 Xplained
  ARM: dts: at91: add dts file for sama5d4ek

 arch/arm/dts/Makefile  |   17 +
 arch/arm/dts/at91-sama5d3_xplained.dts |  348 ++
 arch/arm/dts/at91-sama5d4_xplained.dts |  286 +
 arch/arm/dts/at91-sama5d4ek.dts|  341 ++
 arch/arm/dts/sama5d3.dtsi  | 1539 +
 arch/arm/dts/sama5d31.dtsi |   16 +
 arch/arm/dts/sama5d31ek.dts|   56 +
 arch/arm/dts/sama5d33.dtsi |   14 +
 arch/arm/dts/sama5d33ek.dts|   49 +
 arch/arm/dts/sama5d34.dtsi |   16 +
 arch/arm/dts/sama5d34ek.dts|   66 ++
 arch/arm/dts/sama5d35.dtsi |   18 +
 arch/arm/dts/sama5d35ek.dts|   59 +
 arch/arm/dts/sama5d36.dtsi |   20 +
 arch/arm/dts/sama5d36ek.dts|   57 +
 arch/arm/dts/sama5d36ek_cmp.dts|   55 +
 arch/arm/dts/sama5d3_can.dtsi  |   74 ++
 arch/arm/dts/sama5d3_emac.dtsi |   55 +
 arch/arm/dts/sama5d3_gmac.dtsi |   88 ++
 arch/arm/dts/sama5d3_lcd.dtsi  |  215 
 arch/arm/dts/sama5d3_mci2.dtsi |   59 +
 arch/arm/dts/sama5d3_tcb1.dtsi |   39 +
 arch/arm/dts/sama5d3_uart.dtsi |   79 ++
 arch/arm/dts/sama5d3xcm.dtsi   |  123 ++
 arch/arm/dts/sama5d3xcm_cmp.dtsi   |  166 +++
 arch/arm/dts/sama5d3xdm.dtsi   |   41 +
 arch/arm/dts/sama5d3xmb.dtsi   |  234 
 arch/arm/dts/sama5d3xmb_cmp.dtsi   |  236 
 arch/arm/dts/sama5d4.dtsi  | 1935 
 29 files changed, 6301 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts
 create mode 100644 arch/arm/dts/at91-sama5d4_xplained.dts
 create mode 100644 arch/arm/dts/at91-sama5d4ek.dts
 create mode 100644 arch/arm/dts/sama5d3.dtsi
 create mode 100644 arch/arm/dts/sama5d31.dtsi
 create mode 100644 arch/arm/dts/sama5d31ek.dts
 create mode 100644 arch/arm/dts/sama5d33.dtsi
 create mode 100644 arch/arm/dts/sama5d33ek.dts
 create mode 100644 arch/arm/dts/sama5d34.dtsi
 create mode 100644 arch/arm/dts/sama5d34ek.dts
 create mode 100644 arch/arm/dts/sama5d35.dtsi
 create mode 100644 arch/arm/dts/sama5d35ek.dts
 create mode 100644 arch/arm/dts/sama5d36.dtsi
 create mode 100644 arch/arm/dts/sama5d36ek.dts
 create mode 100644 arch/arm/dts/sama5d36ek_cmp.dts
 create mode 100644 arch/arm/dts/sama5d3_can.dtsi
 create mode 100644 arch/arm/dts/sama5d3_emac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_gmac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_lcd.dtsi
 create mode 100644 arch/arm/dts/sama5d3_mci2.dtsi
 create mode 100644 arch/arm/dts/sama5d3_tcb1.dtsi
 create mode 100644 arch/arm/dts/sama5d3_uart.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm_cmp.dtsi
 create mode 100644 arch/arm/dts/sama5d3xdm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb_cmp.dtsi
 create mode 100644 arch/arm/dts/sama5d4.dtsi

-- 
2.11.0

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[U-Boot] [PATCH v4 3/6] board: sama5d3xek: enable early debug UART

[Wenyou Yang]

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/atmel/sama5d3xek/sama5d3xek.c| 13 -
 configs/sama5d3xek_mmc_defconfig   |  6 ++
 configs/sama5d3xek_nandflash_defconfig |  6 ++
 configs/sama5d3xek_spiflash_defconfig  |  6 ++
 4 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c
index 2a18d877a2..cae6e245dd 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -205,12 +206,22 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
at91_seriald_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+   debug_uart_init();
+#endif
return 0;
 }
+#endif
 
 int board_init(void)
 {
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index e71f87101d..994bc048ba 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -58,6 +58,12 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=13200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/sama5d3xek_nandflash_defconfig 
b/configs/sama5d3xek_nandflash_defconfig
index 2cd6691f4c..dd0263cea2 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -53,6 +53,12 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=13200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/sama5d3xek_spiflash_defconfig 
b/configs/sama5d3xek_spiflash_defconfig
index 748f4da77c..069fbcc0a3 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -54,6 +54,12 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=13200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
-- 
2.11.0

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[U-Boot] [PATCH v4 4/6] board: sama5d3_xplained: update to support DM/DT

[Wenyou Yang]

Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 configs/sama5d3_xplained_mmc_defconfig   | 29 +++-
 configs/sama5d3_xplained_nandflash_defconfig | 28 ++-
 include/configs/sama5d3_xplained.h   | 26 +++--
 3 files changed, 58 insertions(+), 25 deletions(-)

diff --git a/configs/sama5d3_xplained_mmc_defconfig 
b/configs/sama5d3_xplained_mmc_defconfig
index 2654aa11ba..921b6a2112 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -4,15 +4,19 @@ CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
+CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -29,6 +33,29 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig 
b/configs/sama5d3_xplained_nandflash_defconfig
index dc487d92e0..042f6a78e7 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -6,6 +6,9 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
@@ -27,6 +30,29 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/sama5d3_xplained.h 
b/include/configs/sama5d3_xplained.h
index 3c9f49e426..b4a62bd63a 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -12,11 +12,6 @@
 
 #include "at91-sama5_common.h"
 
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE  ATMEL_BASE_DBGU
-#define CONFIG_USART_IDATMEL_ID_DBGU
-
 /*
  * This needs to be defined for the OHCI code to work but it is defined as
  * ATMEL_ID_UHPHS in the CPU specific header files.
@@ -34,10 +29,10 @@
 #define CONFIG_SYS_SDRAM_SIZE  0x1000
 
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_INIT_SP_ADDR0x31
+#define CONFIG_SYS_INIT_SP_ADDR0x318000
 #else
 #define CONFIG_SYS_INIT_SP_ADDR \
-   (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+   (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
 #endif
 
 /* NAND flash */
@@ -67,21 +62,6 @@
 #define CONFIG_CMD_UBIFS
 #endif
 
-/* Ethernet Hardware */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-#define CONFIG_RGMII
-#define CONFIG_PHYLIB
-
-/* MMC */
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_ATMEL_MCI_8BIT
-#endif
-
 /* USB */
 
 #ifdef CONFIG_CMD_USB
@@ -111,7 +91,7 @@
 /* SPL */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE   0x30
-#define CONFIG_SPL_MAX_SIZE0x1
+#define CONFIG_SPL_MAX_SIZE0x18000
 #define CONFIG_SPL_BSS_START_ADDR  

[U-Boot] [PATCH v4 6/6] board: sama5d3_xplained: enable early debug UART

[Wenyou Yang]

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang 
---

Changes in v4: None
Changes in v3:
 - Convert the macb to support DM and clean up macb init code.
 - Remain the SPI speed macros.
 - Update the config options for SPL.
 - Update the commit log.
 - Remove the unneeded dbgu init during board_early_init_f stage.
 - Use CONFIG_DEBUG_UART_CLOCK as the input clock for the early
   debug uart.
 - Drop [PATCH] configs: sama5d3_xplained: move CONFIG_SYS_NO_FLASH
   to defconfig.
 - Rebase on v2017.03.

Changes in v2:
 - rebase on the patch set:
[PATCH v3 0/8] board: sama5d4: convert boards to support DM/DT
http://lists.denx.de/pipermail/u-boot/2017-February/280506.html

 board/atmel/sama5d3_xplained/sama5d3_xplained.c | 13 -
 configs/sama5d3_xplained_mmc_defconfig  |  6 ++
 configs/sama5d3_xplained_nandflash_defconfig|  6 ++
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c 
b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index f2f5506adc..21f332b382 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -65,12 +66,22 @@ static void sama5d3_xplained_mci0_hw_init(void)
 }
 #endif
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
at91_seriald_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+   debug_uart_init();
+#endif
return 0;
 }
+#endif
 
 int board_init(void)
 {
diff --git a/configs/sama5d3_xplained_mmc_defconfig 
b/configs/sama5d3_xplained_mmc_defconfig
index 921b6a2112..d28d1d9a33 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -54,6 +54,12 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=13200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig 
b/configs/sama5d3_xplained_nandflash_defconfig
index 042f6a78e7..8cc8169de5 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -51,6 +51,12 @@ CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=13200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-- 
2.11.0

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[U-Boot] [PATCH v4 5/6] board: sama5d3_xplained: clean up code

[Wenyou Yang]

Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.

Signed-off-by: Wenyou Yang 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/atmel/sama5d3_xplained/sama5d3_xplained.c | 34 -
 1 file changed, 34 deletions(-)

diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c 
b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 2b9da91b2d..f2f5506adc 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -6,16 +6,12 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
 #include 
 #include 
 #include 
@@ -65,20 +61,12 @@ static void sama5d3_xplained_usb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 static void sama5d3_xplained_mci0_hw_init(void)
 {
-   at91_mci_hw_init();
-
at91_set_pio_output(AT91_PIO_PORTE, 2, 0);  /* MCI0 Power */
 }
 #endif
 
 int board_early_init_f(void)
 {
-   at91_periph_clk_enable(ATMEL_ID_PIOA);
-   at91_periph_clk_enable(ATMEL_ID_PIOB);
-   at91_periph_clk_enable(ATMEL_ID_PIOC);
-   at91_periph_clk_enable(ATMEL_ID_PIOD);
-   at91_periph_clk_enable(ATMEL_ID_PIOE);
-
at91_seriald_hw_init();
 
return 0;
@@ -98,10 +86,6 @@ int board_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3_xplained_mci0_hw_init();
 #endif
-#ifdef CONFIG_MACB
-   at91_gmac_hw_init();
-   at91_macb_hw_init();
-#endif
return 0;
 }
 
@@ -113,24 +97,6 @@ int dram_init(void)
return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_MACB
-   macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
-   macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-#endif
-   return 0;
-}
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
-   atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
-   return 0;
-}
-#endif
-
 /* SPL */
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
-- 
2.11.0

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[U-Boot] [PATCH v4 2/6] board: sama5d3xek: clean up code

[Wenyou Yang]

Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.

Signed-off-by: Wenyou Yang 
---

Changes in v4:
 - Remove the ethernet init code completely.

Changes in v3: None
Changes in v2: None

 board/atmel/sama5d3xek/sama5d3xek.c | 134 +---
 1 file changed, 1 insertion(+), 133 deletions(-)

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c
index 1d96149921..2a18d877a2 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -6,7 +6,6 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -16,19 +15,12 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 /* - */
@@ -135,8 +127,6 @@ static void sama5d3xek_usb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 static void sama5d3xek_mci_hw_init(void)
 {
-   at91_mci_hw_init();
-
at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
 }
 #endif
@@ -217,12 +207,6 @@ void lcd_show_board_info(void)
 
 int board_early_init_f(void)
 {
-   at91_periph_clk_enable(ATMEL_ID_PIOA);
-   at91_periph_clk_enable(ATMEL_ID_PIOB);
-   at91_periph_clk_enable(ATMEL_ID_PIOC);
-   at91_periph_clk_enable(ATMEL_ID_PIOD);
-   at91_periph_clk_enable(ATMEL_ID_PIOE);
-
at91_seriald_hw_init();
 
return 0;
@@ -242,21 +226,9 @@ int board_init(void)
 #ifdef CONFIG_CMD_USB
sama5d3xek_usb_hw_init();
 #endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-   at91_udp_hw_init();
-#endif
 #ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3xek_mci_hw_init();
 #endif
-#ifdef CONFIG_ATMEL_SPI
-   at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
-   if (has_emac())
-   at91_macb_hw_init();
-   if (has_gmac())
-   at91_gmac_hw_init();
-#endif
 #ifdef CONFIG_LCD
if (has_lcdc())
sama5d3xek_lcd_hw_init();
@@ -271,106 +243,6 @@ int dram_init(void)
return 0;
 }
 
-int board_phy_config(struct phy_device *phydev)
-{
-   /* board specific timings for GMAC */
-   if (has_gmac()) {
-   /* rx data delay */
-   ksz9021_phy_extended_write(phydev,
-  MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-  0x);
-   /* tx data delay */
-   ksz9021_phy_extended_write(phydev,
-  MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-  0x);
-   /* rx/tx clock delay */
-   ksz9021_phy_extended_write(phydev,
-  MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-  0xf2f4);
-   }
-
-   /* always run the PHY's config routine */
-   if (phydev->drv->config)
-   return phydev->drv->config(phydev);
-
-   return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-   int rc = 0;
-
-#ifdef CONFIG_MACB
-   if (has_emac())
-   rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-   if (has_gmac())
-   rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
-#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-   usba_udc_probe();
-#ifdef CONFIG_USB_ETH_RNDIS
-   usb_eth_initialize(bis);
-#endif
-#endif
-
-   return rc;
-}
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
-   int rc = 0;
-
-   rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
-   return rc;
-}
-#endif
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include 
-
-#ifndef CONFIG_DM_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   return bus == 0 && cs < 4;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-   switch (slave->cs) {
-   case 0:
-   at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
-   case 1:
-   at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
-   case 2:
-   at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
-   case 3:
-   at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
-   default:
-   break;
-   }
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-   switch (slave->cs) {
-   case 0:
-   at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
-   case 1:
-   at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
-   case 2:
-   at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
-   case 3:
-   at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
-   default:
-   break;
-   }
-}
-#endif
-#endif /* CONFIG_ATMEL_SPI 

[U-Boot] [PATCH v4 1/6] board: sama5d3xek: update to support DM/DT

[Wenyou Yang]

Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang 
---

Changes in v4:
 - Remove wrong using CONFIG_PHY_MICREL.

Changes in v3: None
Changes in v2: None

 board/atmel/sama5d3xek/sama5d3xek.c|  2 ++
 configs/sama5d3xek_mmc_defconfig   | 34 -
 configs/sama5d3xek_nandflash_defconfig | 31 +-
 configs/sama5d3xek_spiflash_defconfig  | 35 +++---
 include/configs/sama5d3xek.h   | 35 --
 5 files changed, 101 insertions(+), 36 deletions(-)

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c
index 134c2fe1eb..1d96149921 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -331,6 +331,7 @@ int board_mmc_init(bd_t *bis)
 #ifdef CONFIG_ATMEL_SPI
 #include 
 
+#ifndef CONFIG_DM_SPI
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
return bus == 0 && cs < 4;
@@ -367,6 +368,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
break;
}
 }
+#endif
 #endif /* CONFIG_ATMEL_SPI */
 
 #ifdef CONFIG_BOARD_LATE_INIT
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index b73d647ee3..e71f87101d 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -4,10 +4,13 @@ CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
@@ -15,6 +18,7 @@ CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
+CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -26,13 +30,41 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig 
b/configs/sama5d3xek_nandflash_defconfig
index 7f68d7db96..2cd6691f4c 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -4,8 +4,11 @@ CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
@@ -25,12 +28,38 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig 
b/configs/sama5d3xek_spiflash_defconfig
index c7a183f7ce..748f4da77c 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -4,20 +4,23 @@ CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y

[U-Boot] [PATCH v4 0/6] board: sama5d3: convert boards to support DM/DT

[Wenyou Yang]

The purpose of patch set is to convert the board to support device
tree and driver model, and enable the early debug UART as well.
It is based on the patch set:
[PATCH v8 0/2] pinctrl: at91: Add pinctrl driver
https://lists.denx.de/pipermail/u-boot/2017-March/284577.html

Changes in v4:
 - Remove wrong using CONFIG_PHY_MICREL.
 - Remove the ethernet init code completely.

Changes in v3:
 - Convert the macb to support DM and clean up macb init code.
 - Remain the SPI speed macros.
 - Update the config options for SPL.
 - Update the commit log.
 - Remove the unneeded dbgu init during board_early_init_f stage.
 - Use CONFIG_DEBUG_UART_CLOCK as the input clock for the early
   debug uart.
 - Drop [PATCH] configs: sama5d3_xplained: move CONFIG_SYS_NO_FLASH
   to defconfig.
 - Rebase on v2017.03.

Changes in v2:
 - rebase on the patch set:
[PATCH v3 0/8] board: sama5d4: convert boards to support DM/DT
http://lists.denx.de/pipermail/u-boot/2017-February/280506.html

Wenyou Yang (6):
  board: sama5d3xek: update to support DM/DT
  board: sama5d3xek: clean up code
  board: sama5d3xek: enable early debug UART
  board: sama5d3_xplained: update to support DM/DT
  board: sama5d3_xplained: clean up code
  board: sama5d3_xplained: enable early debug UART

 board/atmel/sama5d3_xplained/sama5d3_xplained.c |  47 ++--
 board/atmel/sama5d3xek/sama5d3xek.c | 145 +++-
 configs/sama5d3_xplained_mmc_defconfig  |  35 +-
 configs/sama5d3_xplained_nandflash_defconfig|  34 +-
 configs/sama5d3xek_mmc_defconfig|  40 ++-
 configs/sama5d3xek_nandflash_defconfig  |  37 +-
 configs/sama5d3xek_spiflash_defconfig   |  41 ++-
 include/configs/sama5d3_xplained.h  |  26 +
 include/configs/sama5d3xek.h|  35 +-
 9 files changed, 212 insertions(+), 228 deletions(-)

-- 
2.11.0

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Re: [U-Boot] [PATCH 05/17] aspeed: Reset Driver

[Maxim Sloyko]

On Tue, Mar 21, 2017 at 4:22 PM, Simon Glass  wrote:
>
> Hi Maxim,
>
> On 16 March 2017 at 15:36, Maxim Sloyko  wrote:
> > Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
> > perform resets and thus depends on it. The actual Watchdog device used
> > needs to be configured in Device Tree using "aspeed,wdt" property, which
> > must be WDT phandle, for example:
> >
> > rst: reset-controller {
> > compatible = "aspeed,ast2500-reset";
> > aspeed,wdt = <>;
> > }
> >
> > Signed-off-by: Maxim Sloyko 
> > ---
> >
> >  arch/arm/include/asm/arch-aspeed/scu_ast2500.h |  28 +++
> >  drivers/reset/Kconfig  |  10 +++
> >  drivers/reset/Makefile |   1 +
> >  drivers/reset/ast2500-reset.c  | 109 
> > +
> >  4 files changed, 148 insertions(+)
> >  create mode 100644 drivers/reset/ast2500-reset.c
> >
>
> Reviewed-by: Simon Glass 
>
> Nits below.
>
> > diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h 
> > b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > index 0fa3ecb9b9..e2556f920d 100644
> > --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > @@ -31,6 +31,34 @@
> >
> >  #define SCU_MISC_UARTCLK_DIV13 (1 << 12)
> >
> > +/*
> > + * SYSRESET is actually more like a Power register,
> > + * except that corresponding bit set to 1 means that
> > + * the peripheral is off.
> > + */
> > +#define SCU_SYSRESET_XDMA  (1 << 25)
> > +#define SCU_SYSRESET_MCTP  (1 << 24)
> > +#define SCU_SYSRESET_ADC   (1 << 23)
> > +#define SCU_SYSRESET_JTAG  (1 << 22)
> > +#define SCU_SYSRESET_MIC   (1 << 18)
> > +#define SCU_SYSRESET_SDIO  (1 << 16)
> > +#define SCU_SYSRESET_USB11HOST (1 << 15)
> > +#define SCU_SYSRESET_USBHUB(1 << 14)
> > +#define SCU_SYSRESET_CRT   (1 << 13)
> > +#define SCU_SYSRESET_MAC2  (1 << 12)
> > +#define SCU_SYSRESET_MAC1  (1 << 11)
> > +#define SCU_SYSRESET_PECI  (1 << 10)
> > +#define SCU_SYSRESET_PWM   (1 << 9)
> > +#define SCU_SYSRESET_PCI_VGA   (1 << 8)
> > +#define SCU_SYSRESET_2D(1 << 7)
> > +#define SCU_SYSRESET_VIDEO (1 << 6)
> > +#define SCU_SYSRESET_LPC   (1 << 5)
> > +#define SCU_SYSRESET_HAC   (1 << 4)
> > +#define SCU_SYSRESET_USBHID(1 << 3)
> > +#define SCU_SYSRESET_I2C   (1 << 2)
> > +#define SCU_SYSRESET_AHB   (1 << 1)
> > +#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
> > +
> >  #ifndef __ASSEMBLY__
> >
> >  struct ast2500_clk_priv {
> > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> > index c42b0bcf0e..eb54189d4b 100644
> > --- a/drivers/reset/Kconfig
> > +++ b/drivers/reset/Kconfig
> > @@ -43,4 +43,14 @@ config RESET_UNIPHIER
> >   Say Y if you want to control reset signals provided by System 
> > Control
> >   block, Media I/O block, Peripheral Block.
> >
> > +config AST2500_RESET
> > +   bool "Reset controller driver for AST2500 SoCs"
> > +   depends on DM_RESET && WDT_ASPEED
> > +   default y if ASPEED_AST2500
> > +   help
> > + Support for reset controller on AST2500 SoC. This controller uses
> > + watchdog to reset different peripherals and thus only supports
> > + resets that are supported by watchdog. The main limitation though
> > + is that some reset signals, like I2C or MISC reset multiple 
> > devices.
> > +
> >  endmenu
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> > index 5c4305cc1d..16ad7eed5b 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
> >  obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
> >  obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
> >  obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
> > +obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
> > diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
> > new file mode 100644
> > index 00..0afa4bd01a
> > --- /dev/null
> > +++ b/drivers/reset/ast2500-reset.c
> > @@ -0,0 +1,109 @@
> > +/*
> > + * Copyright 2017 Google, Inc
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +struct ast2500_reset_priv {
> > +   /* WDT used to perform resets. */
> > +   struct udevice *wdt;
> > +   struct ast2500_scu *scu;
> > +};
> > +
> > +static int ast2500_ofdata_to_platdata(struct udevice *dev)
> > +{
> > +   struct ast2500_reset_priv *priv = dev_get_priv(dev);
> > +   int ret;
> > +
> > +

Re: [U-Boot] [ PATCH 2/2] net: move Broadcom SF2 driver to Kconfig

[Suji Velupillai]

Thank you Joe for your time and feedback,
Please see the answers inline.
Suji


On Tue, Mar 21, 2017 at 11:53 AM, Joe Hershberger  wrote:

> On Fri, Mar 3, 2017 at 7:06 PM, Steve Rae  wrote:
> > From: Suji Velupillai 
> >
> > move to Kconfig:
> > CONFIG_BCM_SF2_ETH
> > CONFIG_BCM_SF2_ETH_GMAC
> >
> > Also modified defconfigs of all platforms that use these configs.
> >
> > Signed-off-by: Suji Velupillai 
> > Tested-by: Suji Velupillai 
> > Reviewed-by: JD Zheng 
> > Reviewed-by: Scott Branden 
> > Signed-off-by: Steve Rae 
> > ---
> >
> >  arch/arm/include/asm/arch-bcmcygnus/configs.h |  6 +-
> >  configs/bcm28155_w1d_defconfig|  5 +++--
> >  configs/bcm911360_entphn-ns_defconfig |  3 +++
> >  configs/bcm911360_entphn_defconfig|  3 +++
> >  configs/bcm911360k_defconfig  |  3 +++
> >  configs/bcm958300k-ns_defconfig   |  3 +++
> >  configs/bcm958300k_defconfig  |  3 +++
> >  configs/bcm958305k_defconfig  |  3 +++
> >  drivers/net/Kconfig   | 15 +++
> >  scripts/config_whitelist.txt  |  2 --
> >  10 files changed, 37 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h
> b/arch/arm/include/asm/arch-bcmcygnus/configs.h
> > index af7f3bf..92b1c5e 100644
> > --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
> > +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright 2014 Broadcom Corporation.
> > + * Copyright 2014-2017 Broadcom.
> >   *
> >   * SPDX-License-Identifier:GPL-2.0+
> >   */
> > @@ -23,10 +23,6 @@
> >  #define CONFIG_SYS_NS16550_COM30x18023000
> >
> >  /* Ethernet */
> > -#define CONFIG_BCM_SF2_ETH
> > -#define CONFIG_BCM_SF2_ETH_GMAC
> > -
> > -#define CONFIG_PHYLIB
> >  #define CONFIG_PHY_BROADCOM
> >  #define CONFIG_PHY_RESET_DELAY 1 /* PHY reset delay in us*/
> >
> > diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_
> defconfig
> > index aa5216e..4adbce6 100644
> > --- a/configs/bcm28155_w1d_defconfig
> > +++ b/configs/bcm28155_w1d_defconfig
> > @@ -1,7 +1,6 @@
> >  CONFIG_ARM=y
> >  CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> >  CONFIG_TARGET_BCM28155_AP=y
> > -CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
> >  CONFIG_VERSION_VARIABLE=y
> >  # CONFIG_DISPLAY_CPUINFO is not set
> >  # CONFIG_DISPLAY_BOARDINFO is not set
> > @@ -15,7 +14,6 @@ CONFIG_CMD_MMC=y
> >  CONFIG_CMD_I2C=y
> >  CONFIG_CMD_GPIO=y
> >  # CONFIG_CMD_SETEXPR is not set
> > -# CONFIG_CMD_NET is not set
> >  # CONFIG_CMD_NFS is not set
> >  CONFIG_CMD_CACHE=y
> >  CONFIG_CMD_FAT=y
> > @@ -33,3 +31,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
> >  CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
> >  CONFIG_G_DNL_VENDOR_NUM=0x18d1
> >  CONFIG_G_DNL_PRODUCT_NUM=0x0d02
> > +CONFIG_NETDEVICES=y
> > +CONFIG_BCM_SF2_ETH=y
> > +CONFIG_BCM_SF2_ETH_GMAC=y
> > diff --git a/configs/bcm911360_entphn-ns_defconfig
> b/configs/bcm911360_entphn-ns_defconfig
> > index adcc152..f1df78a 100644
> > --- a/configs/bcm911360_entphn-ns_defconfig
> > +++ b/configs/bcm911360_entphn-ns_defconfig
> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
> >  CONFIG_CMD_FAT=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_OF_LIBFDT=y
> > +CONFIG_NETDEVICES=y
> > +CONFIG_BCM_SF2_ETH=y
> > +CONFIG_BCM_SF2_ETH_GMAC=y
> > diff --git a/configs/bcm911360_entphn_defconfig
> b/configs/bcm911360_entphn_defconfig
> > index e49071d..22da69e 100644
> > --- a/configs/bcm911360_entphn_defconfig
> > +++ b/configs/bcm911360_entphn_defconfig
> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
> >  CONFIG_CMD_FAT=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_OF_LIBFDT=y
> > +CONFIG_NETDEVICES=y
> > +CONFIG_BCM_SF2_ETH=y
> > +CONFIG_BCM_SF2_ETH_GMAC=y
> > diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
> > index 8077c4a..0281fc8 100644
> > --- a/configs/bcm911360k_defconfig
> > +++ b/configs/bcm911360k_defconfig
> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
> >  CONFIG_CMD_FAT=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_OF_LIBFDT=y
> > +CONFIG_NETDEVICES=y
> > +CONFIG_BCM_SF2_ETH=y
> > +CONFIG_BCM_SF2_ETH_GMAC=y
> > diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_
> defconfig
> > index 26d0b0b..c837721 100644
> > --- a/configs/bcm958300k-ns_defconfig
> > +++ b/configs/bcm958300k-ns_defconfig
> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
> >  CONFIG_CMD_FAT=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_OF_LIBFDT=y
> > +CONFIG_NETDEVICES=y
> > +CONFIG_BCM_SF2_ETH=y
> > +CONFIG_BCM_SF2_ETH_GMAC=y
> > diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
> > index 8077c4a..0281fc8 100644
> > --- a/configs/bcm958300k_defconfig
> > +++ b/configs/bcm958300k_defconfig
> > @@ 

[U-Boot] about TLB mapping(Powerpc T1024RDB)

[shoulianyu]

Hi,
I'm new to Uboot. Can someone help me.
I went through the tbl_table (in tlb.c) and got puzzled by the following 
entries:
...
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
   MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
   0, 2, BOOKE_PAGESZ_256M, 1),
...
 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
   MAS3_SX|MAS3_SW|MAS3_SR, 0,
   0, 5, BOOKE_PAGESZ_16M, 1),


The first entry  maps 256M space starting at 0xe800_, which is  
[0xe800_, 0xf800_) .
The second 16M at  0xf400_,which is [0xf400_, 0xf500_)
the thing I can't understand is how  TLB entries can overlap each other.
Isn't it considered a programming error as pointed out in the E5500Core Ref?


I know I must have got something wrong, but I checked the header files and did 
the calcs again and again,
still, nothing dawned on me. 


I'm using  Freescale T1024RDB board.


please help!!!
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Re: [U-Boot] [PATCH 16/17] aspeed: Add AST2500/AST2400 compatible NIC Driver

[Maxim Sloyko]

On Wed, Mar 22, 2017 at 6:06 AM, Simon Glass  wrote:

> Hi Maxim,
>
> On 21 March 2017 at 17:44, Maxim Sloyko  wrote:
> > Hi Joe,
> >
> > Please see responses inline, simply ACK'ed comments will be addressed
> > in the next version.
> >
> > On Tue, Mar 21, 2017 at 12:32 PM, Joe Hershberger
> >  wrote:
> >> On Thu, Mar 16, 2017 at 4:36 PM, Maxim Sloyko 
> wrote:
> >>> The device that Aspeed uses is basically Faraday FTGMAC100, but with
> >>> some differences here and there. Since I don't have access to a
> properly
> >>> implemented FTGMAC100 though, I can't really test it and so I don't
> >>> feel comfortable claiming compatibility, even though I reused a lot of
> >>> FTGMAC100 driver code.
> >>
> >> I think it would be better to attempt to integrate this driver with
> >> the FTGMAC driver and ask others on the list who have that HW to test
> >> your changes to ensure no regressions. I prefer we have fewer drivers
> >> to maintain.
> >
> > One concern: this driver also performs its clock configuration, which
> > I believe is very specific to the SoC, so to have that compatibility
> > clock configuration needs to be externalized somehow. I don't know
> > what is the best way to do it.
>
> Generally the clock is defined by a DT property in the node, so this
> should work out OK.
>

Well, this device on this SoC needs two different clocks configured, one
for all devices and one device specific. The device speed is also hardware
strapped, so it reads the unrelated register to figure out which rate to
enable. Not to mention, it's still unclear how it's going to be done in
Linux, so somewhere else in this review Tom actually suggested to go non-DT
way with this.

Anyway, I'm going to drop this driver from this series and work this out
separately, just to keep things moving, because it looks like it raises the
largest number of concerns.


>
> Regards,
> Simon
>



-- 
*M*axim *S*loyko
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[U-Boot] [PATCH] rockchip: Add support for MiQi rk3288 board

[Jernej Skrabec]

MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.

Signed-off-by: Jernej Skrabec 
---

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/rk3288-miqi.dts|  46 
 arch/arm/dts/rk3288-miqi.dtsi   | 459 
 arch/arm/mach-rockchip/rk3288/Kconfig   |  11 +
 board/mqmaker/miqi_rk3288/Kconfig   |  15 ++
 board/mqmaker/miqi_rk3288/MAINTAINERS   |   6 +
 board/mqmaker/miqi_rk3288/Makefile  |   7 +
 board/mqmaker/miqi_rk3288/miqi-rk3288.c |  15 ++
 configs/miqi-rk3288_defconfig   |  73 +
 doc/README.rockchip |   5 +-
 include/configs/miqi_rk3288.h   |  22 ++
 11 files changed, 658 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/rk3288-miqi.dts
 create mode 100644 arch/arm/dts/rk3288-miqi.dtsi
 create mode 100644 board/mqmaker/miqi_rk3288/Kconfig
 create mode 100644 board/mqmaker/miqi_rk3288/MAINTAINERS
 create mode 100644 board/mqmaker/miqi_rk3288/Makefile
 create mode 100644 board/mqmaker/miqi_rk3288/miqi-rk3288.c
 create mode 100644 configs/miqi-rk3288_defconfig
 create mode 100644 include/configs/miqi_rk3288.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index afeb43ff66..60a9aeb698 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-fennec.dtb \
rk3288-tinker.dtb \
rk3288-popmetal.dtb \
+   rk3288-miqi.dtb \
rk3328-evb.dtb \
rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts
new file mode 100644
index 00..7b92caf024
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi.dts
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-miqi.dtsi"
+
+/ {
+   model = "mqmaker MiQi";
+   compatible = "mqmaker,miqi", "rockchip,rk3288";
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+};
+
+ {
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   reg-shift = <2>;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
new file mode 100644
index 00..12e584f242
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi.dtsi
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2016 Heiko Stuebner 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * 

[U-Boot] [PATCH 3/3] rockchip: rk3188: add README.rockchip paragraph describing sd boot

[Heiko Stuebner]

Building sd images for rk3188 requires more steps due to the needed split
into TPL and SPL as loaders. Describe how to build an image for it in a
separate paragraph in the READER.rockchip file.

Signed-off-by: Heiko Stuebner 
---
 doc/README.rockchip | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index 186a1a007e..cb81efd4bf 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -147,6 +147,32 @@ For evb_rk3036 board:
 Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, 
the
   debug uart must be disabled
 
+
+Booting from an SD card on RK3188
+=
+
+For rk3188 boards the general storage onto the card stays the same as
+described above, but the image creation needs a bit more care.
+
+The bootrom of rk3188 expects to find a small 1kb loader which returns
+control to the bootrom, after which it will load the real loader, which
+can then be up to 29kb in size and does the regular ddr init.
+
+Additionally the rk3188 requires everything the bootrom loads to be
+rc4-encrypted. Except for the very first stage the bootrom always reads
+and decodes 2kb pages, so files should be sized accordingly.
+
+# copy tpl, pad to 1020 bytes and append spl
+cat tpl/u-boot-tpl.bin > tplspl.bin
+truncate -s 1020 tplspl.bin
+cat spl/u-boot-spl.bin >> tplspl.bin
+tools/mkimage -n rk3188 -T rksd -d tplspl.bin out
+
+# truncate, encode and append u-boot.bin
+truncate -s %2048 u-boot.bin
+cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 
7C4E0304550509072D2C7B38170D1711' >> out
+
+
 Using fastboot on rk3288
 
 - Write GPT partition layout to mmc device which fastboot want to use it to
-- 
2.11.0

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[U-Boot] [PATCH 2/3] rockchip: rk3188: Add Radxa Rock board

[Heiko Stuebner]

The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.

Signed-off-by: Heiko Stuebner 
Reviewed-by: Simon Glass 
Tested-by: Kever Yang 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3188-radxarock.dts | 382 ++
 arch/arm/mach-rockchip/rk3188/Kconfig |  11 +
 board/radxa/rock/Kconfig  |  15 ++
 board/radxa/rock/MAINTAINERS  |   6 +
 board/radxa/rock/Makefile |   7 +
 board/radxa/rock/rock.c   |   7 +
 configs/rock_defconfig|  58 ++
 include/configs/rock.h|  30 +++
 9 files changed, 517 insertions(+)
 create mode 100644 arch/arm/dts/rk3188-radxarock.dts
 create mode 100644 board/radxa/rock/Kconfig
 create mode 100644 board/radxa/rock/MAINTAINERS
 create mode 100644 board/radxa/rock/Makefile
 create mode 100644 board/radxa/rock/rock.c
 create mode 100644 configs/rock_defconfig
 create mode 100644 include/configs/rock.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d00651c74c..8c726c3d10 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
+   rk3188-radxarock.dtb \
rk3288-firefly.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
diff --git a/arch/arm/dts/rk3188-radxarock.dts 
b/arch/arm/dts/rk3188-radxarock.dts
new file mode 100644
index 00..5f5b5e9a1f
--- /dev/null
+++ b/arch/arm/dts/rk3188-radxarock.dts
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner 
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include 
+#include "rk3188.dtsi"
+
+/ {
+   model = "Radxa Rock";
+   compatible = "radxa,rock", "rockchip,rk3188";
+
+   chosen {
+/* stdout-path =  */
+   stdout-path = "serial2:115200n8";
+   };
+
+   config {
+   u-boot,dm-pre-reloc;
+   u-boot,boot-led = "rock:red:power";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x6000 0x8000>;
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+
+   power {
+   gpios = < 4 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "GPIO Key Power";
+   linux,input-type = <1>;
+   wakeup-source;
+   debounce-interval = <100>;
+   };
+   };
+
+   gpio-leds {
+   compatible = "gpio-leds";
+
+   green {
+   label = "rock:green:user1";
+   gpios = < 12 GPIO_ACTIVE_LOW>;
+   default-state = "off";
+   };
+
+   blue {
+   label = "rock:blue:user2";
+   gpios = < 14 GPIO_ACTIVE_LOW>;
+   default-state = "off";
+   };
+
+   sleep {
+   label = "rock:red:power";
+   gpios = < 15 0>;
+   default-state = "off";
+   };
+   };
+
+   sound {
+   compatible = "simple-audio-card";
+   simple-audio-card,name = "SPDIF";
+
+   simple-audio-card,dai-link@1 {  /* S/PDIF - S/PDIF */
+   cpu { sound-dai = <>; };
+   codec { sound-dai = <_out>; };
+   };
+   };
+
+   spdif_out: spdif-out {
+   compatible = "linux,spdif-dit";
+   #sound-dai-cells = <0>;
+   };
+
+   ir_recv: gpio-ir-receiver {
+   compatible = "gpio-ir-receiver";
+   gpios = < 10 1>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_recv_pin>;
+   };
+
+   vcc_otg: usb-otg-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 31 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_vbus_drv>;
+   regulator-name = "otg-vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   vcc_sd0: sdmmc-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "sdmmc-supply";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = < 1 

[U-Boot] [PATCH 1/3] rockchip: rk3188: enable TPL_LIBGENERIC for generic memset

[Heiko Stuebner]

Commit c67c8c604b6c ("board_init.c: Always use memset()") dropped the naive
memset alternative from board_init_f_init_reserve.
So activate CONFIG_TPL_LIBGENERIC for that common memset implementation.
We cannot use the ARCH-specific memset, as that would incur 200bytes of
additional TPL size, space we do not have.

Signed-off-by: Heiko Stuebner 
---
 arch/arm/mach-rockchip/rk3188/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig 
b/arch/arm/mach-rockchip/rk3188/Kconfig
index f8e1d0316b..b70d45cd62 100644
--- a/arch/arm/mach-rockchip/rk3188/Kconfig
+++ b/arch/arm/mach-rockchip/rk3188/Kconfig
@@ -18,6 +18,9 @@ config SPL_SERIAL_SUPPORT
 config TPL_LIBCOMMON_SUPPORT
default y
 
+config TPL_LIBGENERIC_SUPPORT
+   default y
+
 config TPL_SERIAL_SUPPORT
default y
 
-- 
2.11.0

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[U-Boot] [PATCH 0/3] rockchip: rk3188 fixed early stage and radxarock board

[Heiko Stuebner]

Applies on top of current rockchip master branch and needs
Kever's early_init patch for rk3188 and rk3399.

After this one series, there is of course still
rockchip: rk3188: fixups and armclk speedup
series and
rockchip: rk3188: enable remap function
patch open.


changes compared to the original patches:
- made it apply on top of current rockchip master
- arranged in a way to not create build errors
- so adapted the TPL_LIBGENERIC patch to be in front
  of the rock board addition

Heiko Stuebner (3):
  rockchip: rk3188: enable TPL_LIBGENERIC for generic memset
  rockchip: rk3188: Add Radxa Rock board
  rockchip: rk3188: add README.rockchip paragraph describing sd boot

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3188-radxarock.dts | 382 ++
 arch/arm/mach-rockchip/rk3188/Kconfig |  14 ++
 board/radxa/rock/Kconfig  |  15 ++
 board/radxa/rock/MAINTAINERS  |   6 +
 board/radxa/rock/Makefile |   7 +
 board/radxa/rock/rock.c   |   7 +
 configs/rock_defconfig|  58 ++
 doc/README.rockchip   |  26 +++
 include/configs/rock.h|  30 +++
 10 files changed, 546 insertions(+)
 create mode 100644 arch/arm/dts/rk3188-radxarock.dts
 create mode 100644 board/radxa/rock/Kconfig
 create mode 100644 board/radxa/rock/MAINTAINERS
 create mode 100644 board/radxa/rock/Makefile
 create mode 100644 board/radxa/rock/rock.c
 create mode 100644 configs/rock_defconfig
 create mode 100644 include/configs/rock.h

-- 
2.11.0

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[U-Boot] [PATCH] rockchip: spl: RK3399: add COUNTER_FREQUENCY define to rk3399_common.h

[Philipp Tomsich]

The BootROM of the RK3399 SoC does not initialise the cntfrq_el0 (which
holds the value 0 (zero) on entry into the SPL. This causes the timebase
for U-Boot not to advance (and will cause a hang where a timeout would
be expected... e.g. if something goes wrong during MMC/SD card startup).

This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0 (if necessary).

Signed-off-by: Philipp Tomsich 
---

 include/configs/rk3399_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index aeee805..c44f8ad 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -19,6 +19,8 @@
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 
+#define COUNTER_FREQUENCY   2400
+
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_TEXT_BASE   0x0020
-- 
1.9.1

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[U-Boot] [PATCH] ti: clocks: Fix do_enable_clocks() to accept NULL pointers as input parameters

[Lukasz Majewski]

Up till this commit passing NULL as input parameter was allowed, but not
handled properly.

When one passed NULL to one of this function parameters, the code was
executed causing data abort.

However, what is more interesting, the abort was not caught because of code
execution in HYP mode with masked CPSR A bit ("Imprecise Data Abort mask bit).
The TI's AM57xx SoC switch to HYP mode with A bit masked in lowlevel_init.S
due to SMC call. Such operation (by default) is performed in SoC ROM code.

The problem would pop up when one:
- Switch back to SVC mode after disabling LPAE support
- Somebody enables A bit (by executing cpsie a asm instruction)

and then the previously described exception would be caught.

Signed-off-by: Lukasz Majewski 
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c 
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 097b8e3..157155a 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -822,27 +822,29 @@ void do_enable_clocks(u32 const *clk_domains,
u32 i, max = 100;
 
/* Put the clock domains in SW_WKUP mode */
-   for (i = 0; (i < max) && clk_domains[i]; i++) {
+   for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
}
 
/* Clock modules that need to be put in HW_AUTO */
-   for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
+   for (i = 0; (i < max) && clk_modules_hw_auto &&
+clk_modules_hw_auto[i]; i++) {
enable_clock_module(clk_modules_hw_auto[i],
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
wait_for_enable);
};
 
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
-   for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+   for (i = 0; (i < max) && clk_modules_explicit_en &&
+clk_modules_explicit_en[i]; i++) {
enable_clock_module(clk_modules_explicit_en[i],
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
wait_for_enable);
};
 
/* Put the clock domains in HW_AUTO mode now */
-   for (i = 0; (i < max) && clk_domains[i]; i++) {
+   for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
}
-- 
2.1.4

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[U-Boot] [PATCH v2 2/2] rockchip: config: rk3399: update defconfigs and rk3399_common

[Philipp Tomsich]

With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB and for the RK3399-Q7 can be updated.

Signed-off-by: Philipp Tomsich 

---

Changes in v2: None

 configs/evb-rk3399_defconfig| 2 ++
 configs/puma_defconfig  | 4 +++-
 include/configs/rk3399_common.h | 1 -
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 22405ce..7a82869 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -43,7 +43,9 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xFF1A
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/puma_defconfig b/configs/puma_defconfig
index 515185e..8e29d96 100644
--- a/configs/puma_defconfig
+++ b/configs/puma_defconfig
@@ -43,8 +43,10 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=115200
 CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xFF18
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index bc91eb6..c1ea616 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -12,7 +12,6 @@
 #define CONFIG_NR_DRAM_BANKS   1
 #define CONFIG_ENV_SIZE0x2000
 #define CONFIG_SYS_MAXARGS 16
-#define CONFIG_BAUDRATE150
 #define CONFIG_SYS_MALLOC_LEN  (32 << 20)
 #define CONFIG_SYS_CBSIZE  1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
-- 
1.9.1

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[U-Boot] [PATCH v2 0/2] rockchip: rk3399: spl: Make baudrate and UART configurable

[Philipp Tomsich]

The default configuration for debug output from the RK3399 SPL is
UART2 at 1.5MBaud. While this works reasonably well for the EVB,
custom boards may want to change these settings.

To simplify the enablement (i.e. to use the RS232 connector on our
baseboard and to improve the compatibility with commonly available
RS232-to-UART dongles) for the RK3399-Q7 SoM, we need to make both
the UART and the baudrate configurable.

This patch-series makes CONFIG_BAUDRATE a first-class citizen within
the Kconfig framework (so we can set it via defconfig) and adds the
required iomux support for UART0 in the RK3399 SPL.

Changes in v2:
- Changed hex constant to lowercase

Philipp Tomsich (2):
  rockchip: rk3399: spl: add UART0 support for SPL
  rockchip: config: rk3399: update defconfigs and rk3399_common

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h |  8 +++
 arch/arm/mach-rockchip/rk3399-board-spl.c   | 29 ++---
 configs/evb-rk3399_defconfig|  2 ++
 configs/puma_defconfig  |  4 +++-
 include/configs/rk3399_common.h |  1 -
 5 files changed, 34 insertions(+), 10 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH v2 1/2] rockchip: rk3399: spl: add UART0 support for SPL

[Philipp Tomsich]

The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).

To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.

As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.

Signed-off-by: Philipp Tomsich 
---

Changes in v2:
- Changed hex constant to lowercase

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h |  8 +++
 arch/arm/mach-rockchip/rk3399-board-spl.c   | 29 ++---
 2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 62d8496..4701cfb 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -333,6 +333,14 @@ enum {
GRF_GPIO2B4_SEL_MASK= 3 << GRF_GPIO2B4_SEL_SHIFT,
GRF_SPI2TPM_CSN0= 1,
 
+   /* GRF_GPIO2C_IOMUX */
+   GRF_GPIO2C0_SEL_SHIFT   = 0,
+   GRF_GPIO2C0_SEL_MASK= 3 << GRF_GPIO2C0_SEL_SHIFT,
+   GRF_UART0BT_SIN = 1,
+   GRF_GPIO2C1_SEL_SHIFT   = 2,
+   GRF_GPIO2C1_SEL_MASK= 3 << GRF_GPIO2C1_SEL_SHIFT,
+   GRF_UART0BT_SOUT= 1,
+
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A4_SEL_SHIFT   = 8,
GRF_GPIO3A4_SEL_MASK= 3 << GRF_GPIO3A4_SEL_SHIFT,
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c 
b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 7b4e0a1..c212143 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -57,19 +57,22 @@ void secure_timer_init(void)
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
 }
 
-#define GRF_EMMCCORE_CON11 0xff77f02c
-void board_init_f(ulong dummy)
+void board_debug_uart_init(void)
 {
-   struct udevice *pinctrl;
-   struct udevice *dev;
-   int ret;
-
-   /* Example code showing how to enable the debug UART on RK3288 */
 #include 
-   /* Enable early UART2 channel C on the RK3399 */
 #define GRF_BASE   0xff77
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
 
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff18)
+   /* Enable early UART0 on the RK3399 */
+   rk_clrsetreg(>gpio2c_iomux,
+GRF_GPIO2C0_SEL_MASK,
+GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+   rk_clrsetreg(>gpio2c_iomux,
+GRF_GPIO2C1_SEL_MASK,
+GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#else
+   /* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(>gpio4c_iomux,
 GRF_GPIO4C3_SEL_MASK,
 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
@@ -80,6 +83,16 @@ void board_init_f(ulong dummy)
rk_clrsetreg(>soc_con7,
 GRF_UART_DBG_SEL_MASK,
 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
+
+#define GRF_EMMCCORE_CON11 0xff77f02c
+void board_init_f(ulong dummy)
+{
+   struct udevice *pinctrl;
+   struct udevice *dev;
+   int ret;
+
 #define EARLY_UART
 #ifdef EARLY_UART
/*
-- 
1.9.1

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Re: [U-Boot] [ PATCH 2/2] net: move Broadcom SF2 driver to Kconfig

[Joe Hershberger]

On Thu, Mar 23, 2017 at 12:32 PM, Suji Velupillai
 wrote:
> Thank you Joe for your time and feedback,
> Please see the answers inline.
> Suji
>
>
> On Tue, Mar 21, 2017 at 11:53 AM, Joe Hershberger
>  wrote:
>>
>> On Fri, Mar 3, 2017 at 7:06 PM, Steve Rae  wrote:
>> > From: Suji Velupillai 
>> >
>> > move to Kconfig:
>> > CONFIG_BCM_SF2_ETH
>> > CONFIG_BCM_SF2_ETH_GMAC
>> >
>> > Also modified defconfigs of all platforms that use these configs.
>> >
>> > Signed-off-by: Suji Velupillai 
>> > Tested-by: Suji Velupillai 
>> > Reviewed-by: JD Zheng 
>> > Reviewed-by: Scott Branden 
>> > Signed-off-by: Steve Rae 
>> > ---
>> >
>> >  arch/arm/include/asm/arch-bcmcygnus/configs.h |  6 +-
>> >  configs/bcm28155_w1d_defconfig|  5 +++--
>> >  configs/bcm911360_entphn-ns_defconfig |  3 +++
>> >  configs/bcm911360_entphn_defconfig|  3 +++
>> >  configs/bcm911360k_defconfig  |  3 +++
>> >  configs/bcm958300k-ns_defconfig   |  3 +++
>> >  configs/bcm958300k_defconfig  |  3 +++
>> >  configs/bcm958305k_defconfig  |  3 +++
>> >  drivers/net/Kconfig   | 15 +++
>> >  scripts/config_whitelist.txt  |  2 --
>> >  10 files changed, 37 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h
>> > b/arch/arm/include/asm/arch-bcmcygnus/configs.h
>> > index af7f3bf..92b1c5e 100644
>> > --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
>> > +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
>> > @@ -1,5 +1,5 @@
>> >  /*
>> > - * Copyright 2014 Broadcom Corporation.
>> > + * Copyright 2014-2017 Broadcom.
>> >   *
>> >   * SPDX-License-Identifier:GPL-2.0+
>> >   */
>> > @@ -23,10 +23,6 @@
>> >  #define CONFIG_SYS_NS16550_COM30x18023000
>> >
>> >  /* Ethernet */
>> > -#define CONFIG_BCM_SF2_ETH
>> > -#define CONFIG_BCM_SF2_ETH_GMAC
>> > -
>> > -#define CONFIG_PHYLIB
>> >  #define CONFIG_PHY_BROADCOM
>> >  #define CONFIG_PHY_RESET_DELAY 1 /* PHY reset delay in us*/
>> >
>> > diff --git a/configs/bcm28155_w1d_defconfig
>> > b/configs/bcm28155_w1d_defconfig
>> > index aa5216e..4adbce6 100644
>> > --- a/configs/bcm28155_w1d_defconfig
>> > +++ b/configs/bcm28155_w1d_defconfig
>> > @@ -1,7 +1,6 @@
>> >  CONFIG_ARM=y
>> >  CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
>> >  CONFIG_TARGET_BCM28155_AP=y
>> > -CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
>> >  CONFIG_VERSION_VARIABLE=y
>> >  # CONFIG_DISPLAY_CPUINFO is not set
>> >  # CONFIG_DISPLAY_BOARDINFO is not set
>> > @@ -15,7 +14,6 @@ CONFIG_CMD_MMC=y
>> >  CONFIG_CMD_I2C=y
>> >  CONFIG_CMD_GPIO=y
>> >  # CONFIG_CMD_SETEXPR is not set
>> > -# CONFIG_CMD_NET is not set
>> >  # CONFIG_CMD_NFS is not set
>> >  CONFIG_CMD_CACHE=y
>> >  CONFIG_CMD_FAT=y
>> > @@ -33,3 +31,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
>> >  CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
>> >  CONFIG_G_DNL_VENDOR_NUM=0x18d1
>> >  CONFIG_G_DNL_PRODUCT_NUM=0x0d02
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm911360_entphn-ns_defconfig
>> > b/configs/bcm911360_entphn-ns_defconfig
>> > index adcc152..f1df78a 100644
>> > --- a/configs/bcm911360_entphn-ns_defconfig
>> > +++ b/configs/bcm911360_entphn-ns_defconfig
>> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
>> >  CONFIG_CMD_FAT=y
>> >  CONFIG_SYS_NS16550=y
>> >  CONFIG_OF_LIBFDT=y
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm911360_entphn_defconfig
>> > b/configs/bcm911360_entphn_defconfig
>> > index e49071d..22da69e 100644
>> > --- a/configs/bcm911360_entphn_defconfig
>> > +++ b/configs/bcm911360_entphn_defconfig
>> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
>> >  CONFIG_CMD_FAT=y
>> >  CONFIG_SYS_NS16550=y
>> >  CONFIG_OF_LIBFDT=y
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
>> > index 8077c4a..0281fc8 100644
>> > --- a/configs/bcm911360k_defconfig
>> > +++ b/configs/bcm911360k_defconfig
>> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
>> >  CONFIG_CMD_FAT=y
>> >  CONFIG_SYS_NS16550=y
>> >  CONFIG_OF_LIBFDT=y
>> > +CONFIG_NETDEVICES=y
>> > +CONFIG_BCM_SF2_ETH=y
>> > +CONFIG_BCM_SF2_ETH_GMAC=y
>> > diff --git a/configs/bcm958300k-ns_defconfig
>> > b/configs/bcm958300k-ns_defconfig
>> > index 26d0b0b..c837721 100644
>> > --- a/configs/bcm958300k-ns_defconfig
>> > +++ b/configs/bcm958300k-ns_defconfig
>> > @@ -19,3 +19,6 @@ CONFIG_CMD_TIME=y
>> >  CONFIG_CMD_FAT=y
>> >  CONFIG_SYS_NS16550=y
>> >  CONFIG_OF_LIBFDT=y
>> > +CONFIG_NETDEVICES=y
>> > 

Re: [U-Boot] uboot information

[Simon Glass]

Hi,

On 23 March 2017 at 12:36, Sébastien Basset  wrote:
>
>
>
> 2017-03-23 3:19 GMT+01:00 Simon Glass :
>>
>> Hi,
>>
>> On 22 March 2017 at 10:35, Sébastien Basset  wrote:
>> > 1/ No, As i am stuck on the mmc (pci controller internal soc),
>> > 2/ Now i try to boot on usb key, but i don't see controller usb
>> > Sorry, these are two different problems.
>>
>> It is better to post at the bottom that the top, for mailing lists.
>>
>> I think PCI XHCI has some problems. I'm not sure of its status.
>>
>> MMC seems to work well on Minnowboard Max (baytrail) but I am not sure
>> about braswell. Is it perhaps a slightly different chip?
>>
>> Regards,
>> Simon
>>
>
> For PCI XHCI, i see controller usb and root hub, but cannot reset port:
>
> portstatus 711, change 0, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> portstatus 711, change 10, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> portstatus 711, change 10, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> portstatus 711, change 10, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> portstatus 711, change 10, 5 Gb/s
> STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
> Cannot enable port 10 after 5 retries, disabling port.
> Maybe the USB cable is bad?
> cannot reset port 10!?
>
> do you have an idea,why reset port is break down ?

No I am not sure. It could possibly be a driver problem, or perhaps
the port is not enabled in the FSP config?

>
> For MMC, braswell n3160 is dedicated for embedded iot, maybe for security.
>

Do you mean that you cannot use MMC on this chip?

Regards,
Simon
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Re: [U-Boot] uboot information

[Sébastien Basset]

2017-03-23 3:19 GMT+01:00 Simon Glass :

> Hi,
>
> On 22 March 2017 at 10:35, Sébastien Basset  wrote:
> > 1/ No, As i am stuck on the mmc (pci controller internal soc),
> > 2/ Now i try to boot on usb key, but i don't see controller usb
> > Sorry, these are two different problems.
>
> It is better to post at the bottom that the top, for mailing lists.
>
> I think PCI XHCI has some problems. I'm not sure of its status.
>
> MMC seems to work well on Minnowboard Max (baytrail) but I am not sure
> about braswell. Is it perhaps a slightly different chip?
>
> Regards,
> Simon
>
>
For PCI XHCI, i see controller usb and root hub, but cannot reset port:

portstatus 711, change 0, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 711, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 711, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 711, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 711, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
Cannot enable port 10 after 5 retries, disabling port.
Maybe the USB cable is bad?
cannot reset port 10!?

do you have an idea,why reset port is break down ?

For MMC, braswell n3160 is dedicated for embedded iot, maybe for security.
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[U-Boot] [PATCH] Remove extra fdt_fixup_ethernet() call

[Joakim Tjernlund]

ft_cpu_setup() already calls fdt_fixup_ethernet(), calling it
in image_setup_libfdt() is both redundant and breaks any modifications
done by ft_board_setup(). Restore the old behavior by removing
the call in image_setup_libfdt()

Signed-off-by: Joakim Tjernlund 
---
 common/image-fdt.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/common/image-fdt.c b/common/image-fdt.c
index 80e3e63..b8f5654 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -498,7 +498,6 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
goto err;
}
}
-   fdt_fixup_ethernet(blob);
 
/* Delete the old LMB reservation */
lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,
-- 
2.10.2

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[U-Boot] [PATCH v2 40/45] net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID

[Stefan Roese]

Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should
be handled identical to PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 7b4f7a22bd..d20d82e017 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2895,6 +2895,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
val |= MVPP2_GMAC_INBAND_AN_MASK;
break;
case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_ID:
val |= MVPP2_GMAC_PORT_RGMII_MASK;
default:
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
-- 
2.12.1

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Re: [U-Boot] [PATCH v4 19/20] rockchip: rk3188: Add Radxa Rock board

[Heiko Stübner]

Hi Simon,

Am Donnerstag, 23. März 2017, 10:18:31 CET schrieb Simon Glass:
> On 21 February 2017 at 13:35, Simon Glass  wrote:
> > On 18 February 2017 at 11:46, Heiko Stuebner  wrote:
> >> The Rock is a RK3188 based single board computer by Radxa.
> >> Currently it still relies on the proprietary DDR init and
> >> cannot use the generic SPL, but at least is able to boot
> >> a linux kernel and system up to a regular login prompt.
> >> 
> >> Signed-off-by: Heiko Stuebner 
> >> Reviewed-by: Simon Glass 
> >> Tested-by: Kever Yang 
> >> ---
> >> 
> >>  arch/arm/dts/Makefile |   1 +
> >>  arch/arm/dts/rk3188-radxarock.dts | 382
> >>  ++
> >>  arch/arm/mach-rockchip/rk3188/Kconfig |  11 +
> >>  board/radxa/rock/Kconfig  |  15 ++
> >>  board/radxa/rock/MAINTAINERS  |   6 +
> >>  board/radxa/rock/Makefile |   7 +
> >>  board/radxa/rock/rock.c   |   7 +
> >>  configs/rock_defconfig|  56 +
> >>  include/configs/rock.h|  30 +++
> >>  9 files changed, 515 insertions(+)
> >>  create mode 100644 arch/arm/dts/rk3188-radxarock.dts
> >>  create mode 100644 board/radxa/rock/Kconfig
> >>  create mode 100644 board/radxa/rock/MAINTAINERS
> >>  create mode 100644 board/radxa/rock/Makefile
> >>  create mode 100644 board/radxa/rock/rock.c
> >>  create mode 100644 configs/rock_defconfig
> >>  create mode 100644 include/configs/rock.h
> > 
> > Applied to u-boot-rockchip, thanks!
> 
> Just a reminder that I had to drop this patch as it does not build.
> Can you please resend this one? I have also reverted the README patch
> but can apply that myself once this board is enabled.

ah, I should probably fold the patch fixing the build issue into this one. I'll 
create a new series and collect all the different sets flying around.


Heiko
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[U-Boot] [PATCH v2 36/45] net: mvpp2: Restructure probe / init functions

[Stefan Roese]

This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.

Signed-off-by: Stefan Roese 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 76 -
 1 file changed, 46 insertions(+), 30 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 4863336985..ecefa21097 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3830,19 +3830,14 @@ static int mvpp2_port_init(struct udevice *dev, struct 
mvpp2_port *port)
return 0;
 }
 
-/* Ports initialization */
-static int mvpp2_port_probe(struct udevice *dev,
-   struct mvpp2_port *port,
-   int port_node,
-   struct mvpp2 *priv)
+static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 {
+   int port_node = dev_of_offset(dev);
+   const char *phy_mode_str;
int phy_node;
u32 id;
u32 phyaddr;
-   const char *phy_mode_str;
int phy_mode = -1;
-   int priv_common_regs_num = 2;
-   int err;
 
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
if (phy_node < 0) {
@@ -3866,46 +3861,37 @@ static int mvpp2_port_probe(struct udevice *dev,
 
phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
 
-   port->priv = priv;
port->id = id;
-   if (priv->hw_version == MVPP21)
+   if (port->priv->hw_version == MVPP21)
port->first_rxq = port->id * rxq_number;
else
-   port->first_rxq = port->id * priv->max_port_rxqs;
+   port->first_rxq = port->id * port->priv->max_port_rxqs;
port->phy_node = phy_node;
port->phy_interface = phy_mode;
port->phyaddr = phyaddr;
 
-   if (priv->hw_version == MVPP21) {
-   port->base = (void __iomem *)dev_get_addr_index(
-   dev->parent, priv_common_regs_num + id);
-   if (IS_ERR(port->base))
-   return PTR_ERR(port->base);
-   } else {
-   u32 gop_id;
-
-   gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
-   "gop-port-id", -1);
-   if (id == -1) {
-   dev_err(>dev, "missing gop-port-id value\n");
-   return -EINVAL;
-   }
+   return 0;
+}
 
-   port->base = priv->iface_base + MVPP22_PORT_BASE +
-   gop_id * MVPP22_PORT_OFFSET;
-   }
+/* Ports initialization */
+static int mvpp2_port_probe(struct udevice *dev,
+   struct mvpp2_port *port,
+   int port_node,
+   struct mvpp2 *priv)
+{
+   int err;
 
port->tx_ring_size = MVPP2_MAX_TXD;
port->rx_ring_size = MVPP2_MAX_RXD;
 
err = mvpp2_port_init(dev, port);
if (err < 0) {
-   dev_err(>dev, "failed to init port %d\n", id);
+   dev_err(>dev, "failed to init port %d\n", port->id);
return err;
}
mvpp2_port_power_up(port);
 
-   priv->port_list[id] = port;
+   priv->port_list[port->id] = port;
return 0;
 }
 
@@ -4553,6 +4539,36 @@ static int mvpp2_probe(struct udevice *dev)
err = mvpp2_base_probe(dev->parent);
priv->probe_done = 1;
}
+
+   port->priv = dev_get_priv(dev->parent);
+
+   err = phy_info_parse(dev, port);
+   if (err)
+   return err;
+
+   /*
+* We need the port specific io base addresses at this stage, since
+* gop_port_init() accesses these registers
+*/
+   if (priv->hw_version == MVPP21) {
+   int priv_common_regs_num = 2;
+
+   port->base = (void __iomem *)dev_get_addr_index(
+   dev->parent, priv_common_regs_num + port->id);
+   if (IS_ERR(port->base))
+   return PTR_ERR(port->base);
+   } else {
+   port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "gop-port-id", -1);
+   if (port->id == -1) {
+   dev_err(>dev, "missing gop-port-id value\n");
+   return -EINVAL;
+   }
+
+   port->base = priv->iface_base + MVPP22_PORT_BASE +
+   port->gop_id * MVPP22_PORT_OFFSET;
+   }
+
/* Initialize network controller */
err = mvpp2_init(dev, priv);
if (err < 0) {
-- 
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[U-Boot] [PATCH v2 30/45] arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K

[Stefan Roese]

From: Thomas Petazzoni 

This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 arch/arm/dts/armada-7040-db.dts   | 25 +++
 arch/arm/dts/armada-8040-db.dts   | 16 +++
 arch/arm/dts/armada-cp110-master.dtsi | 37 +++
 arch/arm/dts/armada-cp110-slave.dtsi  | 37 +++
 4 files changed, 115 insertions(+)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 63442df8f3..776bc7831d 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -209,3 +209,28 @@
no-1-8-v;
non-removable;
 };
+
+_mdio {
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+   phy1: ethernet-phy@1 {
+   reg = <1>;
+   };
+};
+
+_ethernet {
+   status = "okay";
+};
+
+_eth1 {
+   status = "okay";
+   phy = <>;
+   phy-mode = "sgmii";
+};
+
+_eth2 {
+   status = "okay";
+   phy = <>;
+   phy-mode = "rgmii-id";
+};
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 40def9d6cd..f1f196f563 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -283,3 +283,19 @@
 _utmi0 {
status = "okay";
 };
+
+_mdio {
+   phy1: ethernet-phy@1 {
+   reg = <1>;
+   };
+};
+
+_ethernet {
+   status = "okay";
+};
+
+_eth2 {
+   status = "okay";
+   phy = <>;
+   phy-mode = "rgmii-id";
+};
diff --git a/arch/arm/dts/armada-cp110-master.dtsi 
b/arch/arm/dts/armada-cp110-master.dtsi
index 661a69679e..a450f3fd7c 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -61,6 +61,43 @@
interrupt-parent = <>;
ranges = <0x0 0x0 0xf200 0x200>;
 
+   cpm_ethernet: ethernet@0 {
+   compatible = "marvell,armada-7k-pp22";
+   reg = <0x0 0x10>, <0x129000 0xb000>;
+   clocks = <_syscon0 1 3>, <_syscon0 1 
9>, <_syscon0 1 5>;
+   clock-names = "pp_clk", "gop_clk", "mg_clk";
+   status = "disabled";
+   dma-coherent;
+
+   cpm_eth0: eth0 {
+   interrupts = ;
+   port-id = <0>;
+   gop-port-id = <0>;
+   status = "disabled";
+   };
+
+   cpm_eth1: eth1 {
+   interrupts = ;
+   port-id = <1>;
+   gop-port-id = <2>;
+   status = "disabled";
+   };
+
+   cpm_eth2: eth2 {
+   interrupts = ;
+   port-id = <2>;
+   gop-port-id = <3>;
+   status = "disabled";
+   };
+   };
+
+   cpm_mdio: mdio@12a200 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "marvell,orion-mdio";
+   reg = <0x12a200 0x10>;
+   };
+
cpm_syscon0: system-controller@44 {
compatible = "marvell,cp110-system-controller0",
 "syscon";
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi 
b/arch/arm/dts/armada-cp110-slave.dtsi
index 92ef55cf26..50898a8da6 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -61,6 +61,43 @@
interrupt-parent = <>;
ranges = <0x0 0x0 0xf400 0x200>;
 
+   cps_ethernet: ethernet@0 {
+   compatible = "marvell,armada-7k-pp22";
+   reg = <0x0 0x10>, <0x129000 0xb000>;
+   clocks = <_syscon0 1 3>, <_syscon0 1 
9>, <_syscon0 1 5>;
+   clock-names = "pp_clk", "gop_clk", "mg_clk";
+   status = "disabled";
+   dma-coherent;
+
+   

[U-Boot] [PATCH v2 42/45] net: mvpp2: Configure SMI PHY address needed for PHY polling

[Stefan Roese]

On PPv2.2 we enable PHY polling, so we also need to configure the PHY
address in the specific PHY address rgisters.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index cc6d42255c..086ce32851 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5338,6 +5338,14 @@ static void mvpp2_stop(struct udevice *dev)
mvpp2_cleanup_txqs(port);
 }
 
+static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
+{
+   writel(port->phyaddr, port->priv->iface_base +
+  MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
+
+   return 0;
+}
+
 static int mvpp2_base_probe(struct udevice *dev)
 {
struct mvpp2 *priv = dev_get_priv(dev);
@@ -5476,6 +5484,9 @@ static int mvpp2_probe(struct udevice *dev)
port->base = priv->iface_base + MVPP22_PORT_BASE +
port->gop_id * MVPP22_PORT_OFFSET;
 
+   /* Set phy address of the port */
+   mvpp22_smi_phy_addr_cfg(port);
+
/* GoP Init */
gop_port_init(port);
}
-- 
2.12.1

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[U-Boot] [PATCH v2 25/45] net: mvpp2: finally add the PPv2.2 compatible string

[Stefan Roese]

From: Thomas Petazzoni 

Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index c683fff53f..16da28de69 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4541,6 +4541,10 @@ static const struct udevice_id mvpp2_ids[] = {
.compatible = "marvell,armada-375-pp2",
.data = MVPP21,
},
+   {
+   .compatible = "marvell,armada-7k-pp22",
+   .data = MVPP22,
+   },
{ }
 };
 
-- 
2.12.1

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[U-Boot] [PATCH v2 33/45] net: mvpp2: Add remove function that is called before the OS is started

[Stefan Roese]

This patch adds a remove function to the mvpp2 ethernet driver which is
called before the OS is started, doing:

- Allocate the used buffers back from the buffer manager
- Stop the BM activity

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 2328c25850..e13a679e33 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2454,6 +2454,13 @@ static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
   struct mvpp2_bm_pool *bm_pool)
 {
+   int i;
+
+   for (i = 0; i < bm_pool->buf_num; i++) {
+   /* Allocate buffer back from the buffer manager */
+   mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
+   }
+
bm_pool->buf_num = 0;
 }
 
@@ -4495,6 +4502,21 @@ static int mvpp2_probe(struct udevice *dev)
return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
 }
 
+/*
+ * Empty BM pool and stop its activity before the OS is started
+ */
+static int mvpp2_remove(struct udevice *dev)
+{
+   struct mvpp2_port *port = dev_get_priv(dev);
+   struct mvpp2 *priv = port->priv;
+   int i;
+
+   for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
+   mvpp2_bm_pool_destroy(dev, priv, >bm_pools[i]);
+
+   return 0;
+}
+
 static const struct eth_ops mvpp2_ops = {
.start  = mvpp2_start,
.send   = mvpp2_send,
@@ -4506,9 +4528,11 @@ static struct driver mvpp2_driver = {
.name   = "mvpp2",
.id = UCLASS_ETH,
.probe  = mvpp2_probe,
+   .remove = mvpp2_remove,
.ops= _ops,
.priv_auto_alloc_size = sizeof(struct mvpp2_port),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+   .flags  = DM_FLAG_ACTIVE_DMA,
 };
 
 /*
-- 
2.12.1

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[U-Boot] [PATCH v2 43/45] net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool

[Stefan Roese]

As pointed out by Stefan Chulski, this variable is unused and should be
removed.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe
- Fixed small typo in commit text

 drivers/net/mvpp2.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 086ce32851..ec985977ba 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -1247,9 +1247,6 @@ struct mvpp2_bm_pool {
 
/* Ports using BM pool */
u32 port_map;
-
-   /* Occupied buffers indicator */
-   int in_use_thresh;
 };
 
 /* Static declaractions */
@@ -2801,7 +2798,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 
/* Update BM driver with number of buffers added to pool */
bm_pool->buf_num += i;
-   bm_pool->in_use_thresh = bm_pool->buf_num / 4;
 
return i;
 }
-- 
2.12.1

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[U-Boot] [PATCH v2 45/45] arm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfig

[Stefan Roese]

The Marvell PHY support is needed espescially for the A7040-DB with the
SGMII port (port 2). As without the marvell PHY driver configuration
for SGMII, ethernet won't work.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 configs/mvebu_db-88f7040_defconfig | 1 +
 configs/mvebu_db-88f8040_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/mvebu_db-88f7040_defconfig 
b/configs/mvebu_db-88f7040_defconfig
index fdafeb6607..797eabbfab 100644
--- a/configs/mvebu_db-88f7040_defconfig
+++ b/configs/mvebu_db-88f7040_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
 CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
diff --git a/configs/mvebu_db-88f8040_defconfig 
b/configs/mvebu_db-88f8040_defconfig
index 9866e19778..046da09786 100644
--- a/configs/mvebu_db-88f8040_defconfig
+++ b/configs/mvebu_db-88f8040_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
 CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
-- 
2.12.1

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[U-Boot] [PATCH v2 28/45] net: mvpp2.c: Clear all buffer / descriptor areas before usage

[Stefan Roese]

This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 06909e6a3c..b9e0fdcc82 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4429,6 +4429,9 @@ static int mvpp2_base_probe(struct udevice *dev)
size += RX_BUFFER_SIZE;
}
 
+   /* Clear the complete area so that all descriptors are cleared */
+   memset(bd_space, 0, size);
+
/* Save base addresses for later use */
priv->base = (void *)dev_get_addr_index(dev, 0);
if (IS_ERR(priv->base))
-- 
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[U-Boot] [PATCH v2 44/45] arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G

[Stefan Roese]

The default configuration for the COMPHY-0 port should be 1G, as its
used as 1G SGMII connection. This change is necessary to get the
MAC2 port (SGMII) working on this DB.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 arch/arm/dts/armada-7040-db.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 776bc7831d..84e0dbdc3d 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -159,7 +159,7 @@
 _comphy {
phy0 {
phy-type = ;
-   phy-speed = ;
+   phy-speed = ;
};
 
phy1 {
-- 
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[U-Boot] [PATCH v2 24/45] net: mvpp2: adapt rxq distribution to PPv2.2

[Stefan Roese]

From: Thomas Petazzoni 

In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.

In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from the range of 32 RXQs available for each port. So port 0 must
use RXQs in the range 0->31, port 1 in the range 32->63, etc.

This commit adapts the mvpp2 to this difference between PPv2.1 and
PPv2.2:

- The constant definition MVPP2_MAX_RXQ is replaced by a new field
  'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of
  RXQs per port. This field is initialized during ->probe() depending
  on the IP version.

- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total
  number of RXQs by multiplying the number of ports by the maximum of
  RXQs per port. This was anyway used in only one place.

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted
  to cope with the different allocation strategy between PPv2.1 and
  PPv2.2. Due to this change, the 'next_first_rxq' argument of this
  function is no longer needed and is removed.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
---

Changes in v2: None

 drivers/net/mvpp2.c | 33 ++---
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 16a9c75cf0..c683fff53f 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -454,9 +454,6 @@ do {
\
 /* Maximum number of TXQs used by single port */
 #define MVPP2_MAX_TXQ  8
 
-/* Maximum number of RXQs used by single port */
-#define MVPP2_MAX_RXQ  8
-
 /* Default number of TXQs in use */
 #define MVPP2_DEFAULT_TXQ  1
 
@@ -464,9 +461,6 @@ do {
\
 #define MVPP2_DEFAULT_RXQ  1
 #define CONFIG_MV_ETH_RXQ  8   /* increment by 8 */
 
-/* Total number of RXQs available to all ports */
-#define MVPP2_RXQ_TOTAL_NUM(MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
-
 /* Max number of Rx descriptors */
 #define MVPP2_MAX_RXD  16
 
@@ -772,6 +766,9 @@ struct mvpp2 {
/* HW version */
enum { MVPP21, MVPP22 } hw_version;
 
+   /* Maximum number of RXQs per port */
+   unsigned int max_port_rxqs;
+
struct mii_dev *bus;
 };
 
@@ -3700,7 +3697,8 @@ static int mvpp2_port_init(struct udevice *dev, struct 
mvpp2_port *port)
struct mvpp2_txq_pcpu *txq_pcpu;
int queue, cpu, err;
 
-   if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
+   if (port->first_rxq + rxq_number >
+   MVPP2_MAX_PORTS * priv->max_port_rxqs)
return -EINVAL;
 
/* Disable port */
@@ -3808,8 +3806,7 @@ static int mvpp2_port_init(struct udevice *dev, struct 
mvpp2_port *port)
 static int mvpp2_port_probe(struct udevice *dev,
struct mvpp2_port *port,
int port_node,
-   struct mvpp2 *priv,
-   int *next_first_rxq)
+   struct mvpp2 *priv)
 {
int phy_node;
u32 id;
@@ -3843,7 +3840,10 @@ static int mvpp2_port_probe(struct udevice *dev,
 
port->priv = priv;
port->id = id;
-   port->first_rxq = *next_first_rxq;
+   if (priv->hw_version == MVPP21)
+   port->first_rxq = port->id * rxq_number;
+   else
+   port->first_rxq = port->id * priv->max_port_rxqs;
port->phy_node = phy_node;
port->phy_interface = phy_mode;
port->phyaddr = phyaddr;
@@ -3877,8 +3877,6 @@ static int mvpp2_port_probe(struct udevice *dev,
}
mvpp2_port_power_up(port);
 
-   /* Increment the first Rx queue number to be used by the next port */
-   *next_first_rxq += CONFIG_MV_ETH_RXQ;
priv->port_list[id] = port;
return 0;
 }
@@ -3995,7 +3993,8 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
u32 val;
 
/* Checks for hardware constraints (U-Boot uses only one rxq) */
-   if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
+   if ((rxq_number > priv->max_port_rxqs) ||
+   (txq_number > MVPP2_MAX_TXQ)) {
dev_err(>dev, "invalid queue size parameter\n");
return -EINVAL;
}
@@ -4388,8 +4387,7 @@ static int mvpp2_probe(struct udevice *dev)
return err;
}
 
-   return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
-   _loc.first_rxq);
+   return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
 }
 
 static const struct eth_ops mvpp2_ops = {
@@ -4477,6 

[U-Boot] [PATCH v2 18/45] net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2

[Stefan Roese]

From: Thomas Petazzoni 

This commit modifies the mvpp2_defaults_set() function to not do the
loopback and FIFO threshold initialization, which are not needed for
PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e5b42b9e66..e75979b37a 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2755,16 +2755,18 @@ static void mvpp2_defaults_set(struct mvpp2_port *port)
 {
int tx_port_num, val, queue, ptxq, lrxq;
 
-   /* Configure port to loopback if needed */
-   if (port->flags & MVPP2_F_LOOPBACK)
-   mvpp2_port_loopback_set(port);
-
-   /* Update TX FIFO MIN Threshold */
-   val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
-   val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
-   /* Min. TX threshold must be less than minimal packet length */
-   val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
-   writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+   if (port->priv->hw_version == MVPP21) {
+   /* Configure port to loopback if needed */
+   if (port->flags & MVPP2_F_LOOPBACK)
+   mvpp2_port_loopback_set(port);
+
+   /* Update TX FIFO MIN Threshold */
+   val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+   val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+   /* Min. TX threshold must be less than minimal packet length */
+   val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
+   writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+   }
 
/* Disable Legacy WRR, Disable EJP, Release from reset */
tx_port_num = mvpp2_egress_port(port);
-- 
2.12.1

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[U-Boot] [PATCH v2 39/45] net: mvpp2: Add GoP and NetC support for port 0 (SFI)

[Stefan Roese]

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 161 
 1 file changed, 161 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 76370faff0..7b4f7a22bd 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3234,6 +3234,130 @@ static int gop_gpcs_reset(struct mvpp2_port *port, enum 
mv_reset act)
return 0;
 }
 
+/* Set the internal mux's to the required PCS in the PI */
+static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
+{
+   u32 val;
+   int lane;
+
+   switch (num_of_lanes) {
+   case 1:
+   lane = 0;
+   break;
+   case 2:
+   lane = 1;
+   break;
+   case 4:
+   lane = 2;
+   break;
+   default:
+   return -1;
+   }
+
+   /* configure XG MAC mode */
+   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+   val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+   val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
+   val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
+   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+   return 0;
+}
+
+static int gop_mpcs_mode(struct mvpp2_port *port)
+{
+   u32 val;
+
+   /* configure PCS40G COMMON CONTROL */
+   val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+   val &= ~FORWARD_ERROR_CORRECTION_MASK;
+   writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+
+   /* configure PCS CLOCK RESET */
+   val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+   val &= ~CLK_DIVISION_RATIO_MASK;
+   val |= 1 << CLK_DIVISION_RATIO_OFFS;
+   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+   val &= ~CLK_DIV_PHASE_SET_MASK;
+   val |= MAC_CLK_RESET_MASK;
+   val |= RX_SD_CLK_RESET_MASK;
+   val |= TX_SD_CLK_RESET_MASK;
+   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+   return 0;
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
+{
+   u32 val;
+
+   /* configure 10G MAC mode */
+   val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+   val |= MVPP22_XLG_RX_FC_EN;
+   writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+   val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+   val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+   val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
+   writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP22_XLG_CTRL4_REG);
+   val &= ~MVPP22_XLG_MODE_DMA_1G;
+   val |= MVPP22_XLG_FORWARD_PFC_EN;
+   val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
+   val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
+   writel(val, port->base + MVPP22_XLG_CTRL4_REG);
+
+   /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
+   val = readl(port->base + MVPP22_XLG_CTRL1_REG);
+   val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
+   val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
+   writel(val, port->base + MVPP22_XLG_CTRL1_REG);
+
+   /* unmask link change interrupt */
+   val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+   val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
+   val |= 1; /* unmask summary bit */
+   writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+
+   return 0;
+}
+
+/* Set PCS to reset or exit from reset */
+static int gop_xpcs_reset(struct mvpp2_port *port, enum mv_reset reset)
+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+   if (reset == RESET)
+   val &= ~MVPP22_XPCS_PCSRESET;
+   else
+   val |= MVPP22_XPCS_PCSRESET;
+   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+   return 0;
+}
+
+/* Set the MAC to reset or exit from reset */
+static int gop_xlg_mac_reset(struct mvpp2_port *port, enum mv_reset reset)
+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+   if (reset == RESET)
+   val &= ~MVPP22_XLG_MAC_RESETN;
+   else
+   val |= MVPP22_XLG_MAC_RESETN;
+   writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+   

[U-Boot] [PATCH v2 16/45] net: mvpp2: adjust the allocation/free of BM pools for PPv2.2

[Stefan Roese]

From: Thomas Petazzoni 

This commit adjusts the allocation and freeing of BM pools to support
PPv2.2. This involves:

- Checking that the number of buffer pointers is a multiple of 16, as
  required by the hardware.

- Adjusting the size of the DMA coherent area allocated for buffer
  pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per
  buffer, as opposed to 2 pointers of 32-bits per buffer in
  PPv2.1. The size in bytes is now stored in a new field of the
  mvpp2_bm_pool structure.

- On PPv2.2, getting the physical and virtual address of each buffer
  requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order
  bits of those addresses. A new utility function
  mvpp2_bm_bufs_get_addrs() is introduced to handle this.

- On PPv2.2, releasing a buffer requires writing the high order 32 bits
  of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no
  longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 39 ---
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 605c8bcd70..4f4e6749dc 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -251,14 +251,23 @@ do {  
\
 #define MVPP2_BM_PHY_ALLOC_REG(pool)   (0x6400 + ((pool) * 4))
 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK  BIT(0)
 #define MVPP2_BM_VIRT_ALLOC_REG0x6440
+#define MVPP2_BM_ADDR_HIGH_ALLOC   0x6444
+#define MVPP2_BM_ADDR_HIGH_PHYS_MASK   0xff
+#define MVPP2_BM_ADDR_HIGH_VIRT_MASK   0xff00
+#define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT  8
 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK  BIT(0)
 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK  BIT(1)
 #define MVPP2_BM_PHY_RLS_GRNTD_MASKBIT(2)
 #define MVPP2_BM_VIRT_RLS_REG  0x64c0
-#define MVPP2_BM_MC_RLS_REG0x64c4
+#define MVPP21_BM_MC_RLS_REG   0x64c4
 #define MVPP2_BM_MC_ID_MASK0xfff
 #define MVPP2_BM_FORCE_RELEASE_MASKBIT(12)
+#define MVPP22_BM_ADDR_HIGH_RLS_REG0x64c4
+#define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK  0xff
+#defineMVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK   0xff00
+#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
+#define MVPP22_BM_MC_RLS_REG   0x64d4
 
 /* TX Scheduler registers */
 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
@@ -2332,6 +2341,12 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 {
u32 val;
 
+   /* Number of buffer pointers must be a multiple of 16, as per
+* hardware constraints
+*/
+   if (!IS_ALIGNED(size, 16))
+   return -EINVAL;
+
bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
if (!bm_pool->virt_addr)
@@ -2345,7 +2360,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
}
 
mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
-   bm_pool->dma_addr);
+   lower_32_bits(bm_pool->dma_addr));
mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
@@ -2488,6 +2503,21 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port 
*port, int pool,
 dma_addr_t buf_dma_addr,
 unsigned long buf_phys_addr)
 {
+   if (port->priv->hw_version == MVPP22) {
+   u32 val = 0;
+
+   if (sizeof(dma_addr_t) == 8)
+   val |= upper_32_bits(buf_dma_addr) &
+   MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
+
+   if (sizeof(phys_addr_t) == 8)
+   val |= (upper_32_bits(buf_phys_addr)
+   << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
+   MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
+
+   mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
+   }
+
/* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
 * returned in the "cookie" field of the RX
 * descriptor. Instead of storing the virtual address, we
@@ -4237,7 +4267,10 @@ static int mvpp2_base_probe(struct udevice *dev)
for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
buffer_loc.bm_pool[i] =
(unsigned long *)((unsigned long)bd_space + size);
-   size += MVPP2_BM_POOL_SIZE_MAX 

[U-Boot] [PATCH v2 21/45] net: mvpp2: handle misc PPv2.1/PPv2.2 differences

[Stefan Roese]

From: Thomas Petazzoni 

This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).

Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot
version of this patch does not remove this function but simply adds the
check for MVPP21 before the mvpp2_port_fc_adv_enable() call.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 25 +++--
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 645a818df6..51922c06aa 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -342,6 +342,9 @@ do {
\
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
 
+#define MVPP22_SMI_MISC_CFG_REG0x1204
+#define  MVPP22_SMI_POLLING_EN BIT(10)
+
 #define MVPP22_PORT_BASE   0x30e00
 #define MVPP22_PORT_OFFSET 0x1000
 
@@ -3639,9 +3642,12 @@ static int mvpp2_open(struct udevice *dev, struct 
mvpp2_port *port)
 
 static void mvpp2_port_power_up(struct mvpp2_port *port)
 {
+   struct mvpp2 *priv = port->priv;
+
mvpp2_port_mii_set(port);
mvpp2_port_periodic_xon_disable(port);
-   mvpp2_port_fc_adv_enable(port);
+   if (priv->hw_version == MVPP21)
+   mvpp2_port_fc_adv_enable(port);
mvpp2_port_reset(port);
 }
 
@@ -3892,9 +3898,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
mvpp2_conf_mbus_windows(dram_target_info, priv);
 
/* Disable HW PHY polling */
-   val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
-   val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
-   writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+   if (priv->hw_version == MVPP21) {
+   val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+   val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
+   writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
+   } else {
+   val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
+   val &= ~MVPP22_SMI_POLLING_EN;
+   writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
+   }
 
/* Allocate and initialize aggregated TXQs */
priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
@@ -3920,8 +3932,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
CONFIG_MV_ETH_RXQ);
 
-   writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
-  priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
+   if (priv->hw_version == MVPP21)
+   writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
+  priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
 
/* Allow cache snoop when transmiting packets */
mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
-- 
2.12.1

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[U-Boot] [PATCH v2 38/45] net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

[Stefan Roese]

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 766 +++-
 1 file changed, 758 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 6f9a4137f8..76370faff0 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -355,6 +355,7 @@ do {
\
 /* Per-port registers */
 #define MVPP2_GMAC_CTRL_0_REG  0x0
 #define  MVPP2_GMAC_PORT_EN_MASK   BIT(0)
+#define  MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
 #define  MVPP2_GMAC_MAX_RX_SIZE_OFFS   2
 #define  MVPP2_GMAC_MAX_RX_SIZE_MASK   0x7ffc
 #define  MVPP2_GMAC_MIB_CNTR_EN_MASK   BIT(15)
@@ -366,29 +367,131 @@ do { 
\
 #define  MVPP2_GMAC_SA_LOW_OFFS7
 #define MVPP2_GMAC_CTRL_2_REG  0x8
 #define  MVPP2_GMAC_INBAND_AN_MASK BIT(0)
+#define  MVPP2_GMAC_SGMII_MODE_MASKBIT(0)
 #define  MVPP2_GMAC_PCS_ENABLE_MASKBIT(3)
 #define  MVPP2_GMAC_PORT_RGMII_MASKBIT(4)
+#define  MVPP2_GMAC_PORT_DIS_PADING_MASK   BIT(5)
 #define  MVPP2_GMAC_PORT_RESET_MASKBIT(6)
+#define  MVPP2_GMAC_CLK_125_BYPS_EN_MASK   BIT(9)
 #define MVPP2_GMAC_AUTONEG_CONFIG  0xc
 #define  MVPP2_GMAC_FORCE_LINK_DOWNBIT(0)
 #define  MVPP2_GMAC_FORCE_LINK_PASSBIT(1)
+#define  MVPP2_GMAC_EN_PCS_AN  BIT(2)
+#define  MVPP2_GMAC_AN_BYPASS_EN   BIT(3)
 #define  MVPP2_GMAC_CONFIG_MII_SPEED   BIT(5)
 #define  MVPP2_GMAC_CONFIG_GMII_SPEED  BIT(6)
 #define  MVPP2_GMAC_AN_SPEED_ENBIT(7)
 #define  MVPP2_GMAC_FC_ADV_EN  BIT(9)
+#define  MVPP2_GMAC_EN_FC_AN   BIT(11)
 #define  MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
 #define  MVPP2_GMAC_AN_DUPLEX_EN   BIT(13)
+#define  MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIGBIT(15)
 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS6
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK0x1fc0
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
+#define MVPP2_GMAC_CTRL_4_REG  0x90
+#define  MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASKBIT(0)
+#define  MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK  BIT(5)
+#define  MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
+#define  MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASKBIT(7)
 
-#define MVPP22_SMI_MISC_CFG_REG0x1204
+/*
+ * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
+ * relative to port->base.
+ */
+
+/* Port Mac Control0 */
+#define MVPP22_XLG_CTRL0_REG   0x100
+#define  MVPP22_XLG_PORT_ENBIT(0)
+#define  MVPP22_XLG_MAC_RESETN BIT(1)
+#define  MVPP22_XLG_RX_FC_EN   BIT(7)
+#define  MVPP22_XLG_MIBCNT_DIS BIT(13)
+/* Port Mac Control1 */
+#define MVPP22_XLG_CTRL1_REG   0x104
+#define  MVPP22_XLG_MAX_RX_SIZE_OFFS   0
+#define  MVPP22_XLG_MAX_RX_SIZE_MASK   0x1fff
+/* Port Interrupt Mask */
+#define MVPP22_XLG_INTERRUPT_MASK_REG  0x118
+#define  MVPP22_XLG_INTERRUPT_LINK_CHANGE  BIT(1)
+/* Port Mac Control3 */
+#define MVPP22_XLG_CTRL3_REG   0x11c
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_MASK   (7 << 13)
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_GMAC   (0 << 13)
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
+/* Port Mac Control4 */
+#define MVPP22_XLG_CTRL4_REG   0x184
+#define  MVPP22_XLG_FORWARD_802_3X_FC_EN   BIT(5)
+#define  MVPP22_XLG_FORWARD_PFC_EN BIT(6)
+#define  MVPP22_XLG_MODE_DMA_1GBIT(12)
+#define  MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
+
+/* XPCS registers */
+
+/* Global Configuration 0 */
+#define MVPP22_XPCS_GLOBAL_CFG_0_REG   0x0
+#define  MVPP22_XPCS_PCSRESET  BIT(0)
+#define  MVPP22_XPCS_PCSMODE_OFFS  3
+#define  MVPP22_XPCS_PCSMODE_MASK  (0x3 << \
+MVPP22_XPCS_PCSMODE_OFFS)
+#define  

[U-Boot] [PATCH v2 17/45] net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2

[Stefan Roese]

From: Thomas Petazzoni 

The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 19 ---
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 4f4e6749dc..e5b42b9e66 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -91,9 +91,11 @@ do { 
\
 #define MVPP2_SNOOP_PKT_SIZE_MASK  0x1ff
 #define MVPP2_SNOOP_BUF_HDR_MASK   BIT(9)
 #define MVPP2_RXQ_POOL_SHORT_OFFS  20
-#define MVPP2_RXQ_POOL_SHORT_MASK  0x70
+#define MVPP21_RXQ_POOL_SHORT_MASK 0x70
+#define MVPP22_RXQ_POOL_SHORT_MASK 0xf0
 #define MVPP2_RXQ_POOL_LONG_OFFS   24
-#define MVPP2_RXQ_POOL_LONG_MASK   0x700
+#define MVPP21_RXQ_POOL_LONG_MASK  0x700
+#define MVPP22_RXQ_POOL_LONG_MASK  0xf00
 #define MVPP2_RXQ_PACKET_OFFSET_OFFS   28
 #define MVPP2_RXQ_PACKET_OFFSET_MASK   0x7000
 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
@@ -2467,17 +2469,20 @@ static int mvpp2_bm_init(struct udevice *dev, struct 
mvpp2 *priv)
 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
int lrxq, int long_pool)
 {
-   u32 val;
+   u32 val, mask;
int prxq;
 
/* Get queue physical ID */
prxq = port->rxqs[lrxq]->id;
 
-   val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
-   val &= ~MVPP2_RXQ_POOL_LONG_MASK;
-   val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
-   MVPP2_RXQ_POOL_LONG_MASK);
+   if (port->priv->hw_version == MVPP21)
+   mask = MVPP21_RXQ_POOL_LONG_MASK;
+   else
+   mask = MVPP22_RXQ_POOL_LONG_MASK;
 
+   val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
+   val &= ~mask;
+   val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 }
 
-- 
2.12.1

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[U-Boot] [PATCH v2 03/45] net: mvpp2: simplify mvpp2_bm_bufs_add()

[Stefan Roese]

From: Thomas Petazzoni 

The mvpp2_bm_bufs_add() currently creates a fake cookie by calling
mvpp2_bm_cookie_pool_set(), just to be able to call
mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract
the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID.

Instead of doing this convoluted thing, just call mvpp2_bm_pool_put()
directly, since we have the BM pool ID.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 93eb1f2dd4..365180d456 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2390,7 +2390,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 struct mvpp2_bm_pool *bm_pool, int buf_num)
 {
int i;
-   u32 bm;
 
if (buf_num < 0 ||
(buf_num + bm_pool->buf_num > bm_pool->size)) {
@@ -2400,10 +2399,11 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
return 0;
}
 
-   bm = mvpp2_bm_cookie_pool_set(0, bm_pool->id);
for (i = 0; i < buf_num; i++) {
-   mvpp2_pool_refill(port, bm, (u32)buffer_loc.rx_buffer[i],
+   mvpp2_bm_pool_put(port, bm_pool->id,
+ (u32)buffer_loc.rx_buffer[i],
  (u32)buffer_loc.rx_buffer[i]);
+
}
 
/* Update BM driver with number of buffers added to pool */
-- 
2.12.1

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[U-Boot] [PATCH v2 22/45] net: mvpp2: add AXI bridge initialization for PPv2.2

[Stefan Roese]

From: Thomas Petazzoni 

The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 85 +
 1 file changed, 85 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 51922c06aa..b56af82f92 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -198,6 +198,34 @@ do {   
\
 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
 #define MVPP2_BASE_ADDR_ENABLE 0x4060
 
+/* AXI Bridge Registers */
+#define MVPP22_AXI_BM_WR_ATTR_REG  0x4100
+#define MVPP22_AXI_BM_RD_ATTR_REG  0x4104
+#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
+#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG   0x4114
+#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG   0x4118
+#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG   0x411c
+#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
+#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
+#define MVPP22_AXI_RD_NORMAL_CODE_REG  0x4150
+#define MVPP22_AXI_RD_SNOOP_CODE_REG   0x4154
+#define MVPP22_AXI_WR_NORMAL_CODE_REG  0x4160
+#define MVPP22_AXI_WR_SNOOP_CODE_REG   0x4164
+
+/* Values for AXI Bridge registers */
+#define MVPP22_AXI_ATTR_CACHE_OFFS 0
+#define MVPP22_AXI_ATTR_DOMAIN_OFFS12
+
+#define MVPP22_AXI_CODE_CACHE_OFFS 0
+#define MVPP22_AXI_CODE_DOMAIN_OFFS4
+
+#define MVPP22_AXI_CODE_CACHE_NON_CACHE0x3
+#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
+#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
+
+#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM   2
+#define MVPP22_AXI_CODE_DOMAIN_SYSTEM  3
+
 /* Interrupt Cause and Mask registers */
 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq)(0x5200 + 4 * (rxq))
 #define MVPP2_ISR_RXQ_GROUP_REG(rxq)   (0x5400 + 4 * (rxq))
@@ -3879,6 +3907,60 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
 }
 
+static void mvpp2_axi_init(struct mvpp2 *priv)
+{
+   u32 val, rdval, wrval;
+
+   mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
+
+   /* AXI Bridge Configuration */
+
+   rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
+   << MVPP22_AXI_ATTR_CACHE_OFFS;
+   rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+   << MVPP22_AXI_ATTR_DOMAIN_OFFS;
+
+   wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
+   << MVPP22_AXI_ATTR_CACHE_OFFS;
+   wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+   << MVPP22_AXI_ATTR_DOMAIN_OFFS;
+
+   /* BM */
+   mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
+   mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
+
+   /* Descriptors */
+   mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
+   mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
+   mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
+   mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
+
+   /* Buffer Data */
+   mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
+   mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
+
+   val = MVPP22_AXI_CODE_CACHE_NON_CACHE
+   << MVPP22_AXI_CODE_CACHE_OFFS;
+   val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
+   << MVPP22_AXI_CODE_DOMAIN_OFFS;
+   mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
+   mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
+
+   val = MVPP22_AXI_CODE_CACHE_RD_CACHE
+   << MVPP22_AXI_CODE_CACHE_OFFS;
+   val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+   << MVPP22_AXI_CODE_DOMAIN_OFFS;
+
+   mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
+
+   val = MVPP22_AXI_CODE_CACHE_WR_CACHE
+   << MVPP22_AXI_CODE_CACHE_OFFS;
+   val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
+   << MVPP22_AXI_CODE_DOMAIN_OFFS;
+
+   mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
+}
+
 /* Initialize network controller common part HW */
 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 {
@@ -3897,6 +3979,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
if (dram_target_info)
mvpp2_conf_mbus_windows(dram_target_info, priv);
 
+   if (priv->hw_version == MVPP22)
+   mvpp2_axi_init(priv);
+
/* Disable HW PHY polling */
if (priv->hw_version == MVPP21) {
val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
-- 
2.12.1

[U-Boot] [PATCH v2 13/45] net: mvpp2: add hw_version field in "struct mvpp2"

[Stefan Roese]

From: Thomas Petazzoni 

In preparation to the introduction for the support of PPv2.2 in the
mvpp2 driver, this commit adds a hw_version field to the struct
mvpp2, and uses the .data field of the DT match table to fill it in.

Having the MVPP21 and MVPP22 definitions available will allow to start
adding the necessary conditional code to support PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index d199eafe30..9683439d23 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -707,6 +707,9 @@ struct mvpp2 {
/* Tclk value */
u32 tclk;
 
+   /* HW version */
+   enum { MVPP21, MVPP22 } hw_version;
+
struct mii_dev *bus;
 };
 
@@ -4132,6 +4135,9 @@ static int mvpp2_base_probe(struct udevice *dev)
u32 size = 0;
int i;
 
+   /* Save hw-version */
+   priv->hw_version = dev_get_driver_data(dev);
+
/*
 * U-Boot special buffer handling:
 *
@@ -4234,7 +4240,10 @@ static int mvpp2_base_bind(struct udevice *parent)
 }
 
 static const struct udevice_id mvpp2_ids[] = {
-   { .compatible = "marvell,armada-375-pp2" },
+   {
+   .compatible = "marvell,armada-375-pp2",
+   .data = MVPP21,
+   },
{ }
 };
 
-- 
2.12.1

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[U-Boot] [PATCH v2 35/45] net: include/phy.h: Add new PHY interface modes

[Stefan Roese]

This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will
be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 include/phy.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/phy.h b/include/phy.h
index 5477496e0e..8e507cd7a6 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -61,6 +61,9 @@ typedef enum {
PHY_INTERFACE_MODE_RGMII_TXID,
PHY_INTERFACE_MODE_RTBI,
PHY_INTERFACE_MODE_XGMII,
+   PHY_INTERFACE_MODE_XAUI,
+   PHY_INTERFACE_MODE_RXAUI,
+   PHY_INTERFACE_MODE_SFI,
PHY_INTERFACE_MODE_NONE,/* Must be last */
 
PHY_INTERFACE_MODE_COUNT,
@@ -80,6 +83,9 @@ static const char *phy_interface_strings[] = {
[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
[PHY_INTERFACE_MODE_RTBI]   = "rtbi",
[PHY_INTERFACE_MODE_XGMII]  = "xgmii",
+   [PHY_INTERFACE_MODE_XAUI]   = "xaui",
+   [PHY_INTERFACE_MODE_RXAUI]  = "rxaui",
+   [PHY_INTERFACE_MODE_SFI]= "sfi",
[PHY_INTERFACE_MODE_NONE]   = "",
 };
 
-- 
2.12.1

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[U-Boot] [PATCH v2 20/45] net: mvpp2: handle register mapping and access for PPv2.2

[Stefan Roese]

From: Thomas Petazzoni 

This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.

Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:

- On PPv2.1, we had a first area for the common registers, and then one
  area per port.

- On PPv2.2, we have a first area for the common registers, and a
  second area for all the per-ports registers.

In addition, on PPv2.2, the area for the common registers is split into
so-called "address spaces" of 64 KB each. They allow to access the same
registers, but from different CPUs. Hence the introduction of cpu_base[]
in 'struct mvpp2', and the modification of the mvpp2_write() and
mvpp2_read() register accessors. For PPv2.1, the compatibility is
preserved by using an "address space" size of 0.

Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the
code, macros and variables introduced in the Linux patch version for this.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next,
  mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 46 +-
 1 file changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 5e888e7394..645a818df6 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -342,6 +342,9 @@ do {
\
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
 
+#define MVPP22_PORT_BASE   0x30e00
+#define MVPP22_PORT_OFFSET 0x1000
+
 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
 
 /* Descriptor ring Macros */
@@ -702,6 +705,7 @@ struct mvpp2 {
/* Shared registers' base addresses */
void __iomem *base;
void __iomem *lms_base;
+   void __iomem *iface_base;
 
/* List of pointers to port structures */
struct mvpp2_port **port_list;
@@ -736,6 +740,11 @@ struct mvpp2_pcpu_stats {
 struct mvpp2_port {
u8 id;
 
+   /* Index of the port from the "group of ports" complex point
+* of view
+*/
+   int gop_id;
+
int irq;
 
struct mvpp2 *priv;
@@ -3270,7 +3279,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
 
mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
-   MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
+   MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
 
/* WRR / EJP configuration - indirect access */
tx_port_num = mvpp2_egress_port(port);
@@ -3779,11 +3788,24 @@ static int mvpp2_port_probe(struct udevice *dev,
port->phy_interface = phy_mode;
port->phyaddr = phyaddr;
 
-   port->base = (void __iomem *)dev_get_addr_index(dev->parent,
-   priv_common_regs_num
-   + id);
-   if (IS_ERR(port->base))
-   return PTR_ERR(port->base);
+   if (priv->hw_version == MVPP21) {
+   port->base = (void __iomem *)dev_get_addr_index(
+   dev->parent, priv_common_regs_num + id);
+   if (IS_ERR(port->base))
+   return PTR_ERR(port->base);
+   } else {
+   u32 gop_id;
+
+   gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
+   "gop-port-id", -1);
+   if (id == -1) {
+   dev_err(>dev, "missing gop-port-id value\n");
+   return -EINVAL;
+   }
+
+   port->base = priv->iface_base + MVPP22_PORT_BASE +
+   gop_id * MVPP22_PORT_OFFSET;
+   }
 
port->tx_ring_size = MVPP2_MAX_TXD;
port->rx_ring_size = MVPP2_MAX_RXD;
@@ -4307,9 +4329,15 @@ static int mvpp2_base_probe(struct udevice *dev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
 
-   priv->lms_base = (void *)dev_get_addr_index(dev, 1);
-   if (IS_ERR(priv->lms_base))
-   return PTR_ERR(priv->lms_base);
+   if (priv->hw_version == MVPP21) {
+   priv->lms_base = (void *)dev_get_addr_index(dev, 1);
+   if (IS_ERR(priv->lms_base))
+   return PTR_ERR(priv->lms_base);
+   } else {
+   priv->iface_base = (void *)dev_get_addr_index(dev, 1);
+   if (IS_ERR(priv->iface_base))
+   return 

[U-Boot] [PATCH v2 01/45] bitops.h: Include bitsperlong.h as needed for GENMASK_ULL

[Stefan Roese]

The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is
defined in the bitsperlong.h header. Lets include this header as
the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver
uses this macro.

Signed-off-by: Stefan Roese 
Reviewed-by: Tom Rini 
Reviewed-by: Joe Hershberger 

---

Changes in v2:
- Added Reviewed-by from Tom and Joe

 include/linux/bitops.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 1b2e4915a0..576b15dc53 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -2,6 +2,7 @@
 #define _LINUX_BITOPS_H
 
 #include 
+#include 
 #include 
 
 #define BIT(nr)(1UL << (nr))
-- 
2.12.1

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Re: [U-Boot] [PATCH v4 19/20] rockchip: rk3188: Add Radxa Rock board

[Simon Glass]

Hi Heiko,

On 21 February 2017 at 13:35, Simon Glass  wrote:
> On 18 February 2017 at 11:46, Heiko Stuebner  wrote:
>> The Rock is a RK3188 based single board computer by Radxa.
>> Currently it still relies on the proprietary DDR init and
>> cannot use the generic SPL, but at least is able to boot
>> a linux kernel and system up to a regular login prompt.
>>
>> Signed-off-by: Heiko Stuebner 
>> Reviewed-by: Simon Glass 
>> Tested-by: Kever Yang 
>> ---
>>  arch/arm/dts/Makefile |   1 +
>>  arch/arm/dts/rk3188-radxarock.dts | 382 
>> ++
>>  arch/arm/mach-rockchip/rk3188/Kconfig |  11 +
>>  board/radxa/rock/Kconfig  |  15 ++
>>  board/radxa/rock/MAINTAINERS  |   6 +
>>  board/radxa/rock/Makefile |   7 +
>>  board/radxa/rock/rock.c   |   7 +
>>  configs/rock_defconfig|  56 +
>>  include/configs/rock.h|  30 +++
>>  9 files changed, 515 insertions(+)
>>  create mode 100644 arch/arm/dts/rk3188-radxarock.dts
>>  create mode 100644 board/radxa/rock/Kconfig
>>  create mode 100644 board/radxa/rock/MAINTAINERS
>>  create mode 100644 board/radxa/rock/Makefile
>>  create mode 100644 board/radxa/rock/rock.c
>>  create mode 100644 configs/rock_defconfig
>>  create mode 100644 include/configs/rock.h
>
> Applied to u-boot-rockchip, thanks!

Just a reminder that I had to drop this patch as it does not build.
Can you please resend this one? I have also reverted the README patch
but can apply that myself once this board is enabled.

Regards,
Simon
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[U-Boot] [PATCH v2 05/45] net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT

[Stefan Roese]

From: Thomas Petazzoni 

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 42df1b7e02..74ae1a2d2a 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -295,7 +295,7 @@ do {
\
 #define MVPP2_PHY_AN_CFG0_REG  0x34
 #define MVPP2_PHY_AN_STOP_SMI0_MASKBIT(7)
 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
-#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT  0x27
+#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT  0x27
 
 /* Per-port registers */
 #define MVPP2_GMAC_CTRL_0_REG  0x0
-- 
2.12.1

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[U-Boot] [PATCH v2 07/45] net: mvpp2: enable building on 64-bit platforms

[Stefan Roese]

From: Thomas Petazzoni 

The mvpp2 is going to be extended to support the Marvell Armada 7K/8K
platform, which is ARM64. As a preparation to this work, this commit
enables building the mvpp2 driver on ARM64, by:

 - Adjusting the Kconfig dependency

 - Fixing the types used in the driver so that they are 32/64-bits
   compliant. We use dma_addr_t for DMA addresses, and unsigned long
   for virtual addresses.

It is worth mentioning that after this commit, the driver is for now
still only used on 32-bits platforms, and will only work on 32-bits
platforms.

Changed by Stefan for U-Boot:
Removed the Kconfig change as it does not apply to U-Boot this way.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 769680ac45..d5085909e4 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2219,7 +2219,8 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
if (!bm_pool->virt_addr)
return -ENOMEM;
 
-   if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) {
+   if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
+   MVPP2_BM_POOL_PTR_ALIGN)) {
dev_err(>dev, "BM pool %d is not %d bytes aligned\n",
bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
return -ENOMEM;
@@ -2359,14 +2360,15 @@ static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, 
int pool)
 }
 
 /* Get pool number from a BM cookie */
-static inline int mvpp2_bm_cookie_pool_get(u32 cookie)
+static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
 {
return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
 }
 
 /* Release buffer to BM */
 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
-u32 buf_phys_addr, u32 buf_virt_addr)
+dma_addr_t buf_phys_addr,
+unsigned long buf_virt_addr)
 {
mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
@@ -2397,8 +2399,8 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 
for (i = 0; i < buf_num; i++) {
mvpp2_bm_pool_put(port, bm_pool->id,
- (u32)buffer_loc.rx_buffer[i],
- (u32)buffer_loc.rx_buffer[i]);
+ (dma_addr_t)buffer_loc.rx_buffer[i],
+ (unsigned long)buffer_loc.rx_buffer[i]);
 
}
 
@@ -,7 +3335,7 @@ static int mvpp2_rx_refill(struct mvpp2_port *port,
   struct mvpp2_bm_pool *bm_pool,
   u32 bm, u32 phys_addr)
 {
-   mvpp2_pool_refill(port, bm, phys_addr, phys_addr);
+   mvpp2_pool_refill(port, bm, phys_addr, (unsigned long)phys_addr);
return 0;
 }
 
-- 
2.12.1

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[U-Boot] [PATCH v2 27/45] net: mvpp2: Move probe function from MISC to ETH DM driver

[Stefan Roese]

This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_register().

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 80 -
 1 file changed, 43 insertions(+), 37 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 8751ee85e3..06909e6a3c 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -773,6 +773,8 @@ struct mvpp2 {
unsigned int max_port_rxqs;
 
struct mii_dev *bus;
+
+   int probe_done;
 };
 
 struct mvpp2_pcpu_stats {
@@ -4377,42 +4379,6 @@ static void mvpp2_stop(struct udevice *dev)
mvpp2_cleanup_txqs(port);
 }
 
-static int mvpp2_probe(struct udevice *dev)
-{
-   struct mvpp2_port *port = dev_get_priv(dev);
-   struct mvpp2 *priv = dev_get_priv(dev->parent);
-   int err;
-
-   /* Initialize network controller */
-   err = mvpp2_init(dev, priv);
-   if (err < 0) {
-   dev_err(>dev, "failed to initialize controller\n");
-   return err;
-   }
-
-   return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
-}
-
-static const struct eth_ops mvpp2_ops = {
-   .start  = mvpp2_start,
-   .send   = mvpp2_send,
-   .recv   = mvpp2_recv,
-   .stop   = mvpp2_stop,
-};
-
-static struct driver mvpp2_driver = {
-   .name   = "mvpp2",
-   .id = UCLASS_ETH,
-   .probe  = mvpp2_probe,
-   .ops= _ops,
-   .priv_auto_alloc_size = sizeof(struct mvpp2_port),
-   .platdata_auto_alloc_size = sizeof(struct eth_pdata),
-};
-
-/*
- * Use a MISC device to bind the n instances (child nodes) of the
- * network base controller in UCLASS_ETH.
- */
 static int mvpp2_base_probe(struct udevice *dev)
 {
struct mvpp2 *priv = dev_get_priv(dev);
@@ -4503,6 +4469,47 @@ static int mvpp2_base_probe(struct udevice *dev)
return mdio_register(bus);
 }
 
+static int mvpp2_probe(struct udevice *dev)
+{
+   struct mvpp2_port *port = dev_get_priv(dev);
+   struct mvpp2 *priv = dev_get_priv(dev->parent);
+   int err;
+
+   /* Only call the probe function for the parent once */
+   if (!priv->probe_done) {
+   err = mvpp2_base_probe(dev->parent);
+   priv->probe_done = 1;
+   }
+   /* Initialize network controller */
+   err = mvpp2_init(dev, priv);
+   if (err < 0) {
+   dev_err(>dev, "failed to initialize controller\n");
+   return err;
+   }
+
+   return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
+}
+
+static const struct eth_ops mvpp2_ops = {
+   .start  = mvpp2_start,
+   .send   = mvpp2_send,
+   .recv   = mvpp2_recv,
+   .stop   = mvpp2_stop,
+};
+
+static struct driver mvpp2_driver = {
+   .name   = "mvpp2",
+   .id = UCLASS_ETH,
+   .probe  = mvpp2_probe,
+   .ops= _ops,
+   .priv_auto_alloc_size = sizeof(struct mvpp2_port),
+   .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+/*
+ * Use a MISC device to bind the n instances (child nodes) of the
+ * network base controller in UCLASS_ETH.
+ */
 static int mvpp2_base_bind(struct udevice *parent)
 {
const void *blob = gd->fdt_blob;
@@ -4560,6 +4567,5 @@ U_BOOT_DRIVER(mvpp2_base) = {
.id = UCLASS_MISC,
.of_match = mvpp2_ids,
.bind   = mvpp2_base_bind,
-   .probe  = mvpp2_base_probe,
.priv_auto_alloc_size = sizeof(struct mvpp2),
 };
-- 
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[U-Boot] [PATCH v2 04/45] net: mvpp2: remove unused register definitions

[Stefan Roese]

From: Thomas Petazzoni 

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 365180d456..42df1b7e02 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -294,10 +294,6 @@ do {   
\
 #define MVPP2_SRC_ADDR_HIGH0x28
 #define MVPP2_PHY_AN_CFG0_REG  0x34
 #define MVPP2_PHY_AN_STOP_SMI0_MASKBIT(7)
-#define MVPP2_MIB_COUNTERS_BASE(port)  (0x1000 + ((port) >> 1) * \
-   0x400 + (port) * 0x400)
-#define MVPP2_MIB_LATE_COLLISION   0x7c
-#define MVPP2_ISR_SUM_MASK_REG 0x220c
 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT  0x27
 
-- 
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[U-Boot] [PATCH v2 29/45] net: mvpp2: Enable compilation for Armada 7K/8K platforms

[Stefan Roese]

Since Armada 7K/8K is also equipped with a newer version of the MVPP2
ethernet controller, lets enable compilation of this driver for these
platforms.

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 70e36611ea..8aa92790f4 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -124,12 +124,12 @@ config FEC_MXC
  NXP i.MX processors.
 
 config MVPP2
-   bool "Marvell Armada 375 network interface support"
-   depends on ARMADA_375
+   bool "Marvell Armada 375/7K/8K network interface support"
+   depends on ARMADA_375 || ARMADA_8K
select PHYLIB
help
  This driver supports the network interface units in the
- Marvell ARMADA 375 SoC.
+ Marvell ARMADA 375, 7K and 8K SoCs.
 
 config MACB
bool "Cadence MACB/GEM Ethernet Interface"
-- 
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[U-Boot] [PATCH v2 31/45] arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver

[Stefan Roese]

Since we've now integrated the A7k/8k support in the mvpp2 ethernet
driver, lets enable the support for both Marvell developments boards.

Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 configs/mvebu_db-88f7040_defconfig | 2 +-
 configs/mvebu_db-88f8040_defconfig | 2 +-
 include/configs/mvebu_armada-8k.h  | 8 
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/configs/mvebu_db-88f7040_defconfig 
b/configs/mvebu_db-88f7040_defconfig
index f20158a117..fdafeb6607 100644
--- a/configs/mvebu_db-88f7040_defconfig
+++ b/configs/mvebu_db-88f7040_defconfig
@@ -47,7 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
diff --git a/configs/mvebu_db-88f8040_defconfig 
b/configs/mvebu_db-88f8040_defconfig
index 3611b845fe..9866e19778 100644
--- a/configs/mvebu_db-88f8040_defconfig
+++ b/configs/mvebu_db-88f8040_defconfig
@@ -47,7 +47,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
+CONFIG_MVPP2=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCIE_DW_MVEBU=y
diff --git a/include/configs/mvebu_armada-8k.h 
b/include/configs/mvebu_armada-8k.h
index a8a9d15b5e..8ee5f27a97 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -81,6 +81,14 @@
 #define CONFIG_ENV_SIZE(64 << 10) /* 64KiB */
 #define CONFIG_ENV_SECT_SIZE   (64 << 10) /* 64KiB sectors */
 
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_ENV_OVERWRITE   /* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE/* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
+
 /* USB 2.0 */
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 
-- 
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[U-Boot] [PATCH v2 19/45] net: mvpp2: adjust mvpp2_{rxq, txq}_init for PPv2.2

[Stefan Roese]

From: Thomas Petazzoni 

In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 26 +-
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e75979b37a..5e888e7394 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -143,6 +143,7 @@ do {
\
 /* Descriptor Manager Top Registers */
 #define MVPP2_RXQ_NUM_REG  0x2040
 #define MVPP2_RXQ_DESC_ADDR_REG0x2044
+#define MVPP22_DESC_ADDR_OFFS  8
 #define MVPP2_RXQ_DESC_SIZE_REG0x2048
 #define MVPP2_RXQ_DESC_SIZE_MASK   0x3ff0
 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq)   (0x3000 + 4 * (rxq))
@@ -184,6 +185,7 @@ do {
\
 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
 #define MVPP2_TXQ_RSVD_CLR_OFFSET  16
 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu)  (0x2100 + 4 * (cpu))
+#define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu)  (0x2140 + 4 * (cpu))
 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK  0x3ff0
 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
@@ -3107,6 +3109,8 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
   int desc_num, int cpu,
   struct mvpp2 *priv)
 {
+   u32 txq_dma;
+
/* Allocate memory for TX descriptors */
aggr_txq->descs = buffer_loc.aggr_tx_descs;
aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
@@ -3123,10 +3127,16 @@ static int mvpp2_aggr_txq_init(struct udevice *dev,
aggr_txq->next_desc_to_proc = mvpp2_read(priv,
 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
 
-   /* Set Tx descriptors queue starting address */
-   /* indirect access */
-   mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
-   aggr_txq->descs_dma);
+   /* Set Tx descriptors queue starting address indirect
+* access
+*/
+   if (priv->hw_version == MVPP21)
+   txq_dma = aggr_txq->descs_dma;
+   else
+   txq_dma = aggr_txq->descs_dma >>
+   MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
+
+   mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
 
return 0;
@@ -3137,6 +3147,8 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
  struct mvpp2_rx_queue *rxq)
 
 {
+   u32 rxq_dma;
+
rxq->size = port->rx_ring_size;
 
/* Allocate memory for RX descriptors */
@@ -3155,7 +3167,11 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
 
/* Set Rx descriptors queue starting address - indirect access */
mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
-   mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma);
+   if (port->priv->hw_version == MVPP21)
+   rxq_dma = rxq->descs_dma;
+   else
+   rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
+   mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
 
-- 
2.12.1

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[U-Boot] [PATCH v2 41/45] net: mvpp2: Enable PHY polling mode on PPv2.2

[Stefan Roese]

Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index d20d82e017..cc6d42255c 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4966,14 +4966,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
if (priv->hw_version == MVPP22)
mvpp2_axi_init(priv);
 
-   /* Disable HW PHY polling */
if (priv->hw_version == MVPP21) {
+   /* Disable HW PHY polling */
val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
} else {
+   /* Enable HW PHY polling */
val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
-   val &= ~MVPP22_SMI_POLLING_EN;
+   val |= MVPP22_SMI_POLLING_EN;
writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
}
 
-- 
2.12.1

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[U-Boot] [PATCH v2 14/45] net: mvpp2: introduce an intermediate union for the TX/RX descriptors

[Stefan Roese]

From: Thomas Petazzoni 

Since the format of the HW descriptors is different between PPv2.1 and
PPv2.2, this commit introduces an intermediate union, with for now
only the PPv2.1 descriptors. The bulk of the driver code only
manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the
descriptors can only be accessed and modified through the accessor
functions. A follow-up commit will add the descriptor definitions for
PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 39 ---
 1 file changed, 28 insertions(+), 11 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 9683439d23..f063b04e43 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -797,7 +797,8 @@ struct mvpp2_port {
 #define MVPP2_RXD_L3_IP6   BIT(30)
 #define MVPP2_RXD_BUF_HDR  BIT(31)
 
-struct mvpp2_tx_desc {
+/* HW TX descriptor for PPv2.1 */
+struct mvpp21_tx_desc {
u32 command;/* Options used by HW for packet transmitting.*/
u8  packet_offset;  /* the offset from the buffer beginning */
u8  phys_txq;   /* destination queue ID */
@@ -808,7 +809,8 @@ struct mvpp2_tx_desc {
u32 reserved2;  /* reserved (for future use)*/
 };
 
-struct mvpp2_rx_desc {
+/* HW RX descriptor for PPv2.1 */
+struct mvpp21_rx_desc {
u32 status; /* info about received packet   */
u16 reserved1;  /* parser_info (for future use, PnC)*/
u16 data_size;  /* size of received packet in bytes */
@@ -823,6 +825,21 @@ struct mvpp2_rx_desc {
u32 reserved8;
 };
 
+/* Opaque type used by the driver to manipulate the HW TX and RX
+ * descriptors
+ */
+struct mvpp2_tx_desc {
+   union {
+   struct mvpp21_tx_desc pp21;
+   };
+};
+
+struct mvpp2_rx_desc {
+   union {
+   struct mvpp21_rx_desc pp21;
+   };
+};
+
 /* Per-CPU Tx queue control */
 struct mvpp2_txq_pcpu {
int cpu;
@@ -1023,59 +1040,59 @@ static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port 
*port,
  struct mvpp2_tx_desc *tx_desc,
  dma_addr_t dma_addr)
 {
-   tx_desc->buf_dma_addr = dma_addr;
+   tx_desc->pp21.buf_dma_addr = dma_addr;
 }
 
 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
  struct mvpp2_tx_desc *tx_desc,
  size_t size)
 {
-   tx_desc->data_size = size;
+   tx_desc->pp21.data_size = size;
 }
 
 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 struct mvpp2_tx_desc *tx_desc,
 unsigned int txq)
 {
-   tx_desc->phys_txq = txq;
+   tx_desc->pp21.phys_txq = txq;
 }
 
 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 struct mvpp2_tx_desc *tx_desc,
 unsigned int command)
 {
-   tx_desc->command = command;
+   tx_desc->pp21.command = command;
 }
 
 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
struct mvpp2_tx_desc *tx_desc,
unsigned int offset)
 {
-   tx_desc->packet_offset = offset;
+   tx_desc->pp21.packet_offset = offset;
 }
 
 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->buf_dma_addr;
+   return rx_desc->pp21.buf_dma_addr;
 }
 
 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->buf_cookie;
+   return rx_desc->pp21.buf_cookie;
 }
 
 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->data_size;
+   return rx_desc->pp21.data_size;
 }
 
 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
   struct mvpp2_rx_desc *rx_desc)
 {
-   return rx_desc->status;
+   return rx_desc->pp21.status;
 }
 
 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
-- 
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[U-Boot] [PATCH v2 23/45] net: mvpp2: rework RXQ interrupt group initialization for PPv2.2

[Stefan Roese]

From: Thomas Petazzoni 

This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe
- Rebased on latest patchset version from Thomas available in net-next,
  mostly smaller changes, making checkpatch happy.

 drivers/net/mvpp2.c | 50 +-
 1 file changed, 45 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index b56af82f92..16a9c75cf0 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -228,7 +228,21 @@ do {   
\
 
 /* Interrupt Cause and Mask registers */
 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq)(0x5200 + 4 * (rxq))
-#define MVPP2_ISR_RXQ_GROUP_REG(rxq)   (0x5400 + 4 * (rxq))
+#define MVPP21_ISR_RXQ_GROUP_REG(rxq)  (0x5400 + 4 * (rxq))
+
+#define MVPP22_ISR_RXQ_GROUP_INDEX_REG  0x5400
+#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
+
+#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
+#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
+
+#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
+#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK0x1f
+#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK  0xf00
+#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET8
+
 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
 #define MVPP2_ISR_ENABLE_INTERRUPT(mask)   ((mask) & 0x)
 #define MVPP2_ISR_DISABLE_INTERRUPT(mask)  (((mask) << 16) & 0x)
@@ -3747,7 +3761,19 @@ static int mvpp2_port_init(struct udevice *dev, struct 
mvpp2_port *port)
}
 
/* Configure Rx queue group interrupt for this port */
-   mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
+   if (priv->hw_version == MVPP21) {
+   mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
+   CONFIG_MV_ETH_RXQ);
+   } else {
+   u32 val;
+
+   val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
+   mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
+
+   val = (CONFIG_MV_ETH_RXQ <<
+  MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
+   mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
+   }
 
/* Create Rx descriptor rings */
for (queue = 0; queue < rxq_number; queue++) {
@@ -4013,9 +4039,23 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 
*priv)
mvpp2_rx_fifo_init(priv);
 
/* Reset Rx queue group interrupt configuration */
-   for (i = 0; i < MVPP2_MAX_PORTS; i++)
-   mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
-   CONFIG_MV_ETH_RXQ);
+   for (i = 0; i < MVPP2_MAX_PORTS; i++) {
+   if (priv->hw_version == MVPP21) {
+   mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
+   CONFIG_MV_ETH_RXQ);
+   continue;
+   } else {
+   u32 val;
+
+   val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
+   mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
+
+   val = (CONFIG_MV_ETH_RXQ <<
+  MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
+   mvpp2_write(priv,
+   MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
+   }
+   }
 
if (priv->hw_version == MVPP21)
writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
-- 
2.12.1

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[U-Boot] [PATCH v2 06/45] net: mvpp2: simplify MVPP2_PRS_RI_* definitions

[Stefan Roese]

From: Thomas Petazzoni 

Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which
doesn't compile nicely on 64-bit. Moreover, those definitions are in
fact unneeded, since they are always used in combination with a bit
mask that ensures only the appropriate bits are modified.

Therefore, such definitions should just be set to 0x0. In addition, as
suggested by Russell King, we change the _MASK definitions to also use
the BIT() macro so that it is clear they are related to the values
defined afterwards.

For example:

 #define MVPP2_PRS_RI_L2_CAST_MASK  0x600
 #define MVPP2_PRS_RI_L2_UCAST  ~(BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_MCAST  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST  BIT(10)

becomes

 #define MVPP2_PRS_RI_L2_CAST_MASK  (BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_UCAST  0x0
 #define MVPP2_PRS_RI_L2_MCAST  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST  BIT(10)

Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and
MVPP2_PRS_RI_L2_BCAST) are always applied with
MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for
MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)).

It fixes the following warnings when building the driver on a 64-bit
platform (which is not possible as of this commit, but will be enabled
in a follow-up commit):

drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’:
drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly 
truncated to unsigned type [-Woverflow]
 #define MVPP2_PRS_RI_L2_UCAST   ~(BIT(9) | BIT(10))
  ^
drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro 
‘MVPP2_PRS_RI_L2_UCAST’
 mvpp2_prs_sram_ri_update(, MVPP2_PRS_RI_L2_UCAST,

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 74ae1a2d2a..769680ac45 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -572,28 +572,28 @@ enum mvpp2_tag_type {
 /* Sram result info bits assignment */
 #define MVPP2_PRS_RI_MAC_ME_MASK   0x1
 #define MVPP2_PRS_RI_DSA_MASK  0x2
-#define MVPP2_PRS_RI_VLAN_MASK 0xc
-#define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_NONE 0x0
 #define MVPP2_PRS_RI_VLAN_SINGLE   BIT(2)
 #define MVPP2_PRS_RI_VLAN_DOUBLE   BIT(3)
 #define MVPP2_PRS_RI_VLAN_TRIPLE   (BIT(2) | BIT(3))
 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC  BIT(4)
-#define MVPP2_PRS_RI_L2_CAST_MASK  0x600
-#define MVPP2_PRS_RI_L2_UCAST  ~(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_CAST_MASK  (BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_UCAST  0x0
 #define MVPP2_PRS_RI_L2_MCAST  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST  BIT(10)
 #define MVPP2_PRS_RI_PPPOE_MASK0x800
-#define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000
-#define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_UN 0x0
 #define MVPP2_PRS_RI_L3_IP4BIT(12)
 #define MVPP2_PRS_RI_L3_IP4_OPTBIT(13)
 #define MVPP2_PRS_RI_L3_IP4_OTHER  (BIT(12) | BIT(13))
 #define MVPP2_PRS_RI_L3_IP6BIT(14)
 #define MVPP2_PRS_RI_L3_IP6_EXT(BIT(12) | BIT(14))
 #define MVPP2_PRS_RI_L3_ARP(BIT(13) | BIT(14))
-#define MVPP2_PRS_RI_L3_ADDR_MASK  0x18000
-#define MVPP2_PRS_RI_L3_UCAST  ~(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_ADDR_MASK  (BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_UCAST  0x0
 #define MVPP2_PRS_RI_L3_MCAST  BIT(15)
 #define MVPP2_PRS_RI_L3_BCAST  (BIT(15) | BIT(16))
 #define MVPP2_PRS_RI_IP_FRAG_MASK  0x2
-- 
2.12.1

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[U-Boot] [PATCH v2 12/45] net: mvpp2: add and use accessors for TX/RX descriptors

[Stefan Roese]

From: Thomas Petazzoni 

The PPv2.2 IP has a different TX and RX descriptor layout compared to
PPv2.1. In order to prepare for the introduction of PPv2.2 support in
mvpp2, this commit adds accessors for the different fields of the TX
and RX descriptors, and changes the code to use them.

For now, the mvpp2_port argument passed to the accessors is not used,
but it will be used in follow-up to update the descriptor according to
the version of the IP being used.

Apart from the mechanical changes to use the newly introduced
accessors, a few other changes, needed to use the accessors, are made:

- The mvpp2_txq_inc_put() function now takes a mvpp2_port as first
  argument, as it is needed to use the accessors.

- Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first
  argument, for the same reason.

- In mvpp2_rx_error(), instead of accessing the RX descriptor in each
  case of the switch, we introduce a local variable to store the
  packet size.

- Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie"
  variable to store the RX descriptor cookie, rather than accessing
  it from the descriptor each time.

- In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the
  packet size from the TX descriptor, we use the actual value
  available in the function, which is used to set the TX descriptor
  packet size a few lines before.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stefan Roese 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 118 +---
 1 file changed, 93 insertions(+), 25 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 17ce0e9f7d..d199eafe30 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -1016,6 +1016,65 @@ static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
return readl(priv->base + offset);
 }
 
+static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
+ struct mvpp2_tx_desc *tx_desc,
+ dma_addr_t dma_addr)
+{
+   tx_desc->buf_dma_addr = dma_addr;
+}
+
+static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
+ struct mvpp2_tx_desc *tx_desc,
+ size_t size)
+{
+   tx_desc->data_size = size;
+}
+
+static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
+struct mvpp2_tx_desc *tx_desc,
+unsigned int txq)
+{
+   tx_desc->phys_txq = txq;
+}
+
+static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
+struct mvpp2_tx_desc *tx_desc,
+unsigned int command)
+{
+   tx_desc->command = command;
+}
+
+static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
+   struct mvpp2_tx_desc *tx_desc,
+   unsigned int offset)
+{
+   tx_desc->packet_offset = offset;
+}
+
+static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
+   struct mvpp2_rx_desc *rx_desc)
+{
+   return rx_desc->buf_dma_addr;
+}
+
+static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
+struct mvpp2_rx_desc *rx_desc)
+{
+   return rx_desc->buf_cookie;
+}
+
+static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
+   struct mvpp2_rx_desc *rx_desc)
+{
+   return rx_desc->data_size;
+}
+
+static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
+  struct mvpp2_rx_desc *rx_desc)
+{
+   return rx_desc->status;
+}
+
 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 {
txq_pcpu->txq_get_index++;
@@ -2779,11 +2838,15 @@ static void mvpp2_rxq_offset_set(struct mvpp2_port 
*port,
 }
 
 /* Obtain BM cookie information from descriptor */
-static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
+static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
+struct mvpp2_rx_desc *rx_desc)
 {
-   int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
-  MVPP2_RXD_BM_POOL_ID_OFFS;
int cpu = smp_processor_id();
+   int pool;
+
+   pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
+   MVPP2_RXD_BM_POOL_ID_MASK) >>
+   MVPP2_RXD_BM_POOL_ID_OFFS;
 
return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
   ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
@@ -3005,10 +3068,11 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
 
for (i = 0; i < rx_received; i++) {
struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
-   u32 bm = 

[U-Boot] [PATCH v2 34/45] net: mvpp2: Add RX and TX FIFO configuration for PPv2.2

[Stefan Roese]

This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
driver. The RX FIFO packet data size is changed to the recommended
FIFO sizes. The TX FIFO configuration is newly added.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
---

Changes in v2: None

 drivers/net/mvpp2.c | 75 -
 1 file changed, 68 insertions(+), 7 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e13a679e33..4863336985 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -482,9 +482,23 @@ do {   
\
 #define MVPP2_TX_DESC_ALIGN(MVPP2_DESC_ALIGNED_SIZE - 1)
 
 /* RX FIFO constants */
-#define MVPP2_RX_FIFO_PORT_DATA_SIZE   0x2000
-#define MVPP2_RX_FIFO_PORT_ATTR_SIZE   0x80
-#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
+#define MVPP21_RX_FIFO_PORT_DATA_SIZE  0x2000
+#define MVPP21_RX_FIFO_PORT_ATTR_SIZE  0x80
+#define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
+#define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE0x2000
+#define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE  0x1000
+#define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
+#define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE0x80
+#define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE  0x40
+#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
+
+/* TX general registers */
+#define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port)   (0x8860 + ((eth_tx_port) << 2))
+#define MVPP22_TX_FIFO_SIZE_MASK   0xf
+
+/* TX FIFO constants */
+#define MVPP2_TX_FIFO_DATA_SIZE_10KB   0xa
+#define MVPP2_TX_FIFO_DATA_SIZE_3KB0x3
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
@@ -3934,10 +3948,35 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
int port;
 
for (port = 0; port < MVPP2_MAX_PORTS; port++) {
-   mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
-   MVPP2_RX_FIFO_PORT_DATA_SIZE);
-   mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
-   MVPP2_RX_FIFO_PORT_ATTR_SIZE);
+   if (priv->hw_version == MVPP22) {
+   if (port == 0) {
+   mvpp2_write(priv,
+   MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+   MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
+   mvpp2_write(priv,
+   MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+   MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
+   } else if (port == 1) {
+   mvpp2_write(priv,
+   MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+   
MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
+   mvpp2_write(priv,
+   MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+   
MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
+   } else {
+   mvpp2_write(priv,
+   MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+   MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
+   mvpp2_write(priv,
+   MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+   MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
+   }
+   } else {
+   mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
+   MVPP21_RX_FIFO_PORT_DATA_SIZE);
+   mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
+   MVPP21_RX_FIFO_PORT_ATTR_SIZE);
+   }
}
 
mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
@@ -3945,6 +3984,24 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
 }
 
+/* Initialize Tx FIFO's */
+static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
+{
+   int port, val;
+
+   for (port = 0; port < MVPP2_MAX_PORTS; port++) {
+   /* Port 0 supports 10KB TX FIFO */
+   if (port == 0) {
+   val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
+   MVPP22_TX_FIFO_SIZE_MASK;
+   } else {
+   val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
+   MVPP22_TX_FIFO_SIZE_MASK;
+   }
+   mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
+   }
+}
+
 static void mvpp2_axi_init(struct mvpp2 *priv)
 {
u32 val, rdval, wrval;
@@ -4051,6 +4108,10 @@ static int mvpp2_init(struct udevice *dev, 

[U-Boot] [PATCH v2 32/45] net: mvpp2: Handle eth device naming in multi-CP case correctly

[Stefan Roese]

Currently, the naming of the ethernet ports is not handled correctly in
the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP
also instantiates an ethernet controller with the same device ID's.
This patch now takes this into account and adds the required base-id
so that the slave-CP ethernet devices will be named "mvpp2-3 ...".

This patch also updates my Copyright notice to include 2017 as well.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Acked-by: Joe Hershberger 

---

Changes in v2:
- Added Acked-by from Joe

 drivers/net/mvpp2.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index b9e0fdcc82..2328c25850 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -6,7 +6,7 @@
  * Marcin Wojtas 
  *
  * U-Boot version:
- * Copyright (C) 2016 Stefan Roese 
+ * Copyright (C) 2016-2017 Stefan Roese 
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -1090,6 +1090,8 @@ static int rxq_number = MVPP2_DEFAULT_RXQ;
 /* Number of TXQs used by single port */
 static int txq_number = MVPP2_DEFAULT_TXQ;
 
+static int base_id;
+
 #define MVPP2_DRIVER_NAME "mvpp2"
 #define MVPP2_DRIVER_VERSION "1.0"
 
@@ -4523,6 +4525,7 @@ static int mvpp2_base_bind(struct udevice *parent)
char *name;
int subnode;
u32 id;
+   int base_id_add;
 
/* Lookup eth driver */
drv = lists_uclass_lookup(UCLASS_ETH);
@@ -4531,7 +4534,12 @@ static int mvpp2_base_bind(struct udevice *parent)
return -ENOENT;
}
 
+   base_id_add = base_id;
+
fdt_for_each_subnode(subnode, blob, node) {
+   /* Increment base_id for all subnodes, also the disabled ones */
+   base_id++;
+
/* Skip disabled ports */
if (!fdtdec_get_is_enabled(blob, subnode))
continue;
@@ -4541,6 +4549,7 @@ static int mvpp2_base_bind(struct udevice *parent)
return -ENOMEM;
 
id = fdtdec_get_int(blob, subnode, "port-id", -1);
+   id += base_id_add;
 
name = calloc(1, 16);
sprintf(name, "mvpp2-%d", id);
-- 
2.12.1

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