Hello,
Miquel Raynal wrote on Fri, 7 Dec 2018
11:06:24 +0100:
> Hi Stefan,
>
> Stefan Agner wrote on Thu, 6 Dec 2018 14:57:09 +0100:
>
> > From: Stefan Agner
> >
> > Each ECC layout consumes about 2984 bytes in the .data section. Allow
> > to disable the default ECC layouts if a driver is
Hello Marek,
On Fri, 2018-12-07 at 12:48 +0100, Marek Vasut wrote:
> On 12/07/2018 10:19 AM, Harald Seiler wrote:
> > Currently, U-Boot ignores the BBT stored in the last 4 blocks of NAND
> > flash because the NAND_BBT_USE_FLASH flag is not set. This leads to
> > two issues:
> >
> > * U-Boot
The implementation of the EEPROM commands does not support the DM I2C API.
Prevent compilation breakage by not enabling it if the non-DM API is not
available (if DM_I2C is used without DM_I2C_COMPAT)
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes
On 06/12/2018 07:42, Maxime Ripard wrote:
Hi,
> On Thu, Dec 06, 2018 at 12:02:20AM +, Andre Przywara wrote:
>> Using memcpy() for MMIO operations is, however tempting, not a good
>> idea: It depends on the specific implementation of memcpy, also
>> lacks barriers. In this particular case the
On Fri, Dec 07, 2018 at 02:50:53PM +0100, Jean-Jacques Hiblot wrote:
> It is currently not possible to include the support to remove devices in
> the SPL. This is however needed by platforms that re-select their dtb after
> DM is initialized; they need to remove all the previously bound devices
>
If OF_CONTROL is not enabled and DM_SEQ_ALIAS is enabled, we must
assign an alias (requested sequence number) to devices that belongs to a
class with the DM_UC_FLAG_SEQ_ALIAS flag. Otherwise
uclass_find_device_by_seq() cannot be used to get/probe a device. In
particular i2c_get_chip_for_busnum()
Those platforms need CONFIG_SPL_DM_SEQ_ALIAS because they enable both
DM_I2C and SPL_DM. Without CONFIG_SPL_DM_SEQ_ALIAS, it is not possible to
get the I2C bus with i2c_get_chip_for_busnum().
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Felix Brack
Tested-by: Felix Brack
---
Changes in v3:
To reset the DM after a new dtb is loaded, we need to call dm_uninit()
and then dm_init(). This fails however because gd->dm_root is not nullified
by dm_uninit().
Fixing it by setting gd->dm_root in dm_uninit().
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Simon Glass
---
Changes in v3:
To enumerate devices on the /soc/ node, create a "simple-bus"
driver to match "riscv-virtio-soc".
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v2:
- add DM_FLAG_PRE_RELOC flag to the simple-bus driver
arch/riscv/cpu/qemu/cpu.c | 14 ++
1 file changed, 14
At present the trap handler returns to M-mode only. Change to
returning to previous privilege level instead.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v2: None
arch/riscv/cpu/mtrap.S | 8
1 file changed, 8 deletions(-)
diff --git a/arch/riscv/cpu/mtrap.S
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option.
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/riscv/cpu/ax25/Kconfig | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/cpu/ax25/Kconfig
Increase the heap size for the pre-relocation stage, so that CPU
driver can be loaded.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v2: None
arch/riscv/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index
Add the QEMU RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v2:
- add CMD_CPU as well
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/qemu/Kconfig| 11 +++
On Fri, Dec 07, 2018 at 02:50:51PM +0100, Jean-Jacques Hiblot wrote:
> This is required to take advantage of MULTI_DTB_FIT before relocation.
> If it is too low, DM will be initialized only after relocation has
> taken place. That is too late for the DRA7 because I2C DM is used before
> the
If DM_I2C is used , the I2C controllers must be registered as U_BOOT_DEVICE
because OF_CONTROL is not used in the SPL.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-omap2/am33xx/board.c | 15 +++
1 file changed, 15 insertions(+)
diff
In some cases it may be useful to be able to change the fdt we have been
using and use another one instead. For example, the TI platforms uses an
EEPROM to store board information and, based on the type of board,
different dtbs are used by the SPL. When DM_I2C is used, a first dtb must
be used
From: Andreas Dannenberg
The EEPROM reading in the board detection code is done through legacy
I2C functions which on platforms using DM_I2C this functionality is
provided via the CONFIG_DM_I2C_COMPAT layer. To allow newer platforms
to use the board detection code without relying on
This series remove the usage of the DM_I2C_COMPAT option for all the ti
platforms. It also takes this opportunity to not disable DM_I2C in the SPL.
There are a couples of issues to fix:
- CMD_EEPROM does not support the DM API. Fixed by removing this option
when DM_I2C is used without
This is required to take advantage of MULTI_DTB_FIT before relocation.
If it is too low, DM will be initialized only after relocation has
taken place. That is too late for the DRA7 because I2C DM is used before
the relocation to setup the voltages required, among other things, to
properly
The standard RISC-V ISA sets aside a 12-bit encoding space for up
to 4096 CSRs. This adds all known CSR numbers as defined in the
RISC-V Privileged Architecture Version 1.10.
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/riscv/include/asm/encoding.h | 219
This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.
This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as
With this change, we can avoid a forward declaration.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v2:
- rebase on u-boot/master
- drop the patch "riscv: Pass correct exception code to _exit_trap()"
- drop the patch "riscv: Refactor handle_trap() a little for future
On Fri, Dec 07, 2018 at 02:50:44PM +0100, Jean-Jacques Hiblot wrote:
> Signed-off-by: Jean-Jacques Hiblot
> Reviewed-by: Simon Glass
Reviewed-by: Tom Rini
--
Tom
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On Fri, Dec 07, 2018 at 02:50:40PM +0100, Jean-Jacques Hiblot wrote:
> Those platforms need CONFIG_SPL_DM_SEQ_ALIAS because they enable both
> DM_I2C and SPL_DM. Without CONFIG_SPL_DM_SEQ_ALIAS, it is not possible to
> get the I2C bus with i2c_get_chip_for_busnum().
>
> Signed-off-by:
Hi Tom, Wolfgang,
Tom Rini wrote on Thu, 6 Dec 2018 10:59:25 -0500:
> On Thu, Dec 06, 2018 at 04:23:00PM +0100, Miquel Raynal wrote:
> > Hi Wolfgang,
> >
> > Wolfgang Denk wrote on Thu, 06 Dec 2018 10:32:14 +0100:
> >
> > > Dear Boris,
> > >
> > > In message
On 12/07/2018 01:15 PM, Harald Seiler wrote:
> Hello Marek,
Hi,
> On Fri, 2018-12-07 at 12:48 +0100, Marek Vasut wrote:
>> On 12/07/2018 10:19 AM, Harald Seiler wrote:
>>> Currently, U-Boot ignores the BBT stored in the last 4 blocks of NAND
>>> flash because the NAND_BBT_USE_FLASH flag is not
For getting the I2C0 bus working in u-boot, the used PINS had to be
enabled in the board.c.
In the nanopi_neo2_defconfig you have to set the CONFIG_I2C0_ENABLE=y.
Best regards
Ronny Lubke
-
Engineer
Metirionic GmbH
Strehlener Straße 12 - 14
01069 Dresden
Card detection is not working properly because fsl_esdhc_get_cd() always
returns true since commit 653282b5672c ("dm: mmc: fsl_esdhc: Update to
support MMC operations"). This patch fixes it.
Signed-off-by: Yuichiro Goto
---
drivers/mmc/fsl_esdhc.c | 1 -
1 file changed, 1 deletion(-)
diff
On Fri, Dec 7, 2018 at 11:54 AM Marek Vasut wrote:
>
> On 12/07/2018 09:56 AM, Alex Kiernan wrote:
> [...]
> > +++ b/drivers/usb/musb-new/musb_uboot.c
> > @@ -214,7 +214,7 @@ int musb_lowlevel_init(struct musb_host_data *host)
> > {
> > void *mbase;
> > /* USB spec says it may take
On 12/07/2018 01:29 PM, Alex Kiernan wrote:
> On Fri, Dec 7, 2018 at 11:54 AM Marek Vasut wrote:
>>
>> On 12/07/2018 09:56 AM, Alex Kiernan wrote:
>> [...]
>>> +++ b/drivers/usb/musb-new/musb_uboot.c
>>> @@ -214,7 +214,7 @@ int musb_lowlevel_init(struct musb_host_data *host)
>>> {
>>> void
On Fri, 7 Dec 2018 at 07:56, Takahiro Akashi wrote:
>
> # My patch is more or less a RFC to raise attention.
>
> On Wed, Dec 05, 2018 at 11:53:42AM +0530, Sumit Garg wrote:
> > Hi Akashi,
> >
> > On Wed, 28 Nov 2018 at 11:28, AKASHI Takahiro
> > wrote:
> > >
> > > As the subject suggested, this
Those driver are not DM drivers per se (not using the PMIC/regulator
framework) and are using the legacy I2C API. Make them compatible with
the DM_I2C API.
This impacts the following drivers:
- palmas (used by am57xx/dra7xx evms)
- tps65218 (used by am43xx evms)
- tps65217 and tps65910 (used by
RISC-V privileged architecture v1.10 defines a real-time counter,
exposed as a memory-mapped machine-mode register - mtime. mtime must
run at constant frequency, and the platform must provide a mechanism
for determining the timebase of mtime. The mtime register has a
64-bit precision on all RV32,
From: Anup Patel
This adds an implementation of riscv_get_time() API that is using
rdtime instruction.
This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.
Signed-off-by: Anup Patel
Signed-off-by: Bin Meng
---
Changes in v2:
- incorporated and
On Fri, Dec 07, 2018 at 02:24:22PM +0100, Philipp Tomsich wrote:
> Kever,
>
> > On 07.12.2018, at 02:39, Kever Yang wrote:
> >
> > Hi Philipp,
> >
> > On 12/06/2018 09:50 PM, Philipp Tomsich wrote:
> >> +Tom
> >>
> >>> On 05.12.2018, at 03:25, Kever Yang wrote:
> >>>
> >>> The U-Boot eMMC
On Fri, Dec 07, 2018 at 02:50:42PM +0100, Jean-Jacques Hiblot wrote:
> This allows the driver to be used without OF_CONTROL.
> AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in
> SPL thus requires that the omap I2C can be passed platdata.
>
> Signed-off-by: Jean-Jacques
On Fri, Dec 07, 2018 at 02:50:45PM +0100, Jean-Jacques Hiblot wrote:
> In order to use DM_I2C, we need to move the board detection after the
> early SPL initialization.
>
> Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
--
Tom
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On Fri, Dec 07, 2018 at 02:50:55PM +0100, Jean-Jacques Hiblot wrote:
> The DRA7 platforms requires that the dtb used in the SPL really matches the
> platform to have the best MMC performances.
> To detect the board type/version an I2C EEPROM is read. This requires that
> DM is initialized before
Kever,
> On 07.12.2018, at 02:39, Kever Yang wrote:
>
> Hi Philipp,
>
> On 12/06/2018 09:50 PM, Philipp Tomsich wrote:
>> +Tom
>>
>>> On 05.12.2018, at 03:25, Kever Yang wrote:
>>>
>>> The U-Boot eMMC does not need to care about the power for Rockchip
>>> SoC, because if the board is using
There is no need for an embedded device tree for this board so let the
build process generate a separate u-boot.dtb file instead.
Signed-off-by: Felix Brack
---
arch/arm/mach-omap2/am33xx/Kconfig | 1 +
configs/am335x_pdu001_defconfig| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
On Fri, Dec 07, 2018 at 12:09:33PM +0100, Miquel Raynal wrote:
> Hi Tom, Wolfgang,
[snip]
> So what's our next move? I think Wolfgang had two points:
> * NOR (and everything related to NOR) should not depend on MTD.
> * Same for NAND.
>
> For NAND this is already too late, NAND code already
On Fri, Dec 07, 2018 at 02:50:41PM +0100, Jean-Jacques Hiblot wrote:
> From: Vignesh R
>
> Move away from SoC specific headers to handle different register layout.
> Instead use driver data to get appropriate register layouts like in the
> kernel. While at it, perform some mostly cosmetic
Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v2: None
arch/riscv/cpu/Makefile | 2 +-
arch/riscv/cpu/mtrap.S | 111
Implement arch_cpu_init() to do some basic architecture level cpu
initialization, like FPU enable, etc.
Signed-off-by: Bin Meng
---
Changes in v2:
- use csr_set() to set MSTATUS_FS
- only enabling the cycle, time, and instret counters
- change to use satp
arch/riscv/cpu/cpu.c | 19
On 12/07/2018 10:19 AM, Harald Seiler wrote:
> Currently, U-Boot ignores the BBT stored in the last 4 blocks of NAND
> flash because the NAND_BBT_USE_FLASH flag is not set. This leads to
> two issues:
>
> * U-Boot silently uses a memory-only BBT which is initialized with all
> blocks marked as
On 12/07/2018 09:56 AM, Alex Kiernan wrote:
[...]
> +++ b/drivers/usb/musb-new/musb_uboot.c
> @@ -214,7 +214,7 @@ int musb_lowlevel_init(struct musb_host_data *host)
> {
> void *mbase;
> /* USB spec says it may take up to 1 second for a device to connect */
> - unsigned long
On Fri, Dec 07, 2018 at 02:35:23AM +0100, Marek Vasut wrote:
> On 12/06/2018 09:30 PM, Tom Rini wrote:
> > On Mon, Dec 03, 2018 at 11:12:54PM +0100, Marek Vasut wrote:
> >> Enable watchdog and bootcounter support on the M53Menlo board.
> >>
> >> Signed-off-by: Marek Vasut
> >> Cc: Stefano Babic
On Fri, Dec 7, 2018 at 12:30 PM Marek Vasut wrote:
>
> On 12/07/2018 01:29 PM, Alex Kiernan wrote:
> > On Fri, Dec 7, 2018 at 11:54 AM Marek Vasut wrote:
> >>
> >> On 12/07/2018 09:56 AM, Alex Kiernan wrote:
> >> [...]
> >>> +++ b/drivers/usb/musb-new/musb_uboot.c
> >>> @@ -214,7 +214,7 @@ int
This adds DM drivers to support RISC-V CPU and timer, plus some bug fixes.
This series is available at u-boot-x86/riscv-working for testing.
Changes in v2:
- Use 'Hz' instead of 'HZ'
- add DM_FLAG_PRE_RELOC flag to the simple-bus driver
- pass NULL as the timer device to
From: Anup Patel
So far we have a Kconfig option for supervisor mode. This adds an
option for the machine mode.
Signed-off-by: Anup Patel
Signed-off-by: Bin Meng
---
Changes in v2:
- incorporated and reworked Anup's S-mode timer patch
@ http://patchwork.ozlabs.org/patch/1006663/
From: Lukas Auer
RISC-V has two code models, medium low (medlow) and medium any (medany).
Medlow limits addressable memory to a single 2 GiB range between the
absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
to any single 2 GiB address range.
By default, medlow is selected
sp cannot be loaded before restoring other registers.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v2: None
arch/riscv/cpu/mtrap.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index a5ad558..da307e4
On Wed, Dec 05, 2018 at 06:42:52PM -0700, Simon Glass wrote:
> At present the 'Index' column assumes there is only one digit. But on some
> devices (e.g. snow) there are a lot of regulators and GPIO banks. Adjust
> the output to allow for two digits without messing up the display.
>
> Also
From: Vignesh R
Move away from SoC specific headers to handle different register layout.
Instead use driver data to get appropriate register layouts like in the
kernel. While at it, perform some mostly cosmetic alignment/cleanup in
the functions being updated.
Signed-off-by: Vignesh R
i2c_get_chip_for_busnum() really should check the presence of the chip on
the bus. Most of the users of this function assume that this is done.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v3:
- removed commit introducing dm_i2c_probe_device(). Instead probe the
presence of the chip on
Hi Philipp,
On Thu, Dec 6, 2018 at 10:33 PM Philipp Tomsich
wrote:
>
>
>
> > On 13.11.2018, at 09:21, Bin Meng wrote:
> >
> > This adds U-Boot syscon driver for RISC-V Core Local Interruptor
> > (CLINT). The CLINT block holds memory-mapped control and status
> > registers associated with
Hi Lukas,
On Thu, Dec 6, 2018 at 8:30 PM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Thu, 2018-12-06 at 18:07 +0800, Bin Meng wrote:
> > Hi Lukas,
> >
> > On Thu, Dec 6, 2018 at 7:11 AM Auer, Lukas
> > wrote:
> > >
> > > Hi Bin,
> > >
> > > On Wed, 2018-12-05 at 17:59 +0800, Bin Meng wrote:
> > > >
With current csr_xxx ops, we cannot pass a macro to parameter
'csr', hence we need add another level to allow the parameter
to be a macro itself, aka indirect stringification.
Signed-off-by: Bin Meng
---
Changes in v2:
- new patch to add indirect stringification to csr_xxx ops
This calls cpu_probe_all() to probe all available cpus.
Signed-off-by: Bin Meng
Reviewed-by: Lukas Auer
---
Changes in v2:
- move to arch/riscv/cpu/cpu.c
arch/riscv/cpu/cpu.c| 14 ++
arch/riscv/cpu/qemu/Kconfig | 1 +
2 files changed, 15 insertions(+)
diff --git
On Fri, Dec 07, 2018 at 02:50:37PM +0100, Jean-Jacques Hiblot wrote:
> The implementation of the EEPROM commands does not support the DM I2C API.
> Prevent compilation breakage by not enabling it if the non-DM API is not
> available (if DM_I2C is used without DM_I2C_COMPAT)
>
> Signed-off-by:
This allows the driver to be used without OF_CONTROL.
AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in
SPL thus requires that the omap I2C can be passed platdata.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v3: None
Changes in v2: None
Remove the last call to the non-DM I2C API.
Also remove the #undef CONFIG_DM_I2C_COMPAT because it is not defined
in the common header file anymore.
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Felix Brack
Tested-by: Felix Brack
---
Changes in v3: None
Changes in v2:
- remove the
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. The goal is to eventually remove DM_I2C_COMPAT
when all I2C "clients" have been migrated to use the DM API.
This a step in that direction for the TI based platforms.
Build tested with buildman:
The DRA7 platforms requires that the dtb used in the SPL really matches the
platform to have the best MMC performances.
To detect the board type/version an I2C EEPROM is read. This requires that
DM is initialized before the detection. As a consequence we must reset the
DM after the board
Hi Lukas,
On Thu, Nov 15, 2018 at 5:57 AM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> > This adds a driver for RISC-V CPU. Note the driver will bind
> > a RISC-V timer driver if "timebase-frequency" property is
> > present in the device tree.
> >
> >
It is currently not possible to include the support to remove devices in
the SPL. This is however needed by platforms that re-select their dtb after
DM is initialized; they need to remove all the previously bound devices
before triggering a scan of the new DT.
Add a Kconfig option to be able to
In order to use DM_I2C, we need to move the board detection after the
early SPL initialization.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-omap2/am33xx/board.c | 9 ++---
arch/arm/mach-omap2/hwinit-common.c | 5 ++---
2 files changed, 8
am57xx configs uses DM_I2C both in SPL and u-boot.
Remove code for non-DM I2C support.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v3: None
Changes in v2: None
board/ti/am57xx/board.c | 36 +++-
1 file changed, 3 insertions(+), 33 deletions(-)
diff --git
On 06/12/2018 19:40, Adam Ford wrote:
On Tue, Nov 27, 2018 at 11:04 PM Heiko Schocher wrote:
Hello Adam,
Am 26.11.2018 um 20:18 schrieb Adam Ford:
On Sat, Oct 27, 2018 at 4:46 PM Adam Ford wrote:
On Mon, Oct 22, 2018 at 9:13 AM Jean-Jacques Hiblot wrote:
This series remove the usage of
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 4
arch/arm/dts/omap5-u-boot.dtsi | 4
2 files changed, 8 insertions(+)
diff --git a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
This adds a timebase_freq member to the 'struct cpu_platdata', to
hold the "timebase-frequency" value in the cpu or /cpus node.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
Reviewed-by: Lukas Auer
---
Changes in v2:
- Use 'Hz' instead of 'HZ'
include/cpu.h | 3 +++
1 file changed, 3
This adds a driver for RISC-V CPU. Note the driver will bind
a RISC-V timer driver if "timebase-frequency" property is
present in the device tree.
Signed-off-by: Bin Meng
---
Changes in v2:
- pass NULL as the timer device to device_bind_with_driver_data()
drivers/cpu/Kconfig | 6 +++
This adds all exception codes in encoding.h.
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/riscv/include/asm/encoding.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/include/asm/encoding.h
b/arch/riscv/include/asm/encoding.h
index c910d5c..e6d905a
On Fri, Dec 07, 2018 at 02:50:36PM +0100, Jean-Jacques Hiblot wrote:
> This series remove the usage of the DM_I2C_COMPAT option for all the ti
> platforms. It also takes this opportunity to not disable DM_I2C in the SPL.
>
> There are a couples of issues to fix:
> - CMD_EEPROM does not support
On Thu, Dec 6, 2018 at 2:11 PM Maxime Ripard wrote:
>
> On Thu, Dec 06, 2018 at 01:25:57AM +, Andre Przywara wrote:
> > Now that the Allwinner port in the official mainline ARM Trusted
> > Firmware repository has reached feature parity with the "legacy" ATF
> > port, let's use the opportunity
On Fri, Dec 07, 2018 at 02:50:49PM +0100, Jean-Jacques Hiblot wrote:
> DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
> API when DM_I2C is used. The goal is to eventually remove DM_I2C_COMPAT
> when all I2C "clients" have been migrated to use the DM API.
> This a step in
On Fri, Dec 07, 2018 at 02:50:50PM +0100, Jean-Jacques Hiblot wrote:
> am57xx configs uses DM_I2C both in SPL and u-boot.
> Remove code for non-DM I2C support.
>
> Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
--
Tom
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On 12/07/2018 01:59 PM, Alex Kiernan wrote:
> On Fri, Dec 7, 2018 at 12:30 PM Marek Vasut wrote:
>>
>> On 12/07/2018 01:29 PM, Alex Kiernan wrote:
>>> On Fri, Dec 7, 2018 at 11:54 AM Marek Vasut wrote:
On 12/07/2018 09:56 AM, Alex Kiernan wrote:
[...]
> +++
On Fri, Dec 07, 2018 at 02:50:43PM +0100, Jean-Jacques Hiblot wrote:
> If DM_I2C is used , the I2C controllers must be registered as U_BOOT_DEVICE
> because OF_CONTROL is not used in the SPL.
>
> Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
--
Tom
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On Fri, Dec 07, 2018 at 02:50:47PM +0100, Jean-Jacques Hiblot wrote:
> From: Andreas Dannenberg
>
> The EEPROM reading in the board detection code is done through legacy
> I2C functions which on platforms using DM_I2C this functionality is
> provided via the CONFIG_DM_I2C_COMPAT layer. To allow
On Fri, Dec 07, 2018 at 02:50:46PM +0100, Jean-Jacques Hiblot wrote:
> Those driver are not DM drivers per se (not using the PMIC/regulator
> framework) and are using the legacy I2C API. Make them compatible with
> the DM_I2C API.
>
> This impacts the following drivers:
> - palmas (used by
Hi Wolfgang,
On Fri, Dec 7, 2018 at 1:21 PM Wolfgang Denk wrote:
> This should also work - replace the line
>
> @(echo $$(($(CONFIG_BOARD_SIZE_LIMIT))); wc -c $@ ) | \
>
> by
>
> @(awk "END { print $$(echo $(CONFIG_BOARD_SIZE_LIMIT)) }" /dev/null;
> wc -c $@ ) | \
>
>
> Can you
On Wed, Nov 21, 2018 at 11:35 PM Priit Laes wrote:
>
> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3" series,
> posted by Olliver Schinagl in March 2017. Unfortunately it never got past
> initial discussion [1], but most Olimex Lime2 boards are still running
> into this bug.
From: Hiroyuki Yokoyama
This patch fixes the problem that "main memory domain AXI secure
access protection error" occurs when booting Cortex-A53. Exclude
the area (0x43f0 to 0x47DF) set by DBSC from the map area.
Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
---
From: Takeshi Kihara
This patch fixes the problem that "main memory domain AXI secure access
protection error" occurs. Exclude the area (0x43f0 to 0x47DF)
set by DBSC from the map area.
Signed-off-by: Takeshi Kihara
Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
---
From: Takeshi Kihara
This patch fixes the problem that u-boot will not start unless icache is
enabled early.
Signed-off-by: Takeshi Kihara
Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/cpu_info.c| 4 ++--
arch/arm/mach-rmobile/memmap-gen3.c | 4
Dear Fabio,
In message
you wrote:
>
> > /bin/sh: 1: arithmetic expression: expecting primary: ""(1 * 1024)""
D*mn. I really thought I had tried this in a dash based
environment, too. Sorry for causing such confusion.
> SHELL = /bin/bash"
Yes, if this is really a bash only feature that
Dear Fabio,
In message
you wrote:
>
> I replaced it on the main Makefile and also in the imx one and it
> works as expected now.
Thanks.
> When you send the v2, you can add:
>
> Tested-by: Fabio Estevam
Done. Thanks for your patience.
Best regards,
Wolfgang Denk
--
DENX Software
So far, the use of CONFIG_BOARD_SIZE_LIMIT would only work with
plain numeric constants. Extend it to allow for expressions, so one
can for example use
#define CONFIG_BOARD_SIZE_LIMIT (768 << 10)
in the board configuration.
Signed-off-by: Wolfgang Denk
Tested-by: Fabio Estevam
Cc:
On Wed, Nov 28, 2018 at 07:17:49PM +0100, Álvaro Fernández Rojas wrote:
> Move dma_ops to a separate header file, following other uclass
> implementations. While doing so, this patch also improves dma_ops
> documentation.
>
> Reviewed-by: Tom Rini
> Reviewed-by: Simon Glass
> Signed-off-by:
On Mon, Nov 26, 2018 at 08:20:19PM +0100, Philipp Tomsich wrote:
> In commit e5e06b65ad65 ("clk: Allow clock defaults to be set also
> during re-reloc state") the earlier guard against setting clock
> defaults in pre-reloc state was removed. While it is easy to filter
> 'assigned-clocks'
On Tue, Nov 27, 2018 at 01:49:52PM +0100, Benjamin Gaignard wrote:
> Implement hardware spinlock support for STM32MP1.
>
> Signed-off-by: Benjamin Gaignard
> Reviewed-by: Simon Glass
> Reviewed-by: Patrice Chotard
Applied to u-boot/master, thanks!
--
Tom
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On Sat, Dec 01, 2018 at 06:42:08PM +0100, Álvaro Fernández Rojas wrote:
> Signed-off-by: Álvaro Fernández Rojas
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Nov 28, 2018 at 09:33:43AM +, eugen.hris...@microchip.com wrote:
> Add test for the SPL binary size and the bss section size.
> This will throw an error at build time if the SPL sections
> do not fit in the designated RAM area, thus avoiding oversizing the SPL.
>
> Based on original
On Mon, Dec 03, 2018 at 08:29:43AM -0600, Adam Ford wrote:
> Re-synce the device tree files from Linux 4.20
>
> Signed-off-by: Adam Ford
>
> diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts
> index a1f4d6d5a5..0177e3ed20 100644
Applied to u-boot/master, thanks!
--
Tom
On Mon, Dec 03, 2018 at 10:52:53AM +0100, Patrice Chotard wrote:
> As all STM32 SoCs supports CONFIG_CLK flag,
> it becomes useless in this driver, remove it.
>
> Signed-off-by: Patrice Chotard
Applied to u-boot/master, thanks!
--
Tom
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Hi Tom,
Please pull this PR.
thanks,
Jagan.
The following changes since commit 57dbc151437b36cc1105857d222df28b095236d7:
rockchip: rk3399: Add MAINTAINERS entry (2018-12-06 10:24:12 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-sunxi.git master
for you to fetch
On Fri, Dec 7, 2018 at 6:58 AM Vignesh R wrote:
>
> On 07/12/18 12:47 AM, Simon Goldschmidt wrote:
> > Am 06.12.2018 um 18:39 schrieb Vignesh R:
> >> On 06/12/18 10:06 PM, Simon Goldschmidt wrote:
> >>> Am 06.12.2018 um 14:54 schrieb Simon Goldschmidt:
> On Thu, Dec 6, 2018 at 2:45 PM
On Mon, Dec 03, 2018 at 03:12:25PM +0100, Felix Brack wrote:
> This patch adds code missing when CONFIG_DEBUG_UART_OMAP is enabled as
> early debugging UART. The code is basically copied from the ns16550
> driver.
>
> Signed-off-by: Felix Brack
Applied to u-boot/master, thanks!
--
Tom
On Mon, Dec 03, 2018 at 10:52:52AM +0100, Patrice Chotard wrote:
> To allow access to this define by other driver, move
> it into gpio.h
>
> Signed-off-by: Patrice Chotard
Applied to u-boot/master, thanks!
--
Tom
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