Hi Sean
> On 3/10/20 4:20 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> The IPI code could have race conditions in several places.
> >> * Several harts could race on the value of gd->arch->clint/plic
> >> * Non-boot harts could race with the main hart on the DM subsystem In
> >> addition, if an IPI
Hi Sean
> On 3/10/20 5:08 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> Where possible, I have tried to find compatible drivers based on the layout
> >> of registers. However, many devices remain untested. All untested devices
> >> have been left disabled, but some tentative properties (such as
Hi Tom,
Please pull mmc-2020-3-9
--
DM support for CA SoCs
eMMC board for presidio-asic
Add defer probe for mmc sdhci
TI SoCs mmc misc update
--
CI: https://travis-ci.org/MrVan/u-boot/builds/659943777
Thanks,
Peng.
The
Hi Sean
> On 3/10/20 5:04 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> The Sipeed Maix series is a collection of boards built around the RISC-V
> >> Kendryte K210 processor. This processor contains several peripherals to
> >> accelerate neural network processing and other "ai" tasks. This includes a
On Tue, 10 Mar 2020 at 04:33, Alex Kiernan wrote:
>
> 4dbc107f4683 ("cmd: gpio: Correct do_gpio() return value") correctly
> changed the behaviour of the gpio command to return CMD_RET_SUCCESS or
> CMD_RET_FAILURE.
>
> But any existing script which expects the return value to be the pin
> value
Hi Andy,
On Tue, 10 Mar 2020 at 08:51, Andy Shevchenko
wrote:
>
> On Sat, Mar 07, 2020 at 04:22:13PM -0700, Simon Glass wrote:
> > This little series adds a few checks into the code to allow better
> > operation when booting a build from a previous-state loader such as
> > coreboot.
> >
> > At
Hi Tom,
On Mon, 9 Mar 2020 at 11:42, Tom Rini wrote:
>
> On Mon, Mar 09, 2020 at 11:10:55AM -0600, Stephen Warren wrote:
> > On 3/6/20 8:07 PM, Simon Glass wrote:
> > > It is a pain to have to set the ARCH and CROSS_COMPILE environment
> > > variables when using test.py's --build option. It is
The R5F subsystem/cluster on K3 SoCs can support both LockStep and
Split-modes (superset) or just Split-mode depending on an eFUSE
capability register. The LockStep configuration bit is Read-only
though on Split-mode _only_ devices and as such the System Firmware
does not allow the LockStep mode
Hi Sean
> On 3/10/20 2:51 AM, Rick Chen wrote:
> > Hi Sean
> >
> >>> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> >>> just enable them as normal. The enable count is local to the struct clk,
> >>> but this will never result in the actual en-/dis-able op being called
On 10/03/20 8:38 PM, Andrew F. Davis wrote:
> Additions have been made to the non-HS defconfig without the same
> being made to the HS defconfig, sync them.
>
> Signed-off-by: Andrew F. Davis
Applied to u-boot-ti/next
Thanks and regards,
Lokesh
Hi Simon,
-"Simon Glass" schrieb: -
>
> Devices need to report various identifiers in the ACPI tables. Rather than
> hard-coding these in drivers it is typically better to put them in the
> device tree.
>
> Add a binding file to describe this.
>
> Signed-off-by: Simon Glass
> ---
>
Hi Sean
> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> just enable them as normal. The enable count is local to the struct clk,
> but this will never result in the actual en-/dis-able op being called
> (unless the same struct clk is enabled twice).
>
> For clocks in
Hi Simon,
-"Simon Glass" schrieb: -
>
> Each ACPI table has its own version number. Add the version numbers in a
> single function so we can keep them consistent and easily see what
> versions are supported.
>
> Start a new acpi_table file in a generic directory to house this function.
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, March 10, 2020 9:54 AM
> To: Lukas Auer; Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Subject: Re: [PATCH 1/2] riscv: Fix sbi_remote_sfence_vma{,_asid}
>
> Hi Rick,
>
> On Fri, Mar 6, 2020 at 4:44 PM Bin Meng wrote:
> >
> >
Hi Sean
> The IPI code could have race conditions in several places.
> * Several harts could race on the value of gd->arch->clint/plic
> * Non-boot harts could race with the main hart on the DM subsystem In
> addition, if an IPI was pending when U-Boot started, it would cause the
> IPI
Hi Simon,
> -"Simon Glass" schrieb: -
>
> The ASL compiler cannot handle C structures and the like so needs some
> sort of header guard around these.
>
> We already have an __ASSEMBLY__ #define but it seems best to create a new
> one for ACPI since the rules may be different.
>
> Add
On 25.02.2020 10:16, Eugen Hristev wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> From: Fabien Lehoussel
>
> SPL boot cannot find dtb if CONFIG_SPL_SEPARATE_BSS is disabled :
>
> CONFIG_SPL_SEPARATE_BSS=n
>
> RomBOOT
> Missing DTB
>
On 09/03/20 9:56 PM, Andrew F. Davis wrote:
> Additions have been made to the non-HS defconfig without the same
> being made to the HS defconfig, sync them.
As I said earlier, It is not easy for everyone to enable and test HS platforms.
>
> Signed-off-by: Andrew F. Davis
Can you rebase on
Hi Sean
> > For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> > just enable them as normal. The enable count is local to the struct clk,
> > but this will never result in the actual en-/dis-able op being called
> > (unless the same struct clk is enabled twice).
> >
> >
Hi Sean
> This patch adds alternate versions of the clk_*_register functions for use
> with statically-allocated struct clks. This allows drivers to define clocks
> at compile-time and register them at run-time without malloc-ing. This
> increases the size of the binary, but should not affect ram
Hi Sean
> Where possible, I have tried to find compatible drivers based on the layout
> of registers. However, many devices remain untested. All untested devices
> have been left disabled, but some tentative properties (such as compatible
> strings, and clocks, interrupts, and resets properties)
Hi Sean
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supporting
Add a function reserve_stack_aligned() to reserved memory with 16 bits
alignment after the stack pointer (gd->start_addr_sp) and use this new
function in board_f.c to reserve all the memory area (malloc, board, gd,
fdt, bootstage, stacks).
This 16 byte alignment is needed for cast on struct
This reverts the workaround introduced by the
commit 16fec9b0bc1a ("stm32mp1: remove the imply BOOTSTAGE")
As the bootstage alignment issue is now solved.
Signed-off-by: Patrick Delaunay
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-stm32mp/Kconfig | 2 ++
1
Simplify the arm relocation behavior and get gd directly form new_gd,
as it is already done in crt0_64.S:
ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */
This patch avoid assumption on new GD location (new GD is below bd -
with #GD_SIZE offset).
Signed-off-by: Patrick
Hi Simon,
-"Simon Glass" schrieb: -
>
> This file is potentially useful to other architectures saddled with ACPI
> so move it into a common location.
Nit: "move most of its contents to a common location"
(not the complete file is moved, some parts stay at the old location)
>
>
From: Patrice Chotard
In reserve_bootstage(), in case size is odd, gd->new_bootstage
is not aligned. In bootstage_relocate(), the platform hangs when
getting access to data->record[i].name.
To avoid this issue, make gd->new_bootstage 16 byte aligned.
To ensure that new_bootstage is 16 byte
Hi,
It is a V4 with only cosmetics udpate (s/insure/ensure)
for the V3 serie:
http://patchwork.ozlabs.org/project/uboot/list/?series=162918=*
V2 was:
http://patchwork.ozlabs.org/project/uboot/list/?series=154685=*
After the first correction, only for bootstage alignment,
I remove the stm32mp1
4dbc107f4683 ("cmd: gpio: Correct do_gpio() return value") correctly
changed the behaviour of the gpio command to return CMD_RET_SUCCESS or
CMD_RET_FAILURE.
But any existing script which expects the return value to be the pin
value is broken by this change.
Reinstate the legacy behaviour for
On Tue, Mar 10, 2020 at 10:48:43AM +0100, Stefano Babic wrote:
> Hi,
>
> was the job time on travis reduced ? Even if jobs are high split, I get
> several task failures due to "job time". This comprises "non i.MX6 catch
> all", "catch all ARM" and "catch all AARCH64". Known changes or we
>
Hi Simon,
-"Simon Glass" schrieb: -
>
> Add a sandbox test for the basic ACPI functionality we have so far.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v2:
> - Add in the acpi_table.h header file to this patch
>
> arch/sandbox/dts/test.dts
Hello Tom,
Please pull tag u-boot-atmel-fixes-2020.04-a , the first set of fixes
for the 2020.04 cycle.
Includes two small configuration fixes that will solve the SPL booting
on sama5d3_xplained board.
Thanks!
Eugen
The following changes since commit 548ce227d3d852455c6395c0cec30af0cda77b09:
Hi Philippe,
On Mon, Mar 9, 2020 at 8:25 PM Philippe Schenker
wrote:
>
> Those properties are not supported by MAC on i.MX8MM
>
> Signed-off-by: Philippe Schenker
> ---
>
> arch/arm/dts/imx8mm-verdin.dts | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm-verdin.dts
Hi Tom,
On 10.03.20 12:55, Tom Rini wrote:
> On Tue, Mar 10, 2020 at 10:48:43AM +0100, Stefano Babic wrote:
>
>> Hi,
>>
>> was the job time on travis reduced ? Even if jobs are high split, I get
>> several task failures due to "job time". This comprises "non i.MX6 catch
>> all", "catch all ARM"
Hi Simon,
-"Simon Glass" schrieb: -
>
> This function needs to be used by sandbox for tests. Move it into the
> generic directory.
Nit: Move it into the generic directory and add a test for it.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v2: None
>
Hi Pratik,
On Tue, Mar 10, 2020 at 2:11 PM Pratik Rajyaguru
wrote:
>
> Hi Igor,
>
> I have already posted query in NXP Community. Here's thread:
> https://community.nxp.com/message/1270693
>
> I received suggestion to post in u-boot mailing list, because the query is
> specific to u-boot
On 3/10/20 4:20 AM, Rick Chen wrote:
> Hi Sean
>
>> The IPI code could have race conditions in several places.
>> * Several harts could race on the value of gd->arch->clint/plic
>> * Non-boot harts could race with the main hart on the DM subsystem In
>> addition, if an IPI was pending when
Hi Simon,
> From: Simon Goldschmidt
> Sent: vendredi 6 mars 2020 12:28
>
> On Fri, Mar 6, 2020 at 11:01 AM Patrick Delaunay
> wrote:
> >
> > Add stub for functions clk_...() when CONFIG_CLK is deactivated.
> >
> > This patch avoids compilation issues for driver using these API
> > without
Add support for clock with driver model.
This patch don't added dependency because when CONFIG_CLK
is not activated the clk function are stubbed.
Reviewed-by: Simon Goldschmidt
Signed-off-by: Patrick Delaunay
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Add stub for functions clk_...() when CONFIG_CLK is deactivated.
This patch avoids compilation issues for driver using these API
without protection (#if CONFIG_IS_ENABLED(CLK))
For example, before this patch we have undefined reference to
`clk_disable_bulk') for code:
clk_disable_bulk(>clks);
In this serie I update the DWC2 host driver to use the device tree
information and the associated PHY and CLOCK drivers when they are
availables.
V6 is minor update of the first patch of the serie;
I update some clk stub to return success after Simon Goldschmidt
remarks on V5:
Solve issue for the display of "usb start" command on stm32mp1
because one carriage return is missing in DWC2 probe.
Before the patch:
STM32MP> usb start
starting USB...
Bus usb-otg@4900:Bus usbh-ehci@5800d000: USB EHCI 1.00
after the patch:
STM32MP> usb start
starting USB...
Bus
Use generic phy to initialize the PHY associated to the
DWC2 device and available in the device tree.
This patch don't added dependency because when CONFIG_PHY
is not activated, the generic PHY function are stubbed.
Reviewed-by: Simon Goldschmidt
Signed-off-by: Patrick Delaunay
---
Changes in
Assert reset before deassert in dwc2_reset;
this patch solve issues when the DWC2 registers are already
initialized with value incompatible with host mode.
Force a hardware reset of the IP reset all the DWC2 registers at
default value, the host driver start with a clean state
(Core Soft reset
Hi Pratik,
On Tue, Mar 10, 2020 at 12:37 PM Pratik Rajyaguru
wrote:
>
> Hello All,
>
> I want to set boot count to 5 for iMX.6 to set attempt counter, in case of
> failures at boot time. I am using both Dual and Dual lite modules.
>
> U-boot source code reference: Freescale's U-Boot 2014.04.
>
Hi Simon,
-"Simon Glass" schrieb: -
>
> The DMA Remapping Reporting (DMAR) table contains information about DMA
> remapping.
>
> Add a version simple version of this table with only the minimum fields
> filled out. i.e. no entries.
>
> Reviewed-by: Bin Meng
> Signed-off-by: Simon
On 3/10/20 5:08 AM, Rick Chen wrote:
> Hi Sean
>
>> Where possible, I have tried to find compatible drivers based on the layout
>> of registers. However, many devices remain untested. All untested devices
>> have been left disabled, but some tentative properties (such as compatible
>> strings,
Hi Stefano,
On Tue, Mar 10, 2020 at 5:48 PM Stefano Babic wrote:
>
> Hi,
>
> was the job time on travis reduced ? Even if jobs are high split, I get
> several task failures due to "job time". This comprises "non i.MX6 catch
> all", "catch all ARM" and "catch all AARCH64". Known changes or we
>
On Tue, Mar 10, 2020 at 09:47:33AM +, Alex Kiernan wrote:
> On Sat, Feb 8, 2020 at 12:06 AM Tom Rini wrote:
> >
> > On Sun, Jan 05, 2020 at 08:10:56PM +0100, Luka Kovacic wrote:
> >
> > > Use the correct return value in function do_gpio() and update
> > > commands documentation with the
On 3/10/20 5:04 AM, Rick Chen wrote:
> Hi Sean
>
>> The Sipeed Maix series is a collection of boards built around the RISC-V
>> Kendryte K210 processor. This processor contains several peripherals to
>> accelerate neural network processing and other "ai" tasks. This includes a
>> "KPU" neural
Hi,
was the job time on travis reduced ? Even if jobs are high split, I get
several task failures due to "job time". This comprises "non i.MX6 catch
all", "catch all ARM" and "catch all AARCH64". Known changes or we
should go on and split again and again ?
Best regards,
Stefano
--
On Sat, Feb 8, 2020 at 12:06 AM Tom Rini wrote:
>
> On Sun, Jan 05, 2020 at 08:10:56PM +0100, Luka Kovacic wrote:
>
> > Use the correct return value in function do_gpio() and update
> > commands documentation with the return values from command_ret_t enum.
> >
> > CMD_RET_SUCCESS is returned on
On 19.12.19 15:27, Oliver Graute wrote:
> Fix broken fsl_esdhc_imx conversion
>
> Signed-off-by: Oliver Graute
> Cc: Stefano Babic
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Simon Glass
> Cc: Ye Li
> Cc: uboot-imx
> ---
> board/advantech/imx8qm_rom7720_a1/spl.c | 4 ++--
> 1 file changed, 2
Hello All,
I want to set boot count to 5 for iMX.6 to set attempt counter, in case of
failures at boot time. I am using both Dual and Dual lite modules.
U-boot source code reference: Freescale's U-Boot 2014.04.
As I checked, CONFIG_BOOTCOUNT_LIMIT MACRO can be used to configure attempt
I'm currently trying to boot a Congatec x86 eval board from a USB Mass Storage.
I have a config based on efi-x86_payload64_defconfig with the following changes:
27a28
> CONFIG_ENV_OFFSET=0x0
493c494
< CONFIG_ENV_IS_NOWHERE=y
---
> # CONFIG_ENV_IS_NOWHERE is not set
498c499
< #
Thanks Alifer!
I just followed the README, and it working very well.
Congratulations!
Tested-by: marco...@gmail.com
On 3/10/20 2:51 AM, Rick Chen wrote:
> Hi Sean
>
>>> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
>>> just enable them as normal. The enable count is local to the struct clk,
>>> but this will never result in the actual en-/dis-able op being called
>>> (unless the same
On Tue, Mar 10, 2020 at 12:37 PM Tom Rini wrote:
>
> On Tue, Mar 10, 2020 at 09:47:33AM +, Alex Kiernan wrote:
> > On Sat, Feb 8, 2020 at 12:06 AM Tom Rini wrote:
> > >
> > > On Sun, Jan 05, 2020 at 08:10:56PM +0100, Luka Kovacic wrote:
> > >
> > > > Use the correct return value in function
Hi Philippe,
On Mon, Mar 9, 2020 at 8:26 PM Philippe Schenker
wrote:
>
> This patch determines which phy is placed on the board with the PHY ID
> then it sets the same settings for KSZ9031 as before but for KSZ9131
> it enables both RXC and TXC delay lines in the PHY.
> This will compensate the
On Sun, Mar 08, 2020 at 09:44:36PM -0600, Simon Glass wrote:
> ACPI (Advanced Configuration and Power Interface) is an Intel standard
Not Intel for a long time. Or more precisely, not *only* Intel.
Also this should be corrected (I guess dropping Intel would work) everywhere in
this series.
>
Correct the dependency for STM32 ETZPC protection, linked to SOC
STM32MP identified by CONFIG_STM32MP15x and not linked to
CONFIG_TARGET_STM32MP1 (no more existing).
This patch fix an issue introduced by commit 846254888e2e ("stm32mp1:
split board and SOC support for STM32MP15x family").
Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.
Signed-off-by: Andrew F. Davis
---
Changes from v1:
- Rebased on u-boot-ti/next
configs/am65x_hs_evm_a53_defconfig | 49 +++---
On 3/10/20 11:09 AM, Patrick Delaunay wrote:
>
> In this serie I update the DWC2 host driver to use the device tree
> information and the associated PHY and CLOCK drivers when they are
> availables.
>
> V6 is minor update of the first patch of the serie;
> I update some clk stub to return
> Currently the expansion of the console variable leads to
> the following kernel command line:
> console=ttyLP0,${baudrate} earlycon root=/dev/mmcblk1p2 rootwait rw
> , which causes the console to not show characters after the LPUART driver
> is probed as the 'baudrate' variable is not properly
> On the aristainetos2c boards the PMIC needs to be initialized,
> because the Ethernet PHY uses a different regulator that is not
> setup per hardware default. This does not influence the other
> versions as this regulator isn't used there at all.
> Signed-off-by: Heiko Schocher
Applied to
> Enale DM_PCI support in order to avoid board removal from
> the project.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing
> Convert imx6sabresd ethernet to driver model to fix the following warning:
> = WARNING ==
> This board does not use CONFIG_DM_ETH (Driver Model
> for Ethernet drivers). Please update the board to use
> CONFIG_DM_ETH before the v2020.07 release. Failure to
> This fixes the following warning:
> = WARNING ==
> This board does not use CONFIG_DM_ETH (Driver Model
> for Ethernet drivers). Please update the board to use
> CONFIG_DM_ETH before the v2020.07 release. Failure to
> update by the deadline may result in
> From: Max Krummenacher
> The FEC in the i.MX8MM doesn't support this feature. So don't pretend one
> can use it.
> Signed-off-by: Max Krummenacher
> Signed-off-by: Igor Opaniuk
> Acked-by: Peng Fan
> Reviewed-by: Oleksandr Suvorov
Applied to u-boot-imx, master, thanks !
Best regards,
> Instead of resetting the ethernet phy through functions in imx8mq_evk.c, let
> the
> driver reset the phy via dts description adding a reset duration of 10 ms
> following atheros 8031's datasheet recommendation.
> Signed-off-by: Alifer Moraes
Applied to u-boot-imx, master, thanks !
Best
> Some device may enable CONFIG_CLK but not still support this clock in
> CC, so better use debug() in place of dev_warn() otherwise a lot of
> boards will throw useless dev_warn()s.
> Signed-off-by: Giulio Benetti
> Reviewed-by: Simon Glass
Applied to u-boot-imx, master, thanks !
Best regards,
> From: Igor Opaniuk
> Let pinctrl configuration for eMMC node (usdhc1) also be
> accessible in SPL.
> Signed-off-by: Igor Opaniuk
> Reviewed-by: Peng Fan
> Reviewed-by: Oleksandr Suvorov
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
/custodians/u-boot-imx.git
tags/u-boot-imx-20200310
for you to fetch changes up to 9f656fbee3b433ae1e9daf5d92d46bbdcc9551eb:
mx6slevk: Convert to DM_ETH (2020-03-10 10:59:08 +0100)
Fixes for 2020.04
-
- DM
On Sun, Mar 08, 2020 at 09:44:37PM -0600, Simon Glass wrote:
> Devices need to report various identifiers in the ACPI tables. Rather than
> hard-coding these in drivers it is typically better to put them in the
> device tree.
>
> Add a binding file to describe this.
...
> +Device bindings are
On Sat, Mar 07, 2020 at 04:22:13PM -0700, Simon Glass wrote:
> This little series adds a few checks into the code to allow better
> operation when booting a build from a previous-state loader such as
> coreboot.
>
> At present we have a 'coreboot' target but this runs very different code
> from
> I would like to help co-maintaining this board.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> added missing ahab.o in Makefile
> Signed-off-by: Oliver Graute
> Cc: Stefano Babic
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Simon Glass
> Cc: Ye Li
> Cc: uboot-imx
> Reviewed-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> This fixes the following warning:
> = WARNING ==
> This board does not use CONFIG_DM_ETH (Driver Model
> for Ethernet drivers). Please update the board to use
> CONFIG_DM_ETH before the v2020.07 release. Failure to
> update by the deadline may result in
> Sync the imx6sx dts files with kernel 5.4.16.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB
> From: Frieder Schrempf
> The current implementation in arch/arm/mach-imx/cpu.c uses non-DM
> code to retrieve the core clock frequency. As the root clock is not
> listed we currently get:
> CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
> Fix this by adding the missing entry, which results in:
>
> I would like to help co-maintaining this board.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> Booting a mainline kernel in secure mode on i.MX7D causes only
> one CPU to be brought up.
> Change it to booting in non secure mode by default, which
> allows the two CPUs to be brought up.
> It does have a side effect of not probing the CAAM driver.
> If CAAM driver is needed then a secure
> Set CONFIG_SYS_BOOTMAPSZ to the amount of memory available which is needed
> to relocate the kernel, device tree and initrd.
> Remove 'fdt_high' and 'initrd_high' environment variables from default
> environment which prevents relocation of FDT and initrd.
> Signed-off-by: Oliver Graute
> Cc:
Hi Philippe,
On Mon, Mar 9, 2020 at 8:25 PM Philippe Schenker
wrote:
>
> This patches uses the existing functions for interacting with the
> KSZ9031 and uses the values appropriate for our board.
>
> Signed-off-by: Philippe Schenker
> ---
>
> board/toradex/verdin-imx8mm/verdin-imx8mm.c | 32
Add a separate function for printing sysfw version so that it can be
called independently of k3_sysfw_loader.
Signed-off-by: Lokesh Vutla
Signed-off-by: Vignesh Raghavendra
---
arch/arm/mach-k3/am6_init.c | 9 +
arch/arm/mach-k3/common.c | 22 ++
On Tue, Mar 10, 2020 at 01:05:31PM +0100, Stefano Babic wrote:
> Hi Tom,
>
> On 10.03.20 12:55, Tom Rini wrote:
> > On Tue, Mar 10, 2020 at 10:48:43AM +0100, Stefano Babic wrote:
> >
> >> Hi,
> >>
> >> was the job time on travis reduced ? Even if jobs are high split, I get
> >> several task
Hi Igor,
I have already posted query in NXP Community. Here's thread:
https://community.nxp.com/message/1270693
I received suggestion to post in u-boot mailing list, because the query is
specific to u-boot booting counter mechanism and commands.
Please suggest, if any insight related to
On Sun, Mar 08, 2020 at 09:44:33PM -0600, Simon Glass wrote:
> With P2SB the initial BAR (base-address register) is set up by TPL and
> this is used unchanged right through U-Boot.
>
> At present the reading of this address is split between the ofdata() and
> probe() methods. There are a few
On 3/10/20 4:15 AM, Lokesh Vutla wrote:
>
>
> On 09/03/20 9:56 PM, Andrew F. Davis wrote:
>> Additions have been made to the non-HS defconfig without the same
>> being made to the HS defconfig, sync them.
>
> As I said earlier, It is not easy for everyone to enable and test HS
> platforms.
>
Hi Patrick
On 3/10/20 4:05 PM, Patrick Delaunay wrote:
> Correct the dependency for STM32 ETZPC protection, linked to SOC
> STM32MP identified by CONFIG_STM32MP15x and not linked to
> CONFIG_TARGET_STM32MP1 (no more existing).
>
> This patch fix an issue introduced by commit 846254888e2e
> Added missing USDHC Base address defines
> Signed-off-by: Oliver Graute
> Cc: Stefano Babic
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Simon Glass
> Cc: Ye Li
> Cc: uboot-imx
> Reviewed-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> fdt_high value of 0x disables fdt relocation on boot. We don't
> need that for Cubox-i/Hummingboard. Rely on generic code to find the
> optimal fdt location at boot time.
> Signed-off-by: Baruch Siach
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> Before DM_VIDEO conversion this board used 24bpp
> display configuration, so use it again.
> Signed-off-by: Anatolij Gustschin
> Reviewed-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> Board is not longer used, remove it.
> Signed-off-by: Stefano Babic
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235
> Sync the imx6sx-sdb dts files with kernel 5.4.16.
> Signed-off-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> Soc supports cache so let's enable it.
> Signed-off-by: Giulio Benetti
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235
On 3/10/20 6:01 PM, Patrick DELAUNAY wrote:
> Hi Marek,
>
>> From: Marek Vasut
>> Sent: mardi 10 mars 2020 16:20
>> Subject: Re: [PATCH v6 0/5] usb: host: dwc2: use driver model for PHY and
>> CLOCK
>> Importance: High
>>
>> On 3/10/20 11:09 AM, Patrick Delaunay wrote:
>>>
>>> In this serie I
On Tue, Mar 10, 2020 at 2:15 PM Tom Rini wrote:
> I probably messed things up here then. With
> https://patchwork.ozlabs.org/patch/1239143/ and
> https://patchwork.ozlabs.org/patch/1239144/ is there not a different fix
> needed for i.MX8 now, or were there two issues here that I confused?
My
On Tue, Mar 10, 2020 at 02:34:26PM -0300, Fabio Estevam wrote:
> On Tue, Mar 10, 2020 at 2:15 PM Tom Rini wrote:
>
> > I probably messed things up here then. With
> > https://patchwork.ozlabs.org/patch/1239143/ and
> > https://patchwork.ozlabs.org/patch/1239144/ is there not a different fix
> >
Hi Fabio,
On Thu, Jan 9, 2020 at 12:29 PM Fabio Estevam wrote:
>
> On some i.MX8QXP MEK boards with no MAC address stored, the following
> hang is seen:
>
> Error: ethernet@5b04 address not set.
>
> (Board hangs)
>
> One way to avoid this issue is to select CONFIG_NET_RANDOM_ETHADDR, so
>
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