Re: [PATCH v3 14/17] mtd: spi-nor-core: Perform a Soft Reset on shutdown

On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav wrote: > > On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it > supports it. But Linux as of now expects to get the flash in 1S-1S-1S > mode. Handing the flash to Linux in Octal DTR mode means the kernel will > fail to detect the

[PATCH v5 15/16] configs: evb-rk3399: update support usb3.0 host

Update evb-rk3399 default config to support USB3.0 Host. Signed-off-by: Frank Wang Reviewed-by: Jagan Teki --- configs/evb-rk3399_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7f14e18b1b..6cfb4e5dac 100644

[PATCH v5 01/16] clk: rk3399: Enable/Disable the USB2PHY clk

From: Jagan Teki Enable/Disable the USB2PHY clk for rk3399. CLK is clear in enable and set in disable functionality. Signed-off-by: Jagan Teki --- drivers/clk/rockchip/clk_rk3399.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c

[PATCH v5 16/16] roc-rk3399-pc: Enable USB3.0 Host

From: Jagan Teki Enable USB3.0 Host support for ROC-RK3399-PC boards. Tested USB3.0 SSD on Type C1 port on board. => usb start starting USB... Bus usb@fe38: USB EHCI 1.00 Bus usb@fe3c: USB EHCI 1.00 Bus dwc3: usb maximum-speed not found Register 2000140 NbrPorts 2 Starting the

Re: [PATCH 2/5 v2] efi_loader: Implement EFI variable handling via OP-TEE

On Wed, May 13, 2020 at 08:14:19AM +0200, Heinrich Schuchardt wrote: > On 5/11/20 8:14 PM, Ilias Apalodimas wrote: > > In OP-TEE we can run EDK2's StandAloneMM on a secure partition. > > StandAloneMM is responsible for the UEFI variable support. In > > + [...] > > + EFI_ENTRY("%p \"%ls\"

[PATCH v9 10/18] clk: sifive: fu540-prci: Add ddr clock initialization

Release ddr clock reset Signed-off-by: Pragnesh Patel --- drivers/clk/sifive/fu540-prci.c | 51 + 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index bf06c3a3bb..f26a370a64 100644

[PATCH v9 08/18] riscv: sifive: dts: fu540: add U-Boot dmc node

Add dmc node to enable ddr driver. dmc is used to initialize the memory controller. Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git

[PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset

Release ethernet clock reset Signed-off-by: Pragnesh Patel --- drivers/clk/sifive/fu540-prci.c | 20 1 file changed, 20 insertions(+) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index f26a370a64..45491a77d5 100644 ---

[PATCH v9 07/18] sifive: dts: fu540: Add DDR controller and phy register settings

Add DDR controller and phy register settings, taken from fsbl (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel --- .../dts/fu540-hifive-unleashed-a00-ddr.dtsi | 1489 + 1 file changed, 1489 insertions(+) create mode 100644

[PATCH v9 12/18] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux

This sync has changes required to use GPIO in U-Boot and U-Boot SPL. Sync dts from linux v5.7-rc2 commit: "riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file" (sha1: 0a91330b2af9f71cd483f92774182b58f6d9) Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng ---

[PATCH v9 13/18] riscv: cpu: fu540: Add support for cpu fu540

Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel --- arch/riscv/Kconfig | 1 + arch/riscv/cpu/fu540/Kconfig | 15 ++ arch/riscv/cpu/fu540/Makefile| 7 + arch/riscv/cpu/fu540/cpu.c | 22

[PATCH v9 15/18] sifive: fu540: Add sample SD gpt partition layout

From: Jagan Teki This is a sample GPT partition layout for SD card, right now three important partitions are added to make the system bootable. partition layout: PartStart LBA End LBA Name Attributes Type GUID Partition GUID 1 0x0022

[PATCH v9 14/18] riscv: sifive: fu540: add SPL configuration

Add a support for SPL which will boot from L2 LIM (0x0800_) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel

[PATCH v5 04/16] phy: rockchip: Add Rockchip USB2PHY driver

From: Jagan Teki Add Rockchip USB2PHY driver with initial support. This will help to use it for EHCI controller in host mode, and USB 3.0 controller in otg mode. More functionality like charge, vbus detection will add it in future changes. Signed-off-by: Jagan Teki --- drivers/Makefile

[PATCH v5 03/16] clk: rk3399: Enable/Disable TCPHY clocks

From: Jagan Teki Enable/Disable TCPHY clock for rk3399 platform. Signed-off-by: Jagan Teki --- drivers/clk/rockchip/clk_rk3399.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support. The function has been tested pass on rk3399-evb and roc-rk3399-pc board. For V5 update: - Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16]. - Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4

Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset

On Wed, May 13, 2020 at 12:48 PM Pragnesh Patel wrote: > > Hi Jagan, > > >-Original Message- > >From: Jagan Teki > >Sent: 13 May 2020 12:21 > >To: Pragnesh Patel > >Cc: U-Boot-Denx ; Atish Patra > >; Palmer Dabbelt ; Bin > >Meng ; Paul Walmsley ; > >Anup Patel ; Sagar Kadam > >; Rick

RE: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset

>-Original Message- >From: Jagan Teki >Sent: 13 May 2020 13:30 >To: Pragnesh Patel >Cc: U-Boot-Denx ; Atish Patra >; Palmer Dabbelt ; Bin >Meng ; Paul Walmsley ; >Anup Patel ; Sagar Kadam >; Rick Chen ; Lukasz >Majewski ; Anatolij Gustschin ; Simon >Glass >Subject: Re: [PATCH v9 11/18]

[PATCH v9 00/18] RISC-V SiFive FU540 support SPL

This series add support for SPL to FU540. U-Boot SPL can boot from L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. This series depends on: [1] https://patchwork.ozlabs.org/patch/1281853 [2] https://patchwork.ozlabs.org/patch/1281852 All these

[PATCH v9 02/18] riscv: sifive: fu540: Use OTP DM driver for serial environment variable

Use the OTP DM driver to set the serial environment variable. Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 2 + board/sifive/fu540/Kconfig

[PATCH v9 01/18] misc: add driver for the SiFive otp controller

Added a misc driver to handle OTP memory in SiFive SoCs. Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/sifive-otp.c | 273 ++ 3 files changed,

[PATCH v9 06/18] sifive: fu540: add ddr driver

Add driver for fu540 to support ddr initialization in SPL. This driver is based on FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel --- board/sifive/fu540/Kconfig | 2 + drivers/ram/Kconfig| 1 + drivers/ram/Makefile |

[PATCH v9 05/18] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files

Devicetree files in FU540 platform is synced from Linux, like other platforms does. Apart from these U-Boot in FU540 would also require some U-Boot specific node like clint. So, create board specific -u-boot.dtsi files. This would help of maintain U-Boot specific changes separately without

[PATCH v9 09/18] clk: sifive: fu540-prci: Add clock enable and disable ops

Added clock enable and disable functions in prci ops Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/clk/sifive/fu540-prci.c | 108 1 file changed, 96 insertions(+), 12 deletions(-) diff --git

[PATCH v9 04/18] lib: Makefile: build crc7.c when CONFIG_MMC_SPI

When build U-Boot SPL, meet an issue of undefined reference to 'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when CONFIG_MMC_SPI selected. Signed-off-by: Pragnesh Patel --- lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Makefile b/lib/Makefile

[PATCH v9 03/18] riscv: Add _image_binary_end for SPL

For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end Signed-off-by: Pragnesh Patel Reviewed-by: Anup Patel Reviewed-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/cpu/u-boot-spl.lds | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH v5 07/16] usb: dwc3: add dis_enblslpm_quirk

Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang Reviewed-by: Kever Yang Reviewed-by: Jagan Teki

[PATCH v5 05/16] arm64: dts: rk3399: Move u2phy into root port

From: Jagan Teki Yes, This is changing the actual device tree u2phy structure but the problem with the current Generic PHY subsystem is unable to find PHY if the PHY node is not part of the root structure. This will be reverted, - Once we support the PHY subsystem to get the PHY even though

[PATCH v5 02/16] clk: rk3399: Set empty for TCPHY assigned-clocks

From: Jagan Teki Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = < SCLK_UPHY0_TCPDCORE>; assigned-clocks = <

Re: [ANN] U-Boot v2020.07-rc2 released

Hello Heinrich, Am 13.05.2020 um 07:53 schrieb Heinrich Schuchardt: On 5/13/20 5:54 AM, Heiko Schocher wrote: Hello Tom, Am 12.05.2020 um 15:28 schrieb Heiko Schocher: Hello Tom, Am 12.05.2020 um 00:28 schrieb Tom Rini: Hey all, It's release day and I've tagged v2020.07-rc2.  At this

[PATCH v2] rpi_4_defconfig: add missing CONFIG_ARCH_FIXUP_FDT_MEMORY

As discussed at https://lore.kernel.org/linux-arm-kernel/b726290c-1038-3771-5187-6ac370bc9...@arm.com/T/ the defconfig for rpi4 miss CONFIG_ARCH_FIXUP_FDT_MEMORY. Without it, booting with an initrd fail. Signed-off-by: Corentin Labbe --- Changes since v1: - added fix for rpi_4_32b_defconfig

Re: [RESEND PATCH v2 04/11] net: dwc_eth_qos: Make clk_rx and clk_tx optional

Hi David On 5/12/20 11:56 AM, David Wu wrote: > For others using, clk_rx and clk_tx may not be necessary, > and their clock names are different. > > Signed-off-by: David Wu > --- > > Changes in v2: > - Don't change the Rx and Tx clock names. (Patrice, Stephen) > > drivers/net/dwc_eth_qos.c | 61

Re: [PATCH 2/5 v2] efi_loader: Implement EFI variable handling via OP-TEE

On 5/11/20 8:14 PM, Ilias Apalodimas wrote: > In OP-TEE we can run EDK2's StandAloneMM on a secure partition. > StandAloneMM is responsible for the UEFI variable support. In > combination with OP-TEE and it's U-Boot supplicant, variables are > authenticated/validated in secure world and stored on

[PATCH v9 16/18] sifive: fu540: Add U-Boot proper sector start

From: Jagan Teki Add U-Boot proper sector start offset for SiFive FU540. This value is based on the partition layout supported by SiFive FU540. u-boot.itb need to write on this specific offset so-that the SPL will retrieve it from here and load. Signed-off-by: Jagan Teki Reviewed-by: Bin Meng

[PATCH v9 17/18] configs: fu540: Add config options for U-Boot SPL

With sifive_fu540_defconfig: User can use FSBL or u-boot-spl.bin anyone at a time. For FSBL, fsbl->fw_payload.bin (opensbi + U-Boot) For u-boot-spl.bin, u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb) U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with

[PATCH v9 18/18] doc: sifive: fu540: Add description for OpenSBI generic platform

OpenSBI generic platform support provides platform specific functionality based on the FDT passed by previous booting stage. Depends on OpenSBI commit: platform: Add generic FDT based platform support (sha1: f1aa9e54e6ae70aeac638d5b75093520f65d) Signed-off-by: Pragnesh Patel ---

Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset

On Wed, May 13, 2020 at 11:57 AM Pragnesh Patel wrote: > > Release ethernet clock reset Please add a detailed commit message of why the ethernet clock is resetting in SPL code since ethernet won't need for SPL at all? Jagan.

[PATCH v5 06/16] phy: rockchip: Add Rockchip USB TypeC PHY driver

From: Jagan Teki Add USB TYPEC PHY driver for rockchip platform. Referenced from Linux TypeC PHY driver, currently supporting usb3-port and dp-port need to add it in the future. Signed-off-by: Frank Wang Signed-off-by: Jagan Teki --- drivers/phy/rockchip/Kconfig | 7 +

[PATCH v5 11/16] usb: dwc3: amend UTMI/UTMIW phy interface setup

Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/usb/common/common.c | 25 ++ drivers/usb/dwc3/core.c

[PATCH v5 14/16] ARM: dts: rk3399-evb: usb3.0 host support

Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host for Rockchip RK3399 Evaluation Board. Signed-off-by: Frank Wang Reviewed-by: Jagan Teki --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 + 1 file changed, 13 insertions(+) diff --git

[PATCH v5 12/16] usb: dwc3: add make compatible for rockchip platform

RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller in resetting to hold pipe power state in P2 before initializing the PHY. This commit fixed it and added device compatible for rockchip platform. Signed-off-by: Frank Wang Signed-off-by: Jagan Teki ---

[PATCH v5 10/16] usb: dwc3: Enable AutoRetry feature in the controller

From: Jagan Teki By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with

[PATCH v5 13/16] driver: usb: drop legacy rockchip xhci driver

We have changed to use dwc3 generic driver for usb3.0 host, so the legacy Rockchip's xHCI driver is not needed, and drop it. Signed-off-by: Frank Wang Reviewed-by: Jagan Teki --- drivers/usb/host/Kconfig | 9 -- drivers/usb/host/Makefile| 1 -

[PATCH v5 09/16] usb: dwc3: Add disable u2mac linestate check quirk

From: Jagan Teki This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a

[PATCH v5 08/16] usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel.

RE: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock reset

Hi Jagan, >-Original Message- >From: Jagan Teki >Sent: 13 May 2020 12:21 >To: Pragnesh Patel >Cc: U-Boot-Denx ; Atish Patra >; Palmer Dabbelt ; Bin >Meng ; Paul Walmsley ; >Anup Patel ; Sagar Kadam >; Rick Chen ; Lukasz >Majewski ; Anatolij Gustschin ; Simon >Glass >Subject: Re: [PATCH

Re: [RESEND PATCH v2 03/11] net: dwc_eth_qos: Move interface() to eqos_ops structure

On 5/12/20 11:56 AM, David Wu wrote: > After moving to eqos_ops, if eqos_config is defined > outside file, can not export interface() definition, > only export eqos_ops struct defined in dwc_eth_qos.c. > > Signed-off-by: David Wu > --- > > Changes in v2: > - None > > drivers/net/dwc_eth_qos.c |

Re: [RESEND PATCH v2 02/11] net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32

Hi David On 5/12/20 11:56 AM, David Wu wrote: > It can be seen that most of the Socs using STM mac, "snps,reset-gpio" > gpio is used, adding this option makes reset function more general. > > Signed-off-by: David Wu > --- > > Changes in v2: > - Remove the code is not related (Patrice) > >

Re: [PATCH v3 15/17] mtd: spi-nor-core: Perform a Soft Reset on boot

On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav wrote: > > When the flash is handed to us in a stateful mode like 8D-8D-8D, it is > difficult to detect the mode the flash is in. One option is to read SFDP > in all modes and see which one gives the correct "SFDP" signature, but > not all flashes

Re: [RESEND PATCH v2 01/11] net: dwc_eth_qos: Use dev_ functions calls to get FDT data

Hi David On 5/12/20 11:56 AM, David Wu wrote: > It seems dev_ functions are more general than fdt_ functions. > > Signed-off-by: David Wu > --- > > Changes in v2: > - None > > drivers/net/dwc_eth_qos.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git

Re: [RESEND PATCH v2 07/11] net: dwc_eth_qos: Export common struct and interface at head file

Hi David On 5/12/20 11:57 AM, David Wu wrote: > Open structure data and interface, so that Soc using dw_eth_qos > controller can reference. > > Signed-off-by: David Wu > --- > > Changes in v2: > - Add the lost head file. (Patrice) > > drivers/net/dwc_eth_qos.c | 81

RE: [PATCH] net: dwc_eth_qos: Pad descriptors to cacheline size

Hi Stephen and Marek > From: Stephen Warren > Sent: mercredi 29 avril 2020 23:51 > To: Marek Vasut > Cc: u-boot@lists.denx.de; Joe Hershberger ; Patrice > CHOTARD ; Patrick DELAUNAY > ; Ramon Fried ; Stephen > Warren ; Tom Warren > Subject: Re: [PATCH] net: dwc_eth_qos: Pad descriptors to

Re: [PATCH v2] rpi_4_defconfig: add missing CONFIG_ARCH_FIXUP_FDT_MEMORY

On Wed, May 13, 2020 at 12:38:58PM +0200, Matthias Brugger wrote: > > > On 13/05/2020 10:07, Corentin Labbe wrote: > > As discussed at > > https://lore.kernel.org/linux-arm-kernel/b726290c-1038-3771-5187-6ac370bc9...@arm.com/T/ > > the defconfig for rpi4 miss CONFIG_ARCH_FIXUP_FDT_MEMORY. > >

Re: [PATCH 2/2] configs: khadas-vim3: enable HDMI output

On 11/05/2020 15:17, Neil Armstrong via groups.io wrote: > Enable options to permit HDMI output on Khadas VIM3 & VIM3L boards. > > Signed-off-by: Neil Armstrong > --- > configs/khadas-vim3_defconfig | 9 + > configs/khadas-vim3l_defconfig | 4 > 2 files changed, 13 insertions(+) >

Re: [PATCH 1/2] arm: dts: khadas-vim3: include meson-g12-common-u-boot.dtsi to enable HDMI output

On 11/05/2020 15:17, Neil Armstrong wrote: > Include the common g12 u-boot tweaks to permit enabling video output tweaks > on Khadas VIM3 boards. > > Signed-off-by: Neil Armstrong > --- > arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git

RE: [PATCH] ARM: dts: stm32: Synchronize DDR setttings on DH SoMs

Dear Marek, > From: Marek Vasut > Sent: mercredi 29 avril 2020 15:09 > > Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put > them into use by the board file instead of the default ones. These new DRAM > settings are a better fit for the SoMs. > > Signed-off-by: Marek Vasut >

Re: [PATCH v3 15/17] mtd: spi-nor-core: Perform a Soft Reset on boot

On Wed, May 13, 2020 at 2:24 PM Pratyush Yadav wrote: > > On 13/05/20 12:17PM, Jagan Teki wrote: > > On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav wrote: > > > > > > When the flash is handed to us in a stateful mode like 8D-8D-8D, it is > > > difficult to detect the mode the flash is in. One

Re: Antwort: Re: [PATCH v2 00/35] dm: Add programmatic generation of ACPI tables (part B)

On Tue, May 12, 2020 at 05:22:38PM -0600, Simon Glass wrote: > Hi Andy, > > On Tue, 12 May 2020 at 06:32, Andy Shevchenko > wrote: > > > > On Tue, May 12, 2020 at 01:55:49PM +0200, Wolfgang Wallner wrote: > > > > > > Since you were involved a lot in the discussion in the part A series, > > > >

Re: [PATCH 2/2] configs: rpi_arm64: enable SDHCI SDMA support

On 12/05/2020 12:02, matthias@kernel.org wrote: > From: Matthias Brugger > > RPi4 supports SDMA on it's SDHCI controller. Enable to option for > the combine RPi3/4 config. > > Signed-off-by: Matthias Brugger > > --- Queued for rpi-next > > configs/rpi_arm64_defconfig | 1 + > 1

Re: [PATCH 1/2] mmc: sdhci: Use debug for not supported SDMA info message

On 12/05/2020 12:02, matthias@kernel.org wrote: > From: Matthias Brugger > > If CONFIG_MMC_SDHCI_SDMA is enabled but the HW could not support it, > we no longer error out. Instead we do not enable it in the host. > Change the output from printf to debug as this isn't an error but only >

RE: [PATCH] ARM: dts: stm32: Synchronize DDR setttings on DH SoMs

Hi Marek, > From: Marek Vasut > Sent: mardi 12 mai 2020 18:58 > > On 4/29/20 3:08 PM, Marek Vasut wrote: > > Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put > them > > into use by the board file instead of the default ones. These new DRAM > > settings are a better fit for the

[PATCH 0/4] mach-sunxi: sunxi SPI-NAND-SPL

This patch-series enables u-boot to be booted from SPI-NAND memory on sunxi SoCs. Development was done and tested on a sun8i V3s. To accomplish this, the changes where split in 4 different patches. The following list describes the patches, their title, their message ID and contain their

Re: [PATCH] ARM: dts: stm32: Synchronize DDR setttings on DH SoMs

On 5/13/20 2:26 PM, Patrick DELAUNAY wrote: > Hi Marek, > >> From: Marek Vasut >> Sent: mardi 12 mai 2020 18:58 >> >> On 4/29/20 3:08 PM, Marek Vasut wrote: >>> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put >> them >>> into use by the board file instead of the default ones.

USB gadget ethernet status ?

I decided to check out USB gadget ethernet in u-boot and selected USB_ETHER/USB_ETH_RNDIS and tried to build it but that fails due to missing __constant_cpu_to_leXX() definitions. These are nowhere to find in u-boot so I wonder what shape above code is? Jocke

RE: [RESEND PATCH v2 01/11] net: dwc_eth_qos: Use dev_ functions calls to get FDT data

Dear David, > From: David Wu > Sent: mardi 12 mai 2020 11:56 > > It seems dev_ functions are more general than fdt_ functions. > > Signed-off-by: David Wu > --- > > Changes in v2: > - None > > drivers/net/dwc_eth_qos.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > >

RE: [PATCH] stm32mp1: Fix warning display when 1.5A power supply is used

Hi Patrice > From: Patrice CHOTARD > Sent: jeudi 30 avril 2020 18:41 > > On DK1/2 board, when a 1.5A power supply is detected, a warning message is > displayed. In this message, "1.5mA" is displayed instead of "1.5A". > > Signed-off-by: Patrice Chotard > --- > > board/st/stm32mp1/stm32mp1.c

Re: [PATCH 1/2] rpi: Kconfig option for initial page reservation

On 26/02/2020 22:37, kev...@freebsd.org wrote: > From: Kyle Evans > > While the nearly-universal default for the Raspberry Pi family is to use > spin tables and the spin table implementation provided by the Raspberry Pi > Foundation, FreeBSD and others may use a PSCI implementation instead. >

Re: [PATCH 2/2] rpi: use the newly-added RPI_EFI_NR_SPIN_PAGES

On 26/02/2020 22:39, kev...@freebsd.org wrote: > From: Kyle Evans > > Some systems may use a slightly larger stub to do PSCI for booting the RPi > family. The number of pages has been made configurable so that operating > systems building U-Boot for use in these kinds of environments can

Antwort: [PATCH v2 03/35] acpi: Add a way to check device status

Hi Simon, -"Simon Glass" schrieb: - >Betreff: [PATCH v2 03/35] acpi: Add a way to check device status > >At present U-Boot does not support the different ACPI status values, >but >it is best to put this logic in a central place. Add a function to >get the >device status. >

RE: [PATCH 2/2] [RFC] clk: stm32mp1: Handle SoC speed grade configs

Hi Marek, > From: Marek Vasut > Sent: mercredi 13 mai 2020 12:53 > > On 5/13/20 11:12 AM, Patrick DELAUNAY wrote: > > Dear Marek, > > > >> From: Marek Vasut > >> Sent: mardi 12 mai 2020 19:07 > >> > >> There are two speed grades of the STM32MP1, the A/C and D/F, the > >> former can run up to

Re: [PATCH 2/2] [RFC] clk: stm32mp1: Handle SoC speed grade configs

On 5/13/20 2:23 PM, Patrick DELAUNAY wrote: > Hi Marek, > >> From: Marek Vasut >> Sent: mercredi 13 mai 2020 12:53 >> >> On 5/13/20 11:12 AM, Patrick DELAUNAY wrote: >>> Dear Marek, >>> From: Marek Vasut Sent: mardi 12 mai 2020 19:07 There are two speed grades of the

Re: [PATCH v1 01/10] mips: octeon: Initial minimal support for the Marvell Octeon SoC

sorry for the delay ;) Am 02.05.20 um 10:59 schrieb Stefan Roese: > From: Aaron Williams > > This patch adds very basic support for the Octeon III SoCs. Only > CFI parallel NOR flash and UART is supported for now. > > Please note that the basic Octeon port does not include the DDR3/4 >

Re: [PATCH v3 0/2] usb: xhci: Load Raspberry Pi 4 VL805's firmware

On Tue, 2020-05-05 at 18:26 +0200, Nicolas Saenz Julienne wrote: > Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be > loaded explicitly. Earlier versions didn't need that as they where using > an EEPROM for that purpose. This series takes care of setting up the > relevant

RE: [RESEND PATCH v2 02/11] net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32

Hi David > From: David Wu > Sent: mardi 12 mai 2020 11:56 > > It can be seen that most of the Socs using STM mac, "snps,reset-gpio" > gpio is used, adding this option makes reset function more general. > > Signed-off-by: David Wu > --- > > Changes in v2: > - Remove the code is not related

Using a 'cpu' command to print CPU information

Hi All, I am trying to use 'cpu' command, so I modified config file and compiled u-boot with a 'cpu' command enabled. But when I try to use it properly it's completely silent. It appeared that this behaviour is caused by list at 'dev_head' always being empty in the corresponding uclass. But

RE: [PATCH 8/9] board: stm32mp1: update vddcore in SPL

Hi, > From: Patrick DELAUNAY > Sent: mardi 21 avril 2020 17:11 > > For board using STPMIC1, the vddcore is provided by BUCK1 of STMPIC1 and > need to be updated for 800MHz support and only after the clock tree > initialization. > > The VDDCORE voltage value in provide by clock driver, saved

Re: [PATCH] usb: max3420: add the gadget driver

On 5/12/20 3:54 AM, Jassi Brar wrote: > Hi Marek, Hi Lukasz, Hi, > On Sat, Apr 11, 2020 at 10:42 PM Jassi Brar wrote: >> >> On Sat, Apr 11, 2020 at 9:31 PM Marek Vasut wrote: >>> >>> On 4/12/20 2:04 AM, Heinrich Schuchardt wrote: Am April 11, 2020 11:47:06 PM UTC schrieb Jassi Brar

Re: [PATCH 2/2] rpi: use the newly-added RPI_EFI_NR_SPIN_PAGES

On Wed, May 13, 2020 at 7:13 AM Matthias Brugger wrote: > > On 26/02/2020 22:39, kev...@freebsd.org wrote: > > From: Kyle Evans > > > > Some systems may use a slightly larger stub to do PSCI for booting the RPi > > family. The number of pages has been made configurable so that operating > >

Re: [PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang

Thanks. Have you already checked it on gen2? I think I have gen2 board to test. ср, 13 мая 2020 г. в 22:55, Kurt Miller : > > Use the same approach as ROC-RK3328-CC which enables SPL GPIO, > pinctl and regulator support. This allows the gen3 board to > boot through SPL and does not break gen2 in

Re: [PATCH 1/1] tools: ftdgrep: use /* fallthrough */ as needed

Hi Tom, On Wed, May 13, 2020 at 11:42 PM Tom Rini wrote: > > On Tue, May 12, 2020 at 11:04:38PM -0400, Tom Rini wrote: > > On Mon, May 11, 2020 at 09:08:03PM +0200, Heinrich Schuchardt wrote: > > > On 5/11/20 8:40 PM, Tom Rini wrote: > > > > On Sun, May 10, 2020 at 10:12:07PM +0900, Masahiro

Re: [PATCH 1/1] tools: ftdgrep: use /* fallthrough */ as needed

On Thu, May 14, 2020 at 1:13 AM Tom Rini wrote: > > On Thu, May 14, 2020 at 01:05:37AM +0900, Masahiro Yamada wrote: > > Hi Tom, > > > > On Wed, May 13, 2020 at 11:42 PM Tom Rini wrote: > > > > > > On Tue, May 12, 2020 at 11:04:38PM -0400, Tom Rini wrote: > > > > On Mon, May 11, 2020 at

[RFC 4/6] dtoc: update tests to match new platdata

After using a new approach to link nodes when OF_PLATDATA is enabled the test cases need to be update. This patch updates the tests based on this new implementation. Signed-off-by: Walter Lozano --- tools/dtoc/test_dtoc.py | 123 ++-- 1 file changed, 81

[RFC 6/6] dtoc add test for cd-gpios

Add a test for dtoc taking into account the cd-gpios property. Signed-off-by: Walter Lozano --- tools/dtoc/dtoc_test_phandle_cd_gpios.dts | 42 + tools/dtoc/test_dtoc.py | 72 +++ 2 files changed, 114 insertions(+) create mode 100644

[RFC 3/6] dtoc: extend dtoc to use struct driver_info when linking nodes

In the current implementation, when dtoc parses a dtb to generate a struct platdata it converts the information related to linked nodes as pointers to struct platdata of destination nodes. By doing this, it makes difficult to get pointer to udevices created based on these information. This patch

[RFC 5/6] dtoc: update dtb_platdata to support cd-gpios

Currently dtoc does not support the property cd-gpios used to declare the gpios for card detect in mmc. This patch adds support to cd-gpios property. Signed-off-by: Walter Lozano --- tools/dtoc/dtb_platdata.py | 13 - tools/dtoc/test_dtoc.py| 2 +- 2 files changed, 9

Re: [PATCH 1/1] tools: ftdgrep: use /* fallthrough */ as needed

On Thu, May 14, 2020 at 01:05:37AM +0900, Masahiro Yamada wrote: > Hi Tom, > > On Wed, May 13, 2020 at 11:42 PM Tom Rini wrote: > > > > On Tue, May 12, 2020 at 11:04:38PM -0400, Tom Rini wrote: > > > On Mon, May 11, 2020 at 09:08:03PM +0200, Heinrich Schuchardt wrote: > > > > On 5/11/20 8:40 PM,

Re: [PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang

On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote: > Thanks. Have you already checked it on gen2? I think I have gen2 board to > test. Yes, I have both gen3 and gen2 boards. gen2 continues to work with this patch as well. > > ср, 13 мая 2020 г. в 22:55, Kurt Miller : > > > > > >

Re: [PATCH 1/1] tools: ftdgrep: use /* fallthrough */ as needed

On Thu, May 14, 2020 at 02:27:20AM +0900, Masahiro Yamada wrote: > On Thu, May 14, 2020 at 1:13 AM Tom Rini wrote: > > > > On Thu, May 14, 2020 at 01:05:37AM +0900, Masahiro Yamada wrote: > > > Hi Tom, > > > > > > On Wed, May 13, 2020 at 11:42 PM Tom Rini wrote: > > > > > > > > On Tue, May 12,

Re: [PATCH 0/2] mtd: spi-nand: Update Toshiba support

On Mon, May 11, 2020 at 1:36 AM Robert Marko wrote: > > This patch series updates the Toshiba SPI-NAND driver support to match > the Linux tree. > This imports 2 patches that add support for the new J series, as well > as adding x4 and QE enable to previously added TC58CVG2S0HRAIJ. > > Yoshio

[PATCH 2/4] rockchip: veyron: move board_early_init_f to _r (after reloc)

Previously veyron_init() was called in board_init() context, which is called after relocation. Moving it to veyron.c used board_early_init_f which is called way earlier, and causes veyron_init to hang. Using board_early_init_r instead fixes this. Fixes: b678f2790c ("rockchip: rk3288: Move

[PATCH 4/4] defconfig: veyron: no need for CONFIG_SPL_PINCTRL_FULL

Veyrons do not need full pinctrl support for SPL. The full pinctrl support does nothing when enabled with OF_PLATDATA, thus was already unused. This frees about 4kB of SPL size. Signed-off-by: Urja Rannikko --- configs/chromebit_mickey_defconfig | 3 +-- configs/chromebook_jerry_defconfig | 3

[PATCH 3/4] rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATA

gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang after f0921f5098 ("fdt: Sync up to the latest libfdt"). We use the same test that is used in spl_common_init on whether to call fdtdec_setup to unconditionally avoid linking in the fdt-using code when not necessary and thus

[PATCH 0/4] Making veyrons boot, 2020 edition

Hi, This is a series to make veyrons (tested on a veyron speedy), boot atleast to the u-boot prompt, the first 3 patches are necessary and the 4th one kinda just managed to catch this patch train ;) PS. Thanks to swiftgeek on IRC for some bisecting & testing, thus getting me curious enough to

[PATCH 1/4] rockchip: spl: veyron speedy boots from SPI

Apparently speedy was forgotten from this list of veyron devices. Fixes: 49105fb7ed ("rockchip: add common spl board file") Signed-off-by: Urja Rannikko --- arch/arm/mach-rockchip/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/spl.c

[PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang

Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process. Signed-off-by: Kurt Miller --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +

[RFC 0/6] improve OF_PLATDATA support

When using OF_PLATDATA dtbs are converted to C structs in order to save space as we can remove both dtbs and libraries from TPL/SPL binaries. This patchset tries to improve its support by overcoming some limitations in the current implementation First, the support for scan and check for valid

[RFC 1/6] dtoc: add support to scan drivers

Currently dtoc scans dtbs to convert them to struct platdata and to generate U_BOOT_DEVICE entries. These entries need to be filled with the driver name, but at this moment the information used is the compatible name present in the dtb. This causes that only nodes with a compatible name that

[RFC 2/6] core: extend struct driver_info to point to device

Currently when creating an U_BOOT_DEVICE entry a struct driver_info is declared, which contains the data needed to instantiate the device. However, the actual device is created at runtime and there is no proper way to get the device based on its struct driver_info. This patch extends struct

[PATCH] Makefile: remove m68k GCC 3.4 workaround

This code dates back to 2006, commit 483a0cf804df ("Fixes for gcc 3.4 based m68k toolchain,"). GCC 3.4 is so old. We do not support it. Signed-off-by: Masahiro Yamada --- Makefile | 7 --- 1 file changed, 7 deletions(-) diff --git a/Makefile b/Makefile index a9d58ca7a0..97fd492bc0 100644

Re: [PATCH v1 01/10] mips: octeon: Initial minimal support for the Marvell Octeon SoC

Am 02.05.20 um 10:59 schrieb Stefan Roese: > From: Aaron Williams > > This patch adds very basic support for the Octeon III SoCs. Only > CFI parallel NOR flash and UART is supported for now. > > Please note that the basic Octeon port does not include the DDR3/4 > initialization yet. This

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