On Wed, Jul 15, 2020 at 10:57:19PM +0530, Rayagonda Kokatanur wrote:
> From: Vikas Gupta
>
> Add optee based bnxt fw load driver.
> bnxt is Broadcom NetXtreme controller Ethernet card.
> This driver is used to load bnxt firmware binary using OpTEE.
>
> Signed-off-by: Vikas Gupta
>
On Wed, Jul 15, 2020 at 10:55:40PM +0530, Rayagonda Kokatanur wrote:
> From: Pramod Kumar
>
> Add FIT image its file.
>
> Signed-off-by: Pramod Kumar
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:57:20PM +0530, Rayagonda Kokatanur wrote:
> Enable tee and optee drivers.
>
> Signed-off-by: Vikas Gupta
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:53:01PM +0530, Rayagonda Kokatanur wrote:
> Enable pinctrl driver for ns3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:49:09PM +0530, Rayagonda Kokatanur wrote:
> Update MAINTAINERS for broadcom ns3 platform (TARGET_NS3).
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:53:02PM +0530, Rayagonda Kokatanur wrote:
> Add NS3 pads definitions.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:53:04PM +0530, Rayagonda Kokatanur wrote:
> Enable mmc commands for NS3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Sun, Jul 26, 2020 at 10:37:32PM +0530, Rayagonda Kokatanur wrote:
> Use device tree and UCLASS_IRQ driver to get following
> Generic Interrupt Controller (GIC) details,
>
> -GIC Distributor interface (GICD) base address and
> -GIC Redistributors (GICR) base address.
>
> Signed-off-by:
On Wed, Jul 15, 2020 at 10:55:39PM +0530, Rayagonda Kokatanur wrote:
> Enable FIT config for NS3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:53:06PM +0530, Rayagonda Kokatanur wrote:
> Enable EXT4 and FAT fs support for ns3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:53:07PM +0530, Rayagonda Kokatanur wrote:
> Enable sp805 watchdog driver for ns3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:53:03PM +0530, Rayagonda Kokatanur wrote:
> Enable BCM IPROC mmc driver ns3.
> Enable DMA for MMC Host to have better reads and writes.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:53:05PM +0530, Rayagonda Kokatanur wrote:
> Enable gpt commands for ns3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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The DT nodes on AM65x SoCs currently use a node name "interconnect" for
the various interconnects. This name is not following the DT schema, and
should simply be "bus". Update the fdt fixup logic to use both the
current and the expected corrected path names so that this logic won't
be broken with
Add clock support for SAMA7G5.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile |1 +
drivers/clk/at91/sama7g5.c | 1401
2 files changed, 1402 insertions(+)
create mode 100644 drivers/clk/at91/sama7g5.c
diff --git
Add sam9x60-pll driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Kconfig | 7 +
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-sam9x60-pll.c | 442 +
drivers/clk/at91/pmc.h
Add clk-peripheral compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +
drivers/clk/at91/clk-peripheral.c | 254 ++
drivers/clk/at91/pmc.h| 16 +++
3 files changed, 272 insertions(+)
Add clk-generic driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-generic.c | 202 +
drivers/clk/at91/pmc.h | 6 ++
3 files changed, 209 insertions(+)
Add generic clock ops to be used by every AT91 PMC driver
built on top of CCF.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/pmc.c | 71 ++
drivers/clk/at91/pmc.h | 2 ++
2 files changed, 73 insertions(+)
diff --git a/drivers/clk/at91/pmc.c
Add clk-programmable driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-programmable.c | 208
drivers/clk/at91/pmc.h | 17 +++
3 files changed, 226
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/clk-utmi.c | 71 -
Add clk-system driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-system.c | 112 ++
drivers/clk/at91/pmc.h| 3 ++
3 files changed, 116 insertions(+), 1
Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/clk-master.c | 178 +-
drivers/clk/at91/pmc.h| 5 ++
2 files changed,
Add pre-requisite headers for AT91 clock architecture. These
are based on already present files on Linux and will be used
by following commits for AT91 CCF clock drivers.
Signed-off-by: Claudiu Beznea
---
include/dt-bindings/clk/at91.h | 22
include/linux/clk/at91_pmc.h | 247
Add clk-master driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-master.c | 156 ++
drivers/clk/at91/pmc.h| 21 ++
3 files changed, 178 insertions(+),
Add clk-main driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-main.c | 387
drivers/clk/at91/pmc.h | 10 ++
3 files changed, 398 insertions(+), 1
Add sckc driver compatible with common clock framework. Driver
implements slow clock support for SAM9X60 compatible IPs (in this
list it is also present SAMA7G5's slow clock IP).
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/sckc.c | 172
Add helper for clock drivers. These will be used by following
commits in the process of switching AT91 clock drivers to CCF.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/pmc.c | 91 ++
drivers/clk/at91/pmc.h | 13
2 files changed,
clk_get_by_indexed_prop() retrieves a clock with dev member being set
with the pointer to the udevice for the clock controller driver. But
in case of CCF each struct clk object has set in dev member the reference
to its parent (the root of the clock tree is a fixed clock, every
node in clock tree
On Wed, Jul 15, 2020 at 10:49:03PM +0530, Rayagonda Kokatanur wrote:
> Add ddr memory definitions.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:49:06PM +0530, Rayagonda Kokatanur wrote:
> From: Bharat Gooty
>
> Add env variables and commands for booting Linux.
>
> Signed-off-by: Bharat Gooty
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
On Wed, Jul 15, 2020 at 10:49:05PM +0530, Rayagonda Kokatanur wrote:
> From: Bharat Kumar Reddy Gooty
>
> By default relocation happens to a higher address of DDR,
> i.e, DDR start + DDR size.
>
> U-Boot shall be used to collect the ramdump.
> Restrict U-Boot to use only the 16MB memory, so
On Wed, Jul 15, 2020 at 10:49:07PM +0530, Rayagonda Kokatanur wrote:
> From: Bharat Gooty
>
> Add support for flashing images into QSPI and eMMC.
>
> Signed-off-by: Bharat Gooty
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
On Wed, Jul 15, 2020 at 10:49:08PM +0530, Rayagonda Kokatanur wrote:
> Add README doc for bcmns3 platform.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:48:58PM +0530, Rayagonda Kokatanur wrote:
> Add NS3 memory definitions.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:49:02PM +0530, Rayagonda Kokatanur wrote:
> Enables the Generic Interrupt Controller (GIC) V3
> Interrupt Translation Service (ITS) Locality-specific Peripheral
> Interrupts (LPI) configuration table and LPI table.
>
> Signed-off-by: Rayagonda Kokatanur
>
On Wed, Jul 15, 2020 at 10:49:04PM +0530, Rayagonda Kokatanur wrote:
> Add both DRAM banks memory information and
> the corresponding MMU page table mappings.
>
> Signed-off-by: Bharat Kumar Reddy Gooty
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master,
On Wed, Jul 15, 2020 at 10:55:41PM +0530, Rayagonda Kokatanur wrote:
> From: Pramod Kumar
>
> Add development keys used in FIT.
>
> Signed-off-by: Pramod Kumar
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Sun, Jul 26, 2020 at 10:37:33PM +0530, Rayagonda Kokatanur wrote:
> Use device tree and UCLASS_SYSCON driver to get
> Generic Interrupt Controller (GIC) lpi address and
> maximum GIC redistributors count.
>
> Also update Kconfig to select REGMAP and SYSCON when
> GIC_V3_ITS is enabled.
>
>
On Tue, May 05, 2020 at 11:26:47PM +0530, Rayagonda Kokatanur wrote:
> As no gpio.h is defined for this architecture, to avoid
> compilation failure, do not include for
> arch bcmns3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
On Wed, Jul 15, 2020 at 10:48:55PM +0530, Rayagonda Kokatanur wrote:
> Add support for Broadcom Northstar 3 SoC.
> NS3 is a octo-core 64-bit ARMv8 Cortex-A72 processors
> targeting a broad range of networking applications.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
On Tue, May 05, 2020 at 11:26:46PM +0530, Rayagonda Kokatanur wrote:
> Add gpio driver support for Broadcom iproc-based socs.
>
> Signed-off-by: Rayagonda Kokatanur
> Signed-off-by: Sheetal Tigadoli
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:48:57PM +0530, Rayagonda Kokatanur wrote:
> Enable clock subsystem for ns3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:48:56PM +0530, Rayagonda Kokatanur wrote:
> Add L3 memory flush support for NS3.
>
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jul 15, 2020 at 10:48:59PM +0530, Rayagonda Kokatanur wrote:
> From: Abhishek Shah
>
> Add API to save boot parameters passed from BL31
>
> Use assembly implementation of save_boot_params instead of c function.
> Because generally ATF does not set up SP_EL2 on exiting.
> Thus, usage of
On Wed, Jul 15, 2020 at 10:49:00PM +0530, Rayagonda Kokatanur wrote:
> Default "reset" from U-Boot to L3 reset.
> "reset" command with argument will trigger L1 reset.
>
> Signed-off-by: Rajesh Ravi
> Signed-off-by: Bharat Kumar Reddy Gooty
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by:
On Wed, Jul 15, 2020 at 10:49:01PM +0530, Rayagonda Kokatanur wrote:
> U-boot programs the GIC LPI configuration tables and enables
> the LPI table.
>
> Signed-off-by: Bharat Kumar Reddy Gooty
> Signed-off-by: Rayagonda Kokatanur
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
Hi,
The latest master (423e08cb7701 (origin/master, origin/HEAD) Merge
branch '2020-07-28-misc-soc-improvements') seems to be broken for
HiFive Unleashed.
It already has Bin's fix for unleashed.
a0018fc8209c riscv: Make SiFive HiFive Unleashed board boot again
dram start and size is corrupted
Check pointer returned by dev_get_parent().
Signed-off-by: Claudiu Beznea
---
drivers/clk/clk-uclass.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 70df9d410f4c..aa1f11a27c41 100644
--- a/drivers/clk/clk-uclass.c
+++
Do not disable clock if it is a critical one.
Signed-off-by: Claudiu Beznea
---
drivers/clk/clk-uclass.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index b390a6b01c06..958a9490bee2 100644
--- a/drivers/clk/clk-uclass.c
+++
In common clock framework the relation b/w parent and child clocks is
determined based on the udevice parent/child information. A clock
parent could be changed based on devices needs. In case this is happen
the functionalities for clock who's parent is changed are broken. Add
a function that
The purpose of this series is to add clock support for SAMA7G5.
Allong with this, clock drivers were switched to CCF and aligned
with their corresponding versions present in Linux.
Some changes were done for CCF, patches 1, 2, 4, 5, 6 (I don't know
if they were as is by intention of a fixes tag is
Clock re-parenting is not binding the clock's device to its new
parent device, it only calls the clock's ops->set_parent() API. The
changes in this commit re-parent the clock device to its new parent
so that subsequent operations like clk_get_parent() to point to the
proper parent.
Signed-off-by:
Check hw and hw->dev before dereference it.
Signed-off-by: Claudiu Beznea
---
drivers/clk/clk.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 0f55ba751c0f..9fa18e342eaf 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -57,6 +57,9 @@
Move clock code to compat.c to allow switching to CCF
without mixing CCF code with non CCF code. This prepares the
field for next commits.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 13 +-
drivers/clk/at91/clk-generated.c | 178 ---
Add clk-utmi driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-utmi.c | 165
drivers/clk/at91/pmc.h | 3 +
3 files changed, 169 insertions(+)
create mode
If an exception occurs, the relocated program counter and return address
are required for an analysis.
With this patch you get:
=> exception undefined
Unhandled exception: Illegal instruction
EPC: 80595908 RA: 8059c0c6 TVAL: 8030c01e
EPC: 80007908
On Wed, Jul 29, 2020 at 07:56:09AM +, Patrice CHOTARD wrote:
> Hi Tom,
>
> Please pull the STM32 related patches for v2020.10: u-boot-stm32-20200729
>
> With the following changes:
> - fix SPL boot issue due to early dbgmcu_init() call
> - fix SPL boot issue due to
On Tue, Jul 28, 2020 at 11:35 PM wrote:
>
> From: Wig Cheng
>
> Fix compile warning messages.
>
> Signed-off-by: Wig Cheng
> ---
> configs/pico-imx6ul_defconfig | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/configs/pico-imx6ul_defconfig
On Tue, Jul 28, 2020 at 11:36 PM wrote:
>
> From: Wig Cheng
>
> - Remove pinmux definition from pico-imx6ul.c
> - Enable NET_RANDOM_ETHADDR for temporary solution, because micrel_ksz8xxx
> driver does not support DM_ETH yet, so cannot read MAC address directly.
>
> Before enable DM_ETH:
> Net:
On Thu, Jul 30, 2020 at 1:02 AM Philippe REYNES
wrote:
>
> Hi Patrick
>
> > From: Patrick Oppenlander
> >
> > This meant that the order of operations had to change. If we replace the
> > data property first then fail to add the data-size-unciphered property
> > the data will be ciphered again
On Tue, Jul 28, 2020 at 11:35 PM wrote:
>
> From: Wig Cheng
>
> Fix compile warning messages.
One more thing: you did a good job in writing the commit logs for the
other patches, but this one needs to be improved.
From: Jassi Brar
MAX3420 implements FullSpeed USB Device over SPI.
Another version MAX3421, also implements USB Host mode.
This driver should be good for the device mode of max3421 as well.
Signed-off-by: Jassi Brar
---
Changes since v2:
- used FIELD_PREP instead of simple left shift
On 7/30/20 9:15 AM, Fabio Estevam wrote:
On Tue, Jul 28, 2020 at 11:35 PM wrote:
From: Wig Cheng
Fix compile warning messages.
Signed-off-by: Wig Cheng
---
configs/pico-imx6ul_defconfig | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
The v2 series addresses review comments from Philippe Reynes:
* Use FIT_CIPHER_NODENAME instead of hard coding "cipher"
* Simplify handling of FDT_ERR_NOSPACE
* Simplify detection of previously ciphered data
The last two points are possible as I overlooked that the retry loop
handling ENOSPC in
From: Patrick Oppenlander
Previously mkimage would process any node matching the regex cipher.*
and apply the ciphers to the image data in the order they appeared in
the FDT. This meant that data could be inadvertently ciphered multiple
times.
Switch to processing a single cipher node which
From: Patrick Oppenlander
Also replace fdt_delprop/fdt_setprop with fdt_setprop as fdt_setprop can
replace an existing property value.
Signed-off-by: Patrick Oppenlander
---
tools/image-host.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git
From: Patrick Oppenlander
Previously, mkimage -F could be run multiple times causing already
ciphered image data to be ciphered again.
Signed-off-by: Patrick Oppenlander
---
tools/image-host.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git
Hi Tom,
On Sat, Jun 27, 2020 at 1:31 AM Tom Rini wrote:
>
> On Thu, Jun 25, 2020 at 10:57:09PM +0530, Rayagonda Kokatanur wrote:
> > Hi Tom,
> >
> >
> > On Sun, Apr 12, 2020 at 8:46 PM Rayagonda Kokatanur
> > wrote:
> > >
> > > On Thu, Apr 9, 2020 at 7:11 PM Tom Rini wrote:
> > > >
> > > > On
Hi Wig,
On Tue, Jul 28, 2020 at 11:07 PM wrote:
>
> From: Wig Cheng
>
> Here is the test commands:
>
> => ums 0 mmc 0
> UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x71
>
> Signed-off-by: Wig Cheng
> ---
> configs/pico-imx6ul_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
>
On Tue, Jul 28, 2020 at 11:04 PM wrote:
>
> From: Wig Cheng
>
> Before enable _DM_ETH:
> Net: FEC [PRIME]
>
> After enable DM_ETH:
> Net: eth0: ethernet@2188000
>
> Here is the test commands:
> => dhcp
> BOOTP broadcast 1
> DHCP client bound to address 10.88.88.152 (146 ms)
> ***
Hi Daniel,
On 24.07.20 15:56, Daniel Schwierzeck wrote:
Am Donnerstag, den 23.07.2020, 12:17 +0200 schrieb Stefan Roese:
From: Suneel Garapati
Adds support for SPI controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel
On Thu, Jul 30, 2020 at 3:17 AM Philippe REYNES
wrote:
>
> As for the second patch, I think that the loop is not an issue because
> it always start with "fresh/clean" value (using a backup file).
>
> So I am not sure that changes in this function are needed.
>
OK, I overlooked this.
I will
From: Patrick Oppenlander
This patch addresses issue #2 for signed configurations.
-8<-
Including the image cipher properties in the configuration signature
prevents an attacker from modifying cipher, key or iv properties.
Signed-off-by: Patrick Oppenlander
---
tools/image-host.c |
From: Patrick Oppenlander
The external data is located after the mmapped FDT pointed to by
'old_fdt', not in the newly created FDT we are importing into at 'fdt'.
Signed-off-by: Patrick Oppenlander
---
tools/fit_image.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
The sgmii mode init flow is almost the same for all mediatek SoC, the
only difference is the register offset(SGMSYS_GEN2_SPEED) is 0x2028
in the old chip(mt7622) but changed to 0x128 for the newer chip(mt7629
and the following chips).
Signed-off-by: MarkLee
---
V2: use driver private data from
This patch series enable MT7629 sgmii mode with mt7531 switch support,
1. enable mt7629 sgmii mode support in mediatek eth driver
2. enable mt7629 ethernet dts node with sgmii mode and mt7531
switch support
Change since V1:
- use driver private data from dts to decide
Heinrich,
On Thu, Jul 23, 2020 at 05:54:27PM +0200, Heinrich Schuchardt wrote:
> On 22.07.20 08:05, AKASHI Takahiro wrote:
> > In this commit, skeleton functions for capsule-related API's are
> > added under CONFIG_EFI_UPDATE_CAPSULE configuration.
> > Detailed implementation for a specific
Hi Simon,
On 28.07.2020 21:58, Simon Glass wrote:
Hi Ovidiu,
On Tue, 21 Jul 2020 at 10:43, Ovidiu Panait wrote:
Hi Simon,
On 21.07.2020 17:17, Simon Glass wrote:
On Mon, 20 Jul 2020 at 08:20, Ovidiu Panait wrote:
Factor out ppc-specific bdinfo setup from generic init sequence to
This patch enable sgmii mode and mt7531 switch support in mt7629
ethernet dts node
Signed-off-by: MarkLee
---
V2: no changes
---
arch/arm/dts/mt7629-rfb.dts | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/mt7629-rfb.dts
On 22.07.20 08:05, AKASHI Takahiro wrote:
> Summary
> ===
> 'UpdateCapsule' is one of runtime services defined in UEFI specification
> and its aim is to allow a caller (OS) to pass information to the firmware,
> i.e. U-Boot. This is mostly used to update firmware binary on devices by
>
Hello Simon,
On Tue, 2020-07-28 at 12:58 -0600, Simon Glass wrote:
> Hi Anastasiia,
>
> On Mon, 20 Jul 2020 at 05:02, Anastasiia Lukianenko <
> vicooo...@gmail.com> wrote:
> >
> > From: Peng Fan
> >
> > Introduce CONFIG_XEN to make U-Boot could be used as bootloader
> > for a virtual machine.
Hello Simon,
On Tue, 2020-07-28 at 12:58 -0600, Simon Glass wrote:
> On Mon, 20 Jul 2020 at 05:02, Anastasiia Lukianenko <
> vicooo...@gmail.com> wrote:
> >
> > From: Anastasiia Lukianenko
>
> Please add commit message
Ok, will add.
>
> >
> > Signed-off-by: Anastasiia Lukianenko <
> >
Configure DWC3’s cache type to ‘cacheable’ for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.
Signed-off-by: Ran Wang
---
Hi Tom,
Please pull the STM32 related patches for v2020.10: u-boot-stm32-20200729
With the following changes:
- fix SPL boot issue due to early dbgmcu_init() call
- fix SPL boot issue due to dcache memory region configuration
- add support of CONFIG_ENV_IS_IN_MMC
- add specific SD/eMMC
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
The FU540-C000 support in U-Boot is missing DM based reset driver,
and is handling reset's to sub-system within the prci driver itself.
The series here adds a generic DM reset driver for SiFive SoC's so as
to leverage the U-Boot's reset framework and binds the reset driver with
prci driver.
The
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register
Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.
Signed-off-by: Sagar Shrikant Kadam
Reviewed-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
configs/sifive_fu540_defconfig | 2 ++
This series cleans up the timer drivers in RISC-V and converts them to DM.
This series depends on [1]. This series needs to be tested! I have only tested
it on QEMU and the K210. Notably, this means that the HiFive and anything Andes
is completely untested. CI for this series is located at [2].
This merges the PLIC initialization code from two functions into one.
Signed-off-by: Sean Anderson
---
This patch builds but has NOT been tested.
(no changes since v1)
arch/riscv/lib/andes_plic.c | 58 -
1 file changed, 25 insertions(+), 33 deletions(-)
Another "virtual" clock (in the sense that it isn't configurable). This
could possibly be done as a clock in the device tree, but I think this is a
bit cleaner.
Signed-off-by: Sean Anderson
---
checkpatch still complains about this one, but I don't see any reason to
break it up even further. It
The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured
Use const for the variable nodes in ft_board_setup,
this patch follow fdt_fixup_mtdparts prototype and no more use stack.
Signed-off-by: Patrick Delaunay
---
board/st/stm32mp1/stm32mp1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/st/stm32mp1/stm32mp1.c
This converts the clint driver from the riscv-specific interface to be a
DM-based UCLASS_TIMER driver. We also need to re-add the initialization for
IPI back into the SPL code. This was previously implicitly done when the
timer was initialized. In addition, the SiFive DDR driver previously
This converts the PLMT driver from the riscv-specific timer interface to be
a DM-based UCLASS_TIMER driver.
Signed-off-by: Sean Anderson
---
This patch builds but has NOT been tested.
(no changes since v1)
arch/riscv/Kconfig | 4 ---
arch/riscv/dts/ae350_32.dts |
We may need to add a clock-frequency binding like for the K210.
Signed-off-by: Sean Anderson
---
This patch builds but has NOT been tested.
Changes in v2:
- Fix SiFive CLINT not getting tick-rate from rtcclk
arch/riscv/dts/fu540-c000-u-boot.dtsi | 8 ++--
AFAIK because the K210 clock driver does not come up until after
relocation, the clint will always use the clock-frequency parameter.
Ideally, it should update itself after relocation to take into account the
actual CPU frequency.
Signed-off-by: Sean Anderson
---
Changes in v2:
- New
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