Configure DWC3’s cache type to ‘cacheable’ for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.
Signed-off-by: Ran Wang
---
Change in
Hi Atish,
I just sent a patch to solve this issue.
https://patchwork.ozlabs.org/project/uboot/patch/20200805090053.11805-1-pragnesh.pa...@sifive.com/
Thanks,
Pragnesh
>-Original Message-
>From: U-Boot On Behalf Of Pragnesh Patel
>Sent: 04 August 2020 20:03
>To: Atish Patra ; Bin Meng
On Wed, Aug 5, 2020 at 5:01 PM Pragnesh Patel wrote:
>
> There may be a chance that board specific fix_fdt() will change the
> size of FDT blob so it's safe to call reserve_fdt() after fix_fdt()
> otherwise global data (gd) will overwrite with FDT blob values.
>
> Signed-off-by: Pragnesh Patel
>
Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
for booting up Cyclone5/Arria10.
Signed-off-by: Chee Hong Ang
---
Makefile | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 2629a74..13429a0 100644
--- a/Makefile
+++
On 8/5/20 7:57 AM, Stefan Roese wrote:
> Hi Marek,
>
> On 30.07.20 08:59, Bin Meng wrote:
>> Hi Marek,
>>
>> On Thu, Jul 30, 2020 at 2:32 PM Stefan Roese wrote:
>>>
>>> Hi Bin,
>>>
>>> On 21.07.20 10:46, Stefan Roese wrote:
These patches fix a few issues, found while porting the xHCI
The following changes since commit a2d051e7b6a8f87add1067d936bb0c805a47b0df:
Merge branch '2020-07-31-more-env-updates' (2020-07-31 10:13:07 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-sh.git master
for you to fetch changes up to
Hi Simon,
On 06/06/20 02:00AM, Pratyush Yadav wrote:
> Hi,
>
> This series is a re-spin of Jean-Jacques' earlier effort [0], the goal
> of which was to facilitate porting drivers from the Linux kernel. It
> adds the managed API, using the same API as Linux. It also adds support
> for regmap
Hi Rasmus,
On 05.08.20 10:47, Rasmus Villemoes wrote:
On 24/07/2020 23.14, Tom Rini wrote:
This converts the following to Kconfig:
CONFIG_SYS_MMC_ENV_DEV
CONFIG_SYS_MMC_ENV_PART
Yes, please! That's the only thing preventing us from running a vanilla
upstream U-Boot on a number of our
On Wed, Aug 5, 2020 at 3:11 AM Bin Meng wrote:
> On Tue, Aug 4, 2020 at 10:58 PM Heinrich Schuchardt
> wrote:
> > On 04.08.20 15:15, Bin Meng wrote:
> > > On Tue, Aug 4, 2020 at 7:02 PM Heinrich Schuchardt
> > > wrote:
> > >> On 04.08.20 03:46, Bin Meng wrote:
> > >>> On Tue, Aug 4, 2020 at
Hi
On 27/07/20 3:15 pm, Lokesh Vutla wrote:
> j7200-evm has minor differences with j721e-evm based on the IPs
> available in the SoC. Introduce separate build targets for j7200-evm
> to incorporate the differences.
>
> Signed-off-by: Lokesh Vutla
> ---
> board/ti/j721e/Kconfig | 53
There may be a chance that board specific fix_fdt() will change the
size of FDT blob so it's safe to call reserve_fdt() after fix_fdt()
otherwise global data (gd) will overwrite with FDT blob values.
Signed-off-by: Pragnesh Patel
---
common/board_f.c | 6 +++---
1 file changed, 3 insertions(+),
On 8/5/20 10:15 AM, Chee Hong Ang wrote:
> Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
> for booting up Cyclone5/Arria10.
>
> Signed-off-by: Chee Hong Ang
> ---
> Makefile | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Makefile b/Makefile
On 8/5/20 11:15 AM, Tan, Ley Foon wrote:
[...]
>>> diff --git a/Makefile b/Makefile
>>> index 2629a74..13429a0 100644
>>> --- a/Makefile
>>> +++ b/Makefile
>>> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
>> FORCE
>>> ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT
> -Original Message-
> From: Marek Vasut
> Sent: Wednesday, August 5, 2020 4:23 PM
> To: Ang, Chee Hong ; u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Tom Rini
> ; See, Chin Liang ; Tan, Ley
> Foon ; Chee, Tien Fong
> ; Lim, Elly Siew Chin
>
> Subject: Re: [PATCH v1] Makefile:
Hi Marek,
On 30.07.20 17:16, Stefan Roese wrote:
Hi Simon,
On 28.07.20 21:01, Simon Glass wrote:
Hi Stefan,
On Fri, 24 Jul 2020 at 04:09, Stefan Roese wrote:
Instead of using a fixed length pre-allocated array of regions, this
patch moves to dynamically allocating the regions based on the
Hi Simon,
On 12/06/20 05:38PM, Pratyush Yadav wrote:
> Hi,
>
> This is the 4th of a few series that are re-rolls of Jean-Jacques'
> earlier efforts. The goal is to facilitate porting drivers from the
> Linux kernel.
>
> This particular series is about reset controllers. It adds a managed API,
>
Hi Heinrich
> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
> Sent: Tuesday, August 04, 2020 7:10 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: u-boot@lists.denx.de; Heinrich Schuchardt
> Subject: [PATCH 1/1] cmd: exception: unaligned data access on RISC-V
>
> The command 'exception' can be used
On 24/07/2020 23.14, Tom Rini wrote:
> This converts the following to Kconfig:
>CONFIG_SYS_MMC_ENV_DEV
>CONFIG_SYS_MMC_ENV_PART
Yes, please! That's the only thing preventing us from running a vanilla
upstream U-Boot on a number of our boards where we have the defconfig
out of tree - we
Hi Heinrich
> >> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
> >> Sent: Tuesday, August 04, 2020 7:10 PM
> >> To: Rick Jian-Zhi Chen(陳建志)
> >> Cc: u-boot@lists.denx.de; Heinrich Schuchardt
> >> Subject: [PATCH 1/1] cmd: exception: unaligned data access on RISC-V
> >>
> >> The command
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 5, 2020 9:51 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Tan, Ley Foon
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1]
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 5, 2020 8:55 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Tan, Ley Foon
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1]
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 5, 2020 9:16 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Tan, Ley Foon
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1
On Sun, Aug 02, 2020 at 11:09:06PM -0700, Bin Meng wrote:
> From: Bin Meng
>
> It's better to keep all SPL related functions in the same spl.c.
>
> Signed-off-by: Bin Meng
> ---
>
> board/sifive/fu540/fu540.c | 33 -
> board/sifive/fu540/spl.c | 33
On Sun, Aug 02, 2020 at 11:09:05PM -0700, Bin Meng wrote:
> From: Bin Meng
>
> This option was enabled during the earlier U-Boot porting time. Now
> we already have the OTP driver in place and the unique MAC address
> is read from the OTP, there is no need to turn on this option.
>
>
> -Original Message-
> From: Chee, Tien Fong
> Sent: Tuesday, August 4, 2020 6:02 PM
> To: u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Marek Vasut
> ; See, Chin Liang ; Tan, Ley
> Foon ; Lim, Elly Siew Chin
> ; Ang, Chee Hong
> ; Chee, Tien Fong
> Subject: [PATCH] ddr: socfpga:
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 5, 2020 9:16 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Tan, Ley Foon
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1
Hi Heinrich,
On Thu, Aug 06, 2020 at 10:15:28AM +0800, Rick Chen wrote:
> Hi Heinrich
>
> > >> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
> > >> Sent: Tuesday, August 04, 2020 7:10 PM
> > >> To: Rick Jian-Zhi Chen(陳建志)
> > >> Cc: u-boot@lists.denx.de; Heinrich Schuchardt
> > >>
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, August 03, 2020 2:09 PM
> To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List
> Cc: Bin Meng
> Subject: [PATCH 3/6] riscv: sifive/fu540: spl: Rename soc_spl_init()
>
> From: Bin Meng
>
> spl_soc_init() seems to be a better
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.
Signed-off-by: Chee Hong Ang
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi| 4
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4
Hi Pragnesh
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Wednesday, August 05, 2020 5:01 PM
> To: atish.pa...@wdc.com; bmeng...@gmail.com; u-boot@lists.denx.de;
> anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick Jian-Zhi Chen(陳建志)
> Cc: paul.walms...@sifive.com; Pragnesh
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/misc.h | 5
Hi Rick,
>-Original Message-
>From: Rick Chen
>Sent: 06 August 2020 08:22
>To: Pragnesh Patel
>Cc: U-Boot Mailing List ; Atish Patra
>; Bin Meng ; Anup Patel
>; Sagar Kadam ; Paul
>Walmsley ( Sifive) ; Simon Glass
>; ovpan...@gmail.com; swar...@nvidia.com;
>patrick.delau...@st.com;
On Wed, Aug 05, 2020 at 02:04:02PM +0100, David Woodhouse wrote:
>
>
> On 5 August 2020 13:51:43 BST, Tom Rini wrote:
> >On Wed, Aug 05, 2020 at 11:07:15AM +0200, Stefan Roese wrote:
> >> Hi Rasmus,
> >>
> >> On 05.08.20 10:47, Rasmus Villemoes wrote:
> >> > On 24/07/2020 23.14, Tom Rini
Add .load callback for the 'nowhere' environment driver. This is useful
for when the 'nowhere' driver is used in combination with other drivers
and should be used to load the default environment.
Signed-off-by: Marek Vasut
Reviewed-by: Tom Rini
---
V2: No change
---
env/nowhere.c | 6 ++
1
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.
Signed-off-by: Chee Hong Ang
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4
On 05.08.20 15:34, Marek Vasut wrote:
> The i.MX6/i.MX7 is capable of booting a secondary "redundant" system
> image in case the primary one is corrupted. The user can force this
> boot mode as well by explicitly setting SRC GPR10 bit 30. This can be
> potentially useful when upgrading the
On Wed, Aug 05, 2020 at 02:22:35PM +0100, David Woodhouse wrote:
> On 5 August 2020 14:14:58 BST, Tom Rini wrote:
> >On Wed, Aug 05, 2020 at 02:04:02PM +0100, David Woodhouse wrote:
> >>
> >>
> >> On 5 August 2020 13:51:43 BST, Tom Rini wrote:
> >> >On Wed, Aug 05, 2020 at 11:07:15AM +0200,
On 5 August 2020 14:14:58 BST, Tom Rini wrote:
>On Wed, Aug 05, 2020 at 02:04:02PM +0100, David Woodhouse wrote:
>>
>>
>> On 5 August 2020 13:51:43 BST, Tom Rini wrote:
>> >On Wed, Aug 05, 2020 at 11:07:15AM +0200, Stefan Roese wrote:
>> >> Hi Rasmus,
>> >>
>> >> On 05.08.20 10:47, Rasmus
The i.MX6/i.MX7 is capable of booting a secondary "redundant" system
image in case the primary one is corrupted. The user can force this
boot mode as well by explicitly setting SRC GPR10 bit 30. This can be
potentially useful when upgrading the bootloader itself. Expose this
functionality to the
Add new 'getprisec' subcommand to 'bmode' command, which sets the return
value of the 'bmode' command to either 0 if the system booted from primary
copy or to 1 if the system booted from secondary copy. This can be used
e.g. in 'test' command to determine which copy of the system is running.
Implement the 'getprisec' subcommand of 'bmode' command for i.MX7 by
reading out the SRC GPR10 bit 30. This bit is either set by the BootROM
if it switched to the secondary copy due to primary copy being corrupted
OR it can be overridden by the user.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
On 19/07/2020 20:56, Simon Glass wrote:
Hi,
> On x86 various files that need to be created by binman. It does not make
> sense to enumerate these in the Makefile. They are described in the
> configuration (devicetree) for each board and we can simply run binman
> (always) to generate them.
>
>
Hi Oliver,
On Wed, 5 Aug 2020 15:47:07 +0200
Oliver Graute oliver.gra...@gmail.com wrote:
> Hello,
>
> I try to get my I2C working on imx8qm. But I run into this issue:
>
> => i2c bus
> Bus 3: i2c@5a83
> => i2c dev 3
> Setting bus to 3
> Failed to enable ipg clk
> Failure changing bus
Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers,
which are optional, but can be used to fill in the byte lane delays.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: NXP i.MX U-Boot Team
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/include/asm/arch-mx7/mx7-ddr.h | 16
On Wed, Aug 05, 2020 at 03:29:55PM +0200, Marek Vasut wrote:
> Add .load callback for the 'nowhere' environment driver. This is useful
> for when the 'nowhere' driver is used in combination with other drivers
> and should be used to load the default environment.
>
> Signed-off-by: Marek Vasut
>
On 05. 08. 20 14:37, Michal Simek wrote:
> There is no reason to bind psci driver if U-Boot runs in EL3 because
> SMC/HVC instructions can't be called. That's why detect this state and
> don't let user to crash from prompt by performing reset or poweroff
> commands (if enabled).
>
>
Hi Marek,
On 05.08.20 15:34, Marek Vasut wrote:
> Add the basic differentiation between i.MX6 and i.MX7 into the bmode
> command, the mechanism really works almost the same on both platforms.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: NXP i.MX U-Boot Team
> Cc: Peng Fan
> Cc:
On 05/08/20 2:20 pm, Vignesh Raghavendra wrote:
> Hi
>
> On 27/07/20 3:15 pm, Lokesh Vutla wrote:
>> j7200-evm has minor differences with j721e-evm based on the IPs
>> available in the SoC. Introduce separate build targets for j7200-evm
>> to incorporate the differences.
>>
>> Signed-off-by:
On 8/5/20 3:59 PM, Stefano Babic wrote:
> Hi Marek,
Hi,
> On 05.08.20 15:34, Marek Vasut wrote:
>> Add the basic differentiation between i.MX6 and i.MX7 into the bmode
>> command, the mechanism really works almost the same on both platforms.
>>
>> Signed-off-by: Marek Vasut
>> Cc: Fabio Estevam
On 05.08.20 16:40, Marek Vasut wrote:
> On 8/5/20 3:59 PM, Stefano Babic wrote:
>> Hi Marek,
>
> Hi,
>
>> On 05.08.20 15:34, Marek Vasut wrote:
>>> Add the basic differentiation between i.MX6 and i.MX7 into the bmode
>>> command, the mechanism really works almost the same on both platforms.
>>>
Hi André,
On Wed, 5 Aug 2020 at 08:20, André Przywara wrote:
>
> On 19/07/2020 20:56, Simon Glass wrote:
>
> Hi,
>
> > On x86 various files that need to be created by binman. It does not make
> > sense to enumerate these in the Makefile. They are described in the
> > configuration (devicetree)
On 05/08/2020 16:05, Simon Glass wrote:
> Hi André,
>
> On Wed, 5 Aug 2020 at 08:20, André Przywara wrote:
>>
>> On 19/07/2020 20:56, Simon Glass wrote:
>>
>> Hi,
>>
>>> On x86 various files that need to be created by binman. It does not make
>>> sense to enumerate these in the Makefile. They
> -Original Message-
> From: Chee, Tien Fong
> Sent: Wednesday, August 5, 2020 11:59 AM
> To: u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Marek Vasut
> ; See, Chin Liang ; Tan, Ley
> Foon ; Lim, Elly Siew Chin
> ; Ang, Chee Hong
> ; Chee, Tien Fong
> Subject: [PATCH] ddr: socfpga:
> -Original Message-
> From: Chee, Tien Fong
> Sent: Tuesday, August 4, 2020 6:02 PM
> To: u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Marek Vasut
> ; See, Chin Liang ; Tan, Ley
> Foon ; Lim, Elly Siew Chin
> ; Ang, Chee Hong
> ; Chee, Tien Fong
> Subject: [PATCH] ddr: socfpga:
QSPI driver perform chip select on every flash read/write
access. The driver need to disable/enable the QSPI controller
while performing chip select. This may cause some data lost
especially the QSPI controller is configured to run at slower
speed as it may take longer time to access the flash
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 5, 2020 5:33 PM
> To: u-boot@lists.denx.de
> Cc: Phil Edworthy ; Vignesh R
> ; Tom Rini ; See, Chin Liang
> ; Tan, Ley Foon ; Ang,
> Chee Hong ; Chee, Tien Fong
> ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1] spi:
On 8/5/20 10:47 AM, Rick Chen wrote:
> Hi Heinrich
>
>> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de]
>> Sent: Tuesday, August 04, 2020 7:10 PM
>> To: Rick Jian-Zhi Chen(陳建志)
>> Cc: u-boot@lists.denx.de; Heinrich Schuchardt
>> Subject: [PATCH 1/1] cmd: exception: unaligned data access on
From: Chin Liang See
In current implementation, any exception would trigger a CPU reset.
But a bad written SPL would cause infinite loop where the system
will reload the same SPL instead of loading factory safe image.
Hence this patch is to ensure any exception will cause a hang. At this
Hi,
On 05/08/20 3:48 pm, Chee Hong Ang wrote:
If the QSPI clock is not set (read as 0), QSPI driver probe shall fail
and prevent further QSPI access.
Signed-off-by: Chee Hong Ang
---
drivers/spi/cadence_qspi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
There is no reason to have name variable saved in BSS section when it
doesn't need to be really used. That's why remove static from variable
definition and use strdup() to duplicate string with exact size from malloc
area instead.
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c |
From: Ibai Erkiaga
Remove chip_id function and integrate the firmware call in the
zynqmp_get_silicon_idcode_name function. The change avoids querying the
firmware twice and makes the code bit more clear.
Signed-off-by: Ibai Erkiaga
Signed-off-by: Michal Simek
---
Enable this driver to be able to work with i2c based eeproms on Versal.
Signed-off-by: Michal Simek
---
configs/xilinx_versal_virt_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/xilinx_versal_virt_defconfig
b/configs/xilinx_versal_virt_defconfig
index
Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.
Signed-off-by: Chee Hong Ang
---
.../include/mach/reset_manager_soc64.h | 1 +
arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++
Show reset information such as reset types (cold/warm) and
which events triggered the reset.
Chee Hong Ang (2):
arm: socfpga: soc64: Add SDM triggered warm reset bit mask
arm: socfpga: soc64: Show reset state in SPL
.../include/mach/reset_manager_soc64.h | 12 ++--
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat
register when checking for HPS warm reset status.
Refactor the warm reset mask macro for clarity purpose.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 11 +--
1 file
On 5 August 2020 14:14:58 BST, Tom Rini wrote:
>On Wed, Aug 05, 2020 at 02:04:02PM +0100, David Woodhouse wrote:
>>
>>
>> On 5 August 2020 13:51:43 BST, Tom Rini wrote:
>> >On Wed, Aug 05, 2020 at 11:07:15AM +0200, Stefan Roese wrote:
>> >> Hi Rasmus,
>> >>
>> >> On 05.08.20 10:47, Rasmus
Hi Simon,
On 31.07.20 20:44, Simon Glass wrote:
Hi Stefan,
On Thu, 30 Jul 2020 at 10:26, Stefan Roese wrote:
Hi Simon,
On 28.07.20 21:01, Simon Glass wrote:
Hi Stefan,
On Fri, 24 Jul 2020 at 04:09, Stefan Roese wrote:
From: Suneel Garapati
Adds support for PCI ECAM/PEM controllers
This is another in series of patches which remove ad-hoc reset_cpu()
hacks from board files. This one is for iMX7, so implement default
reset_cpu() there to prevent it from showing up in board files.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: NXP i.MX U-Boot Team
Cc: Peng Fan
Cc:
Add the basic differentiation between i.MX6 and i.MX7 into the bmode
command, the mechanism really works almost the same on both platforms.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: NXP i.MX U-Boot Team
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/include/asm/mach-imx/sys_proto.h | 6
Hi Simon,
On 31.07.20 16:25, Stefan Roese wrote:
Hi Simon,
On 28.07.20 21:01, Simon Glass wrote:
On Fri, 24 Jul 2020 at 04:09, Stefan Roese wrote:
From: Suneel Garapati
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2
platforms.
Signed-off-by: Suneel Garapati
Hello,
I try to get my I2C working on imx8qm. But I run into this issue:
=> i2c bus
Bus 3: i2c@5a83
=> i2c dev 3
Setting bus to 3
Failed to enable ipg clk
Failure changing bus number (-524)
Some idea how to fix that?
I'am using U-Boot 2020.04
Best regards,
Oliver
Enable sysreset support for Agilex platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/Kconfig | 2 +-
drivers/sysreset/Kconfig | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b8a32c38d..105b5f08a9 100644
---
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 5, 2020 5:54 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Tan, Ley Foon
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1]
From: Ibai Erkiaga
Current implementation for getting chip ID uses either raw access on EL3
or a SMC call to get the silicon information. Following change
simplifies the code using always the firmware driver.
Signed-off-by: Ibai Erkiaga
Signed-off-by: Michal Simek
---
From: Ibai Erkiaga
Current algorithm used to get the silicon name is bit complicated and
hard to follow. Updated to use more straightforward mechanism based on
the Device ID code table (Table 1-2). The full IDCODE register is used
(except device revision bits [31:28]) to get the device name and
From: Ibai Erkiaga
Modify the board init function to allow getting the chip ID when U-Boot
proper is executed at EL3.
Signed-off-by: Ibai Erkiaga
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
From: Ibai Erkiaga
Current IPI module register description is not align with IPI HW. The
registers with the wrong offset are not used so it does not cause real
issues. This patch aligns the register description.
Additionally comments added to explain why recv function does not check
any flag
Hi,
This patch series is intended to cleanup the functions used to get
the silicon name for ZynqMPSoC devices. It make use the firmware driver
rather than SMC call and impements more understandable agorithm to
compute the device name.
Thanks,
Ibai/Michal
Ibai Erkiaga (7):
xilinx: zynqmp:
From: Ibai Erkiaga
Removes duplicated definition of PAYLOAD_ARG_CNT and define it in the
firmware driver. Additionally fixes payload buffer declarations without
macro usage
Signed-off-by: Ibai Erkiaga
Signed-off-by: Michal Simek
---
arch/arm/mach-versal/include/mach/sys_proto.h | 2 --
From: Ibai Erkiaga
This patch merges ZynqMP firmware calls under xilinx_pm_request in order
to make trainsparent the EL. Calls at EL3 are send through IPI messages
and EL2 through SMC calls.
The EL2 call uses fixed payload and arg size as the EL3 call. The
firmware is capable to handle
On 05.08.20 13:45, Sean Anderson wrote:
> On 8/3/20 2:20 PM, Heinrich Schuchardt wrote:
>> On 03.08.20 16:08, Sean Anderson wrote:
>>> Maybe. Because we are configuring the PLL, the CPU clock is temporarily
>>> set to the in0 oscillator, so the timer would give an incorrect delay.
>>> However, it
On Sun, Jul 26, 2020 at 08:27:35PM -0600, Simon Glass wrote:
> At present if CONFIG_LOG enabled, putting LOG_DEBUG at the top of a file
> (before log.h inclusion) causes _log() to be executed for every log()
> call, regardless of the build- or run-time logging level.
>
> However there is no
On Wed, Aug 05, 2020 at 02:54:05PM +0200, Heinrich Schuchardt wrote:
> On 05.08.20 14:18, Tom Rini wrote:
> > On Sun, Jul 26, 2020 at 08:27:35PM -0600, Simon Glass wrote:
> >
> >> At present if CONFIG_LOG enabled, putting LOG_DEBUG at the top of a file
> >> (before log.h inclusion) causes _log()
> Hi,
>
> On 05/08/20 3:48 pm, Chee Hong Ang wrote:
> > If the QSPI clock is not set (read as 0), QSPI driver probe shall fail
> > and prevent further QSPI access.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > drivers/spi/cadence_qspi.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> >
There is no reason to bind psci driver if U-Boot runs in EL3 because
SMC/HVC instructions can't be called. That's why detect this state and
don't let user to crash from prompt by performing reset or poweroff
commands (if enabled).
Signed-off-by: Michal Simek
---
Maybe there is a better way how
On 05.08.20 14:18, Tom Rini wrote:
> On Sun, Jul 26, 2020 at 08:27:35PM -0600, Simon Glass wrote:
>
>> At present if CONFIG_LOG enabled, putting LOG_DEBUG at the top of a file
>> (before log.h inclusion) causes _log() to be executed for every log()
>> call, regardless of the build- or run-time
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/misc.h | 5
Octeon TX2 sets the TB100_EN bit in the config register. We need to use
a fixed 100MHz clock for this as well to work properly.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Suneel Garapati
Cc: Chandrakala Chavva
Cc: Jagan Teki
---
drivers/spi/octeon_spi.c | 5 -
1 file changed, 4
> > -Original Message-
> > From: Ang, Chee Hong
> > Sent: Wednesday, August 5, 2020 5:54 PM
> > To: u-boot@lists.denx.de
> > Cc: Marek Vasut ; Simon Goldschmidt
> > ; Tom Rini ; See,
> > Chin Liang ; Tan, Ley Foon
> > ; Ang, Chee Hong ;
> > Chee, Tien Fong ; Lim, Elly Siew Chin
> >
> >
On 8/3/20 2:20 PM, Heinrich Schuchardt wrote:
> On 03.08.20 16:08, Sean Anderson wrote:
>> Maybe. Because we are configuring the PLL, the CPU clock is temporarily
>> set to the in0 oscillator, so the timer would give an incorrect delay.
>> However, it would probably be fine even if incorrect. The
There is no reason to build private function when
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET is not defined. There is already weak
function which handles default case properly.
Signed-off-by: Michal Simek
---
board/xilinx/common/board.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff
Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG to enable/disable updating
variables with run time information.
Signed-off-by: Michal Simek
---
arch/arm/Kconfig | 3 +++
board/xilinx/versal/board.c | 3 +++
board/xilinx/zynq/board.c| 8
board/xilinx/zynqmp/zynqmp.c | 3 +++
On Wed, Aug 05, 2020 at 11:07:15AM +0200, Stefan Roese wrote:
> Hi Rasmus,
>
> On 05.08.20 10:47, Rasmus Villemoes wrote:
> > On 24/07/2020 23.14, Tom Rini wrote:
> > > This converts the following to Kconfig:
> > > CONFIG_SYS_MMC_ENV_DEV
> > > CONFIG_SYS_MMC_ENV_PART
> >
> > Yes, please!
> -Original Message-
> From: Marek Vasut
> Sent: Wednesday, August 5, 2020 5:18 PM
> To: Tan, Ley Foon ; Ang, Chee Hong
> ; u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Tom Rini
> ; See, Chin Liang ; Chee,
> Tien Fong ; Lim, Elly Siew Chin
>
> Subject: Re: [PATCH v1] Makefile:
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 5, 2020 6:08 PM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Chee, Tien Fong
> ; Lim, Elly Siew Chin
>
> Subject: RE: [PATCH v1] sysreset:
If the QSPI clock is not set (read as 0), QSPI driver probe shall fail
and prevent further QSPI access.
Signed-off-by: Chee Hong Ang
---
drivers/spi/cadence_qspi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index
On 8/5/20 11:26 AM, Tan, Ley Foon wrote:
Hi,
[...]
> diff --git a/Makefile b/Makefile
> index 2629a74..13429a0 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
FORCE
> ifneq ($(CONFIG_ARCH_SOCFPGA),)
env_set..() can failed that's why check return status and report it back to
make sure that user is aware that's something went wrong.
Signed-off-by: Michal Simek
---
board/xilinx/common/board.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git
On 5 August 2020 13:51:43 BST, Tom Rini wrote:
>On Wed, Aug 05, 2020 at 11:07:15AM +0200, Stefan Roese wrote:
>> Hi Rasmus,
>>
>> On 05.08.20 10:47, Rasmus Villemoes wrote:
>> > On 24/07/2020 23.14, Tom Rini wrote:
>> > > This converts the following to Kconfig:
>> > >
Rename the driver from S10 to SoC64 because Intel Agilex platform
also using the this SYSRESET SoCFPGA driver for S10.
Signed-off-by: Chee Hong Ang
---
arch/arm/Kconfig| 2 +-
drivers/sysreset/Kconfig
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