[PATCH v2 07/21] mips: mtmips: add support for MediaTek MT7620 SoC
This patch adds support for MediaTek MT7620 SoC.
All files are dedicated for u-boot.
Signed-off-by: Weijie Gao
---
v2 changes: remove use of common.h
---
arch/mips/dts/mt7620-u-boot.dtsi | 14 +
arch/mips/dts/mt7620.dtsi | 296 ++
arch/mips/mach-mtmips/Kconfig | 18 ++
arch/mips/mach-mtmips/Makefile| 1 +
.../mach-mtmips/include/mach/mt7620-sysc.h| 54
arch/mips/mach-mtmips/mt7620/Kconfig | 54
arch/mips/mach-mtmips/mt7620/Makefile | 10 +
arch/mips/mach-mtmips/mt7620/dram.c | 113 +++
arch/mips/mach-mtmips/mt7620/init.c | 193
arch/mips/mach-mtmips/mt7620/lowlevel_init.S | 53
arch/mips/mach-mtmips/mt7620/mt7620.h | 103 ++
arch/mips/mach-mtmips/mt7620/serial.c | 36 +++
arch/mips/mach-mtmips/mt7620/sysc.c | 172 ++
include/configs/mt7620.h | 46 +++
14 files changed, 1163 insertions(+)
create mode 100644 arch/mips/dts/mt7620-u-boot.dtsi
create mode 100644 arch/mips/dts/mt7620.dtsi
create mode 100644 arch/mips/mach-mtmips/include/mach/mt7620-sysc.h
create mode 100644 arch/mips/mach-mtmips/mt7620/Kconfig
create mode 100644 arch/mips/mach-mtmips/mt7620/Makefile
create mode 100644 arch/mips/mach-mtmips/mt7620/dram.c
create mode 100644 arch/mips/mach-mtmips/mt7620/init.c
create mode 100644 arch/mips/mach-mtmips/mt7620/lowlevel_init.S
create mode 100644 arch/mips/mach-mtmips/mt7620/mt7620.h
create mode 100644 arch/mips/mach-mtmips/mt7620/serial.c
create mode 100644 arch/mips/mach-mtmips/mt7620/sysc.c
create mode 100644 include/configs/mt7620.h
diff --git a/arch/mips/dts/mt7620-u-boot.dtsi b/arch/mips/dts/mt7620-u-boot.dtsi
new file mode 100644
index 00..ed8425719b
--- /dev/null
+++ b/arch/mips/dts/mt7620-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao
+ */
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/mips/dts/mt7620.dtsi b/arch/mips/dts/mt7620.dtsi
new file mode 100644
index 00..03a80b7a70
--- /dev/null
+++ b/arch/mips/dts/mt7620.dtsi
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt7620-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ clk48m: clk48m@0 {
+ compatible = "fixed-clock";
+
+ clock-frequency = <4800>;
+
+ #clock-cells = <0>;
+ };
+
+ sysc: sysc@1000 {
+ compatible = "mediatek,mt7620-sysc";
+ reg = <0x1000 0x100>;
+ };
+
+ clkctrl: clkctrl@1030 {
+ compatible = "mediatek,mt7620-clk";
+ mediatek,sysc = <>;
+
+ #clock-cells = <1>;
+ };
+
+ rstctrl: rstctrl@1034 {
+ compatible = "mediatek,mtmips-reset";
+ reg = <0x1034 0x4>;
+ #reset-cells = <1>;
+ };
+
+ reboot: resetctl-reboot {
+ compatible = "resetctl-reboot";
+
+ resets = < SYS_RST>;
+ reset-names = "sysreset";
+ };
+
+ uartfull: uartfull@1500 {
+ compatible = "mediatek,mt7620-uart";
+ reg = <1500 0x100>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_gpio_pins>;
+
+ clocks = < CLK_UARTF>;
+
+ resets = < UARTF_RST>;
+ reset-names = "uartf";
+
+ clock-frequency = <4000>;
+
+ status = "disabled";
+ };
+
+ uartlite: uartlite@1c00 {
+ compatible = "mediatek,mt7620-uart";
+ reg = <0x1c00 0x100>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ clocks = < CLK_UARTL>;
+
+ resets = < UARTL_RST>;
+ reset-names = "uartl";
+
+ clock-frequency = <4000>;
+ };
+
+ pinctrl: pinctrl@1060 {
+ compatible = "mediatek,mt7620-pinctrl";
+ reg = <0x1060 0x4>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_default>;
+
+ state_default: pin_state {
+ sutif_pins {
+ groups = "sutif";
+ function = "none";
+ };
+ };
+
+ nand_pins: nand_pins {
+ groups = "nand";
+ function = "nand";
+ };
+
+
[PATCH v2 08/21] mips: mtmips: add two reference boards for mt7620
The mt7620_rfb board supports integrated 10/100M PHYs plus two external
giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.
The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
16MB SPI-NOR flash.
Signed-off-by: Weijie Gao
---
v2 changes: remove use of common.h
---
arch/mips/dts/Makefile | 2 +
arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts | 100 +++
arch/mips/dts/mediatek,mt7620-rfb.dts| 97 ++
arch/mips/mach-mtmips/mt7620/Kconfig | 17
board/mediatek/mt7620/Kconfig| 12 +++
board/mediatek/mt7620/MAINTAINERS| 9 ++
board/mediatek/mt7620/Makefile | 3 +
board/mediatek/mt7620/board.c| 6 ++
configs/mt7620_mt7530_rfb_defconfig | 58 +++
configs/mt7620_rfb_defconfig | 76 ++
10 files changed, 380 insertions(+)
create mode 100644 arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
create mode 100644 arch/mips/dts/mediatek,mt7620-rfb.dts
create mode 100644 board/mediatek/mt7620/Kconfig
create mode 100644 board/mediatek/mt7620/MAINTAINERS
create mode 100644 board/mediatek/mt7620/Makefile
create mode 100644 board/mediatek/mt7620/board.c
create mode 100644 configs/mt7620_mt7530_rfb_defconfig
create mode 100644 configs/mt7620_rfb_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index e82f96d4e4..7c42923134 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -14,6 +14,8 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
+dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) +=
gardena-smart-gateway-mt7688.dtb
dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
diff --git a/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
b/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
new file mode 100644
index 00..8bc3b1673a
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao
+ */
+
+/dts-v1/;
+
+#include
+#include "mt7620.dtsi"
+
+/ {
+ compatible = "mediatek,mt7620-mt7530-rfb", "mediatek,mt7620-soc";
+ model = "MediaTek MT7620-MT7530 RFB (MTKC712)";
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path =
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ state_default: pin_state {
+ pleds {
+ groups = "ephy led", "wled";
+ function = "led";
+ };
+
+ gpios {
+ groups = "pa", "uartf";
+ function = "gpio";
+ };
+ };
+
+ gsw_pins: gsw_pins {
+ mdio {
+ groups = "mdio";
+ function = "mdio";
+ };
+
+ rgmii1 {
+ groups = "rgmii1";
+ function = "rgmii1";
+ };
+ };
+};
+
+ {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <2500>;
+ reg = <0>;
+ };
+};
+
+ {
+ pa0_pull_low {
+ gpio-hog;
+ output-low;
+ gpios = <20 GPIO_ACTIVE_HIGH>;
+ };
+
+ pa1_pull_low {
+ gpio-hog;
+ output-low;
+ gpios = <21 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+ {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+
+ port5 {
+ phy-mode = "rgmii";
+ phy-addr = <5>;
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ mediatek,mt7530;
+ mediatek,mt7530-reset = < 10 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
diff --git a/arch/mips/dts/mediatek,mt7620-rfb.dts
b/arch/mips/dts/mediatek,mt7620-rfb.dts
new file mode 100644
index 00..616903e554
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7620-rfb.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao
+ */
+
+/dts-v1/;
+
+#include
+#include "mt7620.dtsi"
+
+/ {
+ compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc";
+ model = "MediaTek MT7620 RFB (WS2120)";
[PATCH v2 09/21] configs: mtmips: refresh for mt7628 based boards
Since mt7620 is added into Kconfig, the CONFIG_SOC_MT7628=y which is omitted by default must be added back, otherwise make xxx_defconfig for these boards will be configured for mt7620 platform. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao --- v2 changes: none --- configs/gardena-smart-gateway-mt7688_defconfig | 1 + configs/linkit-smart-7688_defconfig| 1 + configs/mt7628_rfb_defconfig | 1 + configs/vocore2_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 001a66d0f6..c03123f6e4 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xB CONFIG_ARCH_MTMIPS=y +CONFIG_SOC_MT7628=y CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index 437000b4c7..dd2524e4ec 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x4 CONFIG_SPL=y CONFIG_ARCH_MTMIPS=y +CONFIG_SOC_MT7628=y CONFIG_BOARD_LINKIT_SMART_7688=y CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig index 69025728b2..831e54e9f3 100644 --- a/configs/mt7628_rfb_defconfig +++ b/configs/mt7628_rfb_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x4 CONFIG_SPL=y CONFIG_ARCH_MTMIPS=y +CONFIG_SOC_MT7628=y CONFIG_BOARD_MT7628_RFB=y CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb" CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig index acb9abf1be..e255829366 100644 --- a/configs/vocore2_defconfig +++ b/configs/vocore2_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x4 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ARCH_MTMIPS=y +CONFIG_SOC_MT7628=y CONFIG_BOARD_VOCORE2=y CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y -- 2.17.1
[PATCH v2 10/21] serial: add uart driver for MediaTek MT7620 SoC
This patch adds uart support for MediaTek MT7620 and earlier SoCs.
The UART used by MT7620 is incompatible with the ns16550a driver.
All registers of this UART have different addresses. A special 16-bit
register for Divisor Latch is used to set the baudrate instead of the
original two 8-bit registers (DLL and DLM).
The driver supports of-platdata which is useful for tiny SPL.
Signed-off-by: Weijie Gao
---
v2 changes: replace non-DM code with of-platdata
---
drivers/serial/Kconfig | 20 +++
drivers/serial/Makefile| 1 +
drivers/serial/serial.c| 2 +
drivers/serial/serial_mt7620.c | 246 +
4 files changed, 269 insertions(+)
create mode 100644 drivers/serial/serial_mt7620.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b4805a2e4e..44fff8a3cd 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -401,6 +401,16 @@ config DEBUG_UART_MTK
driver will be available until the real driver model serial is
running.
+config DEBUG_UART_MT7620
+ bool "UART driver for MediaTek MT7620 and earlier SoCs"
+ depends on MT7620_SERIAL
+ help
+ Select this to enable a debug UART using the UART driver for
+ MediaTek MT7620 and earlier SoCs.
+ You will need to provide parameters to make this work. The
+ driver will be available until the real driver model serial is
+ running.
+
endchoice
config DEBUG_UART_BASE
@@ -817,6 +827,16 @@ config MTK_SERIAL
The High-speed UART is compatible with the ns16550a UART and have
its own high-speed registers.
+config MT7620_SERIAL
+ bool "UART driver for MediaTek MT7620 and earlier SoCs"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART support for MediaTek MT7620 and earlier
+ SoCs. This driver uses driver model and requires a device tree
+ binding to operate.
+ The UART driver for MediaTek MT7620 and earlier SoCs is *NOT*
+ compatible with the ns16550a UART.
+
config MPC8XX_CONS
bool "Console driver for MPC8XX"
depends on MPC8xx
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 25f7f8d342..0c3810f5d5 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
+obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o
obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 355659ba05..1546f41e42 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -127,6 +127,7 @@ serial_initfunc(pl01x_serial_initialize);
serial_initfunc(pxa_serial_initialize);
serial_initfunc(sh_serial_initialize);
serial_initfunc(mtk_serial_initialize);
+serial_initfunc(mt7620_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
@@ -181,6 +182,7 @@ int serial_initialize(void)
pxa_serial_initialize();
sh_serial_initialize();
mtk_serial_initialize();
+ mt7620_serial_initialize();
serial_assign(default_serial_console()->name);
diff --git a/drivers/serial/serial_mt7620.c b/drivers/serial/serial_mt7620.c
new file mode 100644
index 00..4f6b5de4cf
--- /dev/null
+++ b/drivers/serial/serial_mt7620.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * UART driver for MediaTek MT7620 and earlier SoCs
+ *
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+#include
+#endif
+
+struct mt7620_serial_regs {
+ u32 rbr;
+ u32 thr;
+ u32 ier;
+ u32 iir;
+ u32 fcr;
+ u32 lcr;
+ u32 mcr;
+ u32 lsr;
+ u32 msr;
+ u32 scratch;
+ u32 dl;
+ u32 dll;
+ u32 dlm;
+ u32 ifctl;
+};
+
+#define UART_LCR_WLS_8 0x03/* 8 bit character length */
+
+#define UART_LSR_DR0x01/* Data ready */
+#define UART_LSR_THRE 0x20/* Xmit holding register empty */
+#define UART_LSR_TEMT 0x40/* Xmitter empty */
+
+#define UART_MCR_DTR 0x01/* DTR */
+#define UART_MCR_RTS 0x02/* RTS */
+
+#define UART_FCR_FIFO_EN 0x01/* Fifo enable */
+#define UART_FCR_RXSR 0x02/* Receiver soft reset */
+#define UART_FCR_TXSR 0x04/* Transmitter soft reset */
+
+#define UART_MCRVAL (UART_MCR_DTR | \
+UART_MCR_RTS)
+
+/* Clear & enable FIFOs */
+#define UART_FCRVAL (UART_FCR_FIFO_EN | \
+UART_FCR_RXSR |\
+UART_FCR_TXSR)
+
[PATCH v2 06/21] mips: mtmips: add support to initialize SDRAM
This patch adds support for mtmips SoCs to initialize the SDRAM.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
arch/mips/mach-mtmips/ddr_init.c | 59
arch/mips/mach-mtmips/include/mach/ddr.h | 4 ++
2 files changed, 63 insertions(+)
diff --git a/arch/mips/mach-mtmips/ddr_init.c b/arch/mips/mach-mtmips/ddr_init.c
index 6c6d0933f2..9c986daea6 100644
--- a/arch/mips/mach-mtmips/ddr_init.c
+++ b/arch/mips/mach-mtmips/ddr_init.c
@@ -15,6 +15,13 @@
#define DDR_BW_TEST_PAT0xaaaa
+static const u32 sdr_size_cfg1[] = {
+ [DRAM_8MB] = (1 << NUMROWS_S),
+ [DRAM_16MB] = (1 << NUMROWS_S) | (1 << NUMCOLS_S),
+ [DRAM_32MB] = (2 << NUMROWS_S) | (1 << NUMCOLS_S),
+ [DRAM_64MB] = (2 << NUMROWS_S) | (2 << NUMCOLS_S),
+};
+
static const u32 dram_size[] = {
[DRAM_8MB] = SZ_8M,
[DRAM_16MB] = SZ_16M,
@@ -193,3 +200,55 @@ void ddr2_init(struct mc_ddr_init_param *param)
param->memsize = dram_size[sz];
param->bus_width = bw;
}
+
+static void mc_sdr_init(void __iomem *memc, mc_reset_t mc_reset, u32 cfg0,
+ u32 cfg1)
+{
+ mc_reset(1);
+ __udelay(200);
+ mc_reset(0);
+
+ writel(cfg0, memc + MEMCTL_SDRAM_CFG0_REG);
+ writel(cfg1, memc + MEMCTL_SDRAM_CFG1_REG);
+
+ while (!(readl(memc + MEMCTL_SDRAM_CFG1_REG) & SDRAM_INIT_DONE))
+ ;
+
+ clrsetbits_32(memc + MEMCTL_PWR_SAVE_CNT_REG, SR_TAR_CNT_M,
+ 1 << SR_TAR_CNT_S);
+
+ setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN);
+}
+
+void sdr_init(struct mc_ddr_init_param *param)
+{
+ enum mc_dram_size sz;
+ u32 cfg1;
+
+ cfg1 = param->sdr_cfg1 | SDRAM_INIT_START;
+ cfg1 &= ~(NUMCOLS_M | NUMROWS_M);
+
+ /* First initialization, determine SDR capacity */
+ mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0,
+ cfg1 | sdr_size_cfg1[DRAM_64MB]);
+
+ if (dram_addr_test_bit(9)) {
+ sz = DRAM_8MB;
+ } else {
+ if (dram_addr_test_bit(10)) {
+ if (dram_addr_test_bit(23))
+ sz = DRAM_16MB;
+ else
+ sz = DRAM_32MB;
+ } else {
+ sz = DRAM_64MB;
+ }
+ }
+
+ /* Final initialization */
+ mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0,
+ cfg1 | sdr_size_cfg1[sz]);
+
+ /* Return actual DDR configuration */
+ param->memsize = dram_size[sz];
+}
diff --git a/arch/mips/mach-mtmips/include/mach/ddr.h
b/arch/mips/mach-mtmips/include/mach/ddr.h
index f92198137b..15ff66ace6 100644
--- a/arch/mips/mach-mtmips/include/mach/ddr.h
+++ b/arch/mips/mach-mtmips/include/mach/ddr.h
@@ -35,6 +35,9 @@ typedef void (*mc_reset_t)(int assert);
struct mc_ddr_init_param {
void __iomem *memc;
+ u32 sdr_cfg0;
+ u32 sdr_cfg1;
+
u32 dq_dly;
u32 dqs_dly;
@@ -45,6 +48,7 @@ struct mc_ddr_init_param {
u32 bus_width;
};
+void sdr_init(struct mc_ddr_init_param *param);
void ddr1_init(struct mc_ddr_init_param *param);
void ddr2_init(struct mc_ddr_init_param *param);
void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw);
--
2.17.1
[PATCH v2 05/21] mips: enable _machine_restart for spl
The sysreset driver has a config CONFIG_SPL_SYSRESET for the spl stage.
Change CONFIG_SYSRESET to CONFIG_IS_ENABLED(SYSRESET) will give spl a
chance to use _machine_restart instead of the sysreset driver.
Signed-off-by: Weijie Gao
---
v2 changes: new
---
arch/mips/cpu/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 7d5c9fd83a..b304026a67 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -12,7 +12,7 @@
#include
#include
-#ifndef CONFIG_SYSRESET
+#if !CONFIG_IS_ENABLED(SYSRESET)
void __weak _machine_restart(void)
{
fprintf(stderr, "*** reset failed ***\n");
--
2.17.1
[PATCH v2 02/21] mips: mtmips: move mt7628 related Kconfig into mt7628 subdirectory
This patch is a preparation for add a new soc fot mtmips. Move all mt7628 related Kconfig (boards and UART selection) into mt7628 subdirectory and make sure the top directory of mtmips contains only selection for SoCs. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao --- v2 changes: none --- arch/mips/mach-mtmips/Kconfig| 53 +--- arch/mips/mach-mtmips/mt7628/Kconfig | 53 2 files changed, 54 insertions(+), 52 deletions(-) create mode 100644 arch/mips/mach-mtmips/mt7628/Kconfig diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 737de2cb8e..7c07430a0c 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -58,57 +58,6 @@ config SOC_MT7628 endchoice -choice - prompt "Board select" - -config BOARD_GARDENA_SMART_GATEWAY_MT7688 - bool "GARDENA smart Gateway" - depends on SOC_MT7628 - select BOARD_LATE_INIT - help - GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM - and 8 MiB of flash (SPI NOR) and additional SPI NAND storage. - -config BOARD_LINKIT_SMART_7688 - bool "LinkIt Smart 7688" - depends on SOC_MT7628 - help - Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM - and 32 MiB of flash (SPI). - Between its different peripherals there's an integrated switch with 4 - ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and - a MT7688 (PCIe). - -config BOARD_MT7628_RFB - bool "MediaTek MT7628 RFB" - depends on SOC_MT7628 - help - The reference design of MT7628. The board has 128 MiB DDR2, 8 MiB - SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host, - 1 SDXC, 1 PCIe socket and JTAG pins. - -config BOARD_VOCORE2 - bool "VoCore2" - depends on SOC_MT7628 - select SPL_SERIAL_SUPPORT - select SPL_UART2_SPIS_PINMUX - help - VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM - and 16 MiB of flash (SPI). - -endchoice - -config SPL_UART2_SPIS_PINMUX - bool "Use alternative pinmux for UART2 in SPL stage" - depends on SPL_SERIAL_SUPPORT - default n - help - Select this if the UART2 of your board is connected to GPIO 16/17 - (shared with SPIS) rather than the usual GPIO 20/21. - -source "board/gardena/smart-gateway-mt7688/Kconfig" -source "board/mediatek/mt7628/Kconfig" -source "board/seeed/linkit-smart-7688/Kconfig" -source "board/vocore/vocore2/Kconfig" +source "arch/mips/mach-mtmips/mt7628/Kconfig" endmenu diff --git a/arch/mips/mach-mtmips/mt7628/Kconfig b/arch/mips/mach-mtmips/mt7628/Kconfig new file mode 100644 index 00..e3f56e782e --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/Kconfig @@ -0,0 +1,53 @@ + +if SOC_MT7628 + +choice + prompt "Board select" + +config BOARD_GARDENA_SMART_GATEWAY_MT7688 + bool "GARDENA smart Gateway" + select BOARD_LATE_INIT + help + GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM + and 8 MiB of flash (SPI NOR) and additional SPI NAND storage. + +config BOARD_LINKIT_SMART_7688 + bool "LinkIt Smart 7688" + help + Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM + and 32 MiB of flash (SPI). + Between its different peripherals there's an integrated switch with 4 + ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and + a MT7688 (PCIe). + +config BOARD_MT7628_RFB + bool "MediaTek MT7628 RFB" + help + The reference design of MT7628. The board has 128 MiB DDR2, 8 MiB + SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host, + 1 SDXC, 1 PCIe socket and JTAG pins. + +config BOARD_VOCORE2 + bool "VoCore2" + select SPL_SERIAL_SUPPORT + select SPL_UART2_SPIS_PINMUX + help + VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM + and 16 MiB of flash (SPI). + +endchoice + +config SPL_UART2_SPIS_PINMUX + bool "Use alternative pinmux for UART2 in SPL stage" + depends on SPL_SERIAL_SUPPORT + default n + help + Select this if the UART2 of your board is connected to GPIO 16/17 + (shared with SPIS) rather than the usual GPIO 20/21. + +source "board/gardena/smart-gateway-mt7688/Kconfig" +source "board/mediatek/mt7628/Kconfig" +source "board/seeed/linkit-smart-7688/Kconfig" +source "board/vocore/vocore2/Kconfig" + +endif -- 2.17.1
[PATCH v2 04/21] mips: mtmips: fix dram size detection in dram_init
CONFIG_SYS_SDRAM_BASE points to cached memory, i.e. KSEG0, which is not
suitable for detecting memory size.
Replace CONFIG_SYS_SDRAM_BASE with KSEG1, and make dram_init() always do
memory size detection in any stage.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v2 changes: none
---
arch/mips/mach-mtmips/cpu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c
index 2ddf8cb096..ca1967055a 100644
--- a/arch/mips/mach-mtmips/cpu.c
+++ b/arch/mips/mach-mtmips/cpu.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -14,9 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
-#endif
+ gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
return 0;
}
--
2.17.1
Re: [PATCH v7 01/17] dfu: rename dfu_tftp_write() to dfu_write_by_name()
Hi Tom, > On Thu, Oct 29, 2020 at 01:47:41PM +0900, AKASHI Takahiro wrote: > > > This function is essentially independent from tftp, and will also be > > utilised in implementing UEFI capsule update in a later commit. > > So just give it a more generic name. > > In addition, a new configuration option, CONFIG_DFU_WRITE_ALT, was > > introduced so that the file will be compiled with different options, > > particularly one added in a later commit. > > > > Signed-off-by: AKASHI Takahiro > > Reviewed-by: Tom Rini > I guess that DFU related patches will go with -master or UEFI related tree? Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de pgp5rVO3VjlUt.pgp Description: OpenPGP digital signature
[PATCH v2 01/21] mips: dts: switch to board defines for dtb for mtmips
Previous the dts files for gardena-smart-gateway-mt7688 and linkit-smart-7688 are set to be built when mtmips is selected. This can lead to a compilation error if another soc is added to this arch with different dtsi files. So it's better to build the dtb only if their board is selected. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao --- v2 changes: none --- arch/mips/dts/Makefile | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index dc85901dca..e82f96d4e4 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -1,8 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_ARCH_MTMIPS) += \ - gardena-smart-gateway-mt7688.dtb \ - linkit-smart-7688.dtb dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_AP152) += ap152.dtb @@ -18,6 +15,8 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb +dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb +dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb -- 2.17.1
[PATCH v2 03/21] mips: mtmips: select SYSRESET for mt7628 only
Currently only mt7628 needs the sysreset driver, do not select it for mt7620. Signed-off-by: Weijie Gao --- v2 changes: new --- arch/mips/Kconfig | 1 - arch/mips/mach-mtmips/Kconfig | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e0f6b6c4b3..77f563e98e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -97,7 +97,6 @@ config ARCH_MTMIPS select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_LITTLE_ENDIAN - select SYSRESET select SUPPORT_SPL config ARCH_JZ47XX diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 7c07430a0c..c383e82a6b 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -43,6 +43,7 @@ config SOC_MT7628 select SYS_MIPS_CACHE_INIT_RAM_LOAD select PINCTRL_MT7628 select MTK_SERIAL + select SYSRESET select SYSRESET_RESETCTL select SPL_SEPARATE_BSS if SPL select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL -- 2.17.1
[PATCH v2 00/21] Add support for MediaTek MT7620 SoC
This series will add support for MediaTek MT7620 SoC with two reference boards and related drivers. The MediaTek MT7620 is a 2x2 802.11n WiSoC integrating a MIPS 24KEc processor running at a maximum frequency of 620MHz. This chip can be found in many wireless routers. This series add all basic drivers which are useful in u-boot, like usb, sdhc, ethernet, spi and serial. Booting from NAND is currently unsupported. Thanks, Weijie v2 changes: - Remove non-DM code from mt7620-serial driver, and use of-platdata instead - Fix dev_err related compilation error - Add expire_now for mt7620-wdt - Remove use of common.h Weijie Gao (21): mips: dts: switch to board defines for dtb for mtmips mips: mtmips: move mt7628 related Kconfig into mt7628 subdirectory mips: mtmips: select SYSRESET for mt7628 only mips: mtmips: fix dram size detection in dram_init mips: enable _machine_restart for spl mips: mtmips: add support to initialize SDRAM mips: mtmips: add support for MediaTek MT7620 SoC mips: mtmips: add two reference boards for mt7620 configs: mtmips: refresh for mt7628 based boards serial: add uart driver for MediaTek MT7620 SoC clk: add clock driver for MediaTek MT7620 SoC reset: mtmips: add reset controller support for MediaTek MT7620 SoC pinctrl: mtmips: add support for MediaTek MT7620 SoC watchdog: add watchdog driver for MediaTek MT7620 SoC gpio: add GPIO controller driver for MediaTek MT7620 SoC spi: add spi controller support for MediaTek MT7620 SoC phy: add USB PHY driver for MediaTek MT7620 SoC net: add ethernet driver for MediaTek MT7620 SoC mmc: mtk-sd: add pad control settings for MediaTek MT7620/MT76x8 SoCs reset: reset-mtmips: add DM_FLAG_PRE_RELOC flag MAINTAINERS: add maintainer for MediaTek MIPS platform MAINTAINERS | 23 + arch/mips/Kconfig |1 - arch/mips/cpu/cpu.c |2 +- arch/mips/dts/Makefile|7 +- arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts | 100 ++ arch/mips/dts/mediatek,mt7620-rfb.dts | 97 ++ arch/mips/dts/mt7620-u-boot.dtsi | 14 + arch/mips/dts/mt7620.dtsi | 296 arch/mips/mach-mtmips/Kconfig | 72 +- arch/mips/mach-mtmips/Makefile|1 + arch/mips/mach-mtmips/cpu.c |5 +- arch/mips/mach-mtmips/ddr_init.c | 59 + arch/mips/mach-mtmips/include/mach/ddr.h |4 + .../mach-mtmips/include/mach/mt7620-sysc.h| 54 + arch/mips/mach-mtmips/mt7620/Kconfig | 71 + arch/mips/mach-mtmips/mt7620/Makefile | 10 + arch/mips/mach-mtmips/mt7620/dram.c | 113 ++ arch/mips/mach-mtmips/mt7620/init.c | 193 +++ arch/mips/mach-mtmips/mt7620/lowlevel_init.S | 53 + arch/mips/mach-mtmips/mt7620/mt7620.h | 103 ++ arch/mips/mach-mtmips/mt7620/serial.c | 36 + arch/mips/mach-mtmips/mt7620/sysc.c | 172 +++ arch/mips/mach-mtmips/mt7628/Kconfig | 53 + board/mediatek/mt7620/Kconfig | 12 + board/mediatek/mt7620/MAINTAINERS |9 + board/mediatek/mt7620/Makefile|3 + board/mediatek/mt7620/board.c |6 + .../gardena-smart-gateway-mt7688_defconfig|1 + configs/linkit-smart-7688_defconfig |1 + configs/mt7620_mt7530_rfb_defconfig | 58 + configs/mt7620_rfb_defconfig | 76 + configs/mt7628_rfb_defconfig |1 + configs/vocore2_defconfig |1 + drivers/clk/mtmips/Makefile |1 + drivers/clk/mtmips/clk-mt7620.c | 159 +++ drivers/gpio/Kconfig |8 + drivers/gpio/Makefile |1 + drivers/gpio/mt7620_gpio.c| 146 ++ drivers/mmc/mtk-sd.c | 122 +- drivers/net/Kconfig | 12 + drivers/net/Makefile |1 + drivers/net/mt7620-eth.c | 1222 + drivers/phy/Kconfig |7 + drivers/phy/Makefile |1 + drivers/phy/mt7620-usb-phy.c | 113 ++ drivers/pinctrl/mtmips/Kconfig|9 + drivers/pinctrl/mtmips/Makefile |1 + drivers/pinctrl/mtmips/pinctrl-mt7620.c | 200 +++ drivers/reset/reset-mtmips.c |1 + drivers/serial/Kconfig| 20 + drivers/serial/Makefile |1 + drivers/serial/serial.c |2 + drivers/serial/serial_mt7620.c| 246 drivers/spi/Kconfig |7 + drivers/spi/Makefile |1 + drivers/spi/mt7620_spi.c | 277 drivers/watchdog/Kconfig
Re: Using USB Mass Storage on AM335X
Hello Otavio, Am 29.10.2020 um 23:19 schrieb Otavio Salvador: Hi, I am working on porting mainline U-Boot to a custom AM335X board that only has eMMC as the boot medium. I can load U-Boot via serial boot and flash MLO and u-boot.img into the eMMC using DFU. Then the board boots successfully via eMMC. Now I want to run the "ums" command to be able to mount the eMMC on the host. The problem I am getting is that when I select CONFIG_CMD_USB_MASS_STORAGE=y the board no longer boots. Does anyone know why selecting CONFIG_CMD_USB_MASS_STORAGE=y causes the board to not boot anymore? Not really ... I cannot see, which impact activating this command has with not booting ... May some problem with image size? Early malloc space, some addresses which now overlap? You see absolutly no U-Boot output on serial? Do you have enabled early debug uart (if it is possible for am335x .. I can;t remember) If so, you need a debugger, as it fails very early ... So, you see .. no real idea ... I am sorry. bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v7 00/17] efi_loader: add capsule update support
On 10/29/20 5:47 AM, AKASHI Takahiro wrote:
Summary
===
'UpdateCapsule' is one of runtime services defined in UEFI specification
and its aim is to allow a caller (OS) to pass information to the firmware,
i.e. U-Boot. This is mostly used to update firmware binary on devices by
instructions from OS.
While 'UpdateCapsule' is a runtime services function, it is, at least
initially, supported only before exiting boot services alike other runtime
functions, [Get/]SetVariable. This is because modifying storage which may
be shared with OS must be carefully designed and there is no general
assumption that we can do it.
Therefore, we practically support only "capsule on disk"; any capsule can
be handed over to UEFI subsystem as a file on a specific file system.
In this patch series, all the related definitions and structures are given
as UEFI specification describes, and basic framework for capsule support
is provided. Currently supported is
* firmware update (Firmware Management Protocol or simply FMP)
Most of functionality of firmware update is provided by FMP driver and
it can be, by nature, system/platform-specific. So you can and should
implement your own FMP driver(s) based on your system requirements.
Under the current implementation, we provide two basic but generic
drivers with two formats:
* FIT image format (as used in TFTP update and dfu)
* raw image format
It's totally up to users which one, or both, should be used on users'
system depending on user requirements.
Gitlab CI fails:
https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/jobs/172745
https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/jobs/172744
# Create signature database
# PK
check_call('cd %s; openssl req -x509 -sha256 -newkey
rsa:2048 -subj /CN=TEST_PK/ -keyout PK.key -out PK.crt -nodes -days 365'
% mnt_point, shell=True)
check_call('cd %s; %scert-to-efi-sig-list -g %s PK.crt
PK.esl; %ssign-efi-sig-list -t "2020-04-01" -c PK.crt -k PK.key PK
PK.esl PK.auth'
> % (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
E NameError: name 'EFITOOLS_PATH' is not defined
test/py/tests/test_efi_secboot/conftest.py:50: NameError
To get the series merged, please, provide the necessary patches for
.azure-pipelines.yml, .gitlab-ci.yml, .travis.yml.
Possibly you will have to adjust
https://gitlab.denx.de/u-boot/gitlab-ci-runner
Best regards
Heinrich
Quick usage
===
1. You can create a capsule file with the following host command:
$ mkeficapsule [--fit | --raw ]
2. Put the file under:
/EFI/UpdateCapsule of UEFI system partition
3. Specify firmware storage to be updated in "dfu_alt_info" variable
(Please follow README.dfu for details.)
==> env set dfu_alt_info '...'
4. After setting up UEFI's OsIndications variable, reboot U-Boot:
OsIndications <= EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED
Patch structure
===
Patch#1-#4,#12: preparatory patches
Patch#5-#11,#13: main part of implementation
Patch#14-#15: utilities
Patch#16-#17: pytests
[1] https://git.linaro.org/people/takahiro.akashi/u-boot.git efi/capsule
Prerequisite patches
None
Test
* passed all the pytests which are included in this patch series
on sandbox build locally.
Please note that the capsule pytest itself won't be run in the CI
partly because some specific configuration for sandbox build is
required and partly because there is a problem with virt-make-fs.
See test_efi_capsule_firmware.py.
Issues
==
* Timing of executing capsules-on-disk
Currently, processing a capsule is triggered only as part of
UEFI subsystem initialization. This means that, for example,
firmware update, may not take place at system booting time and
will potentially be delayed until a first call of any UEFI functions.
=> See patch#5 for my proposal
* A bunch of warnings like
WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef'
where possible
I don't think that fixing those improves anything.
* Add a document in uefi.rst
TODO's
==
(Won't be addressed in this series.)
* capsule authentication
* capsule dependency (dependency expression instruction set, or depex)
* loading drivers in a capsule
* handling RESET flag in a capsule and QeuryCapsuleCaps
* full semantics of ESRT (EFI System Resource Table)
* enabling capsule API at runtime
* json capsule
* recovery from update failure
Changes
===
v7 (October 29, 2020)
* rename CONFIG_DFU_ALT to CONFIG_DFU_WRITE_ALT (Patch#1,#3,#13)
v6 RESEND (October 29, 2020)
* rebased on v2021.01-rc1
v6 (September 7, 2020)
* temporarily drop the prerequisite patch[2]
* add a missing field (dependencies) in efi_api.h (but never used) (Patch#10)
* add a missing field (image_capsule_support) and related definitions
in efi_api.h (Patch#10, #15)
* cosmetic changes on constant
Re: stm32mp: The purpose of "!tee_find_device()"
On Thu, 29 Oct 2020 at 15:33, Alex G. wrote: > > On 9/30/20 6:03 PM, Alex G. wrote: > > Hi > > > > I'm trying to wrap my head around the purpose of the following lines in > > ft_system_setup(): > > > > if (!CONFIG_IS_ENABLED(OPTEE) || > > !tee_find_device(NULL, NULL, NULL, NULL)) > > stm32_fdt_disable_optee(blob); > > Hi! Me again! Do we have a (good) reason for this, or should I submit a > patch to remove this problematic code? > > Alex > > > My interpretation is "if optee is not running, delete the FDT node". > > The problem is that tee_find_device() invokes device_probe(). This in > > turn does an SMC call. This call results in an abort and reboot if optee > > is not running in the first place. > > > > So I don't think that tee_find_device() can be used as a check for "Is > > optee running?". Exhibit B: Outside of mach-stm32mp, tee_find_device() > > is used to obtain of a _working_ TEE node, not to ask if "is optee > > running?". > > > > > > My problem is that trying to start linux with CONFIG_OPTEE=y will cause > > the bootm command to crash (log in appendix A): > > > > load mmc 0:7 $loadaddr boot/uImage > > load mmc 0:7 $fdt_addr_r boot/stm32mp157c-dk2.dtb > > load mmc 0:7 0xc800 boot/utee > > setenv bootm_boot_mode sec > > bootm 0xc800 - $fdt_addr_r > > > > What is the intent of calling tee_find_device() in an FDT fixup > > function? The scheme is the generic U-Boot implementation do copy OP-TEE related nodes when found in its FDT to the FDT provided to Linux. (called from common/image-fdt.c) However stm32mp1 can be used with or without OP-TEE installed. To get a generic stm32mp1/U-Boot image that support both configurations (with and w/o OP-TEE installed), U-Boot FDT and config for this plaform do enable OP-TEE but, at u-boot runtime, if we find OP-TEE's not present, we remove the FTD node so that Linux does get it and expect OP-TEE is present. > > Do you have any ideas how to make it not crash (short of > > commenting out the problem lines) ? The crash seems due to that there is no secure monitor by the time you have this sequence called. Secure monitor is the code that handles the SMC. If none installed, SMCs ends nowhere and likely badly crash the systel. If OP-TEE is not running but there is a secure monitor loaded, it should not crash. It seems to me that U-Boot does set up a secure monitor for PSCI minimal support, so the U-Boot PSCI stack should nicely handle the SMC to report that there is no OP-TEE installed. Enabling CONFIG_ARMV7_PSCI should fix the issue I think. Regards, Etienne > > > > Alex > > > > > > Appendix A: u-boot log after bootm command > > > > ## Booting kernel from Legacy Image at c800 ... > > Image Name: > > Created: 2020-09-28 20:58:56 UTC > > Image Type: ARM Trusted Execution Environment Kernel Image > > (uncompressed) > > Data Size:349276 Bytes = 341.1 KiB > > Load Address: fde4 > > Entry Point: fe00 > > Verifying Checksum ... OK > > Loading Kernel Image > > ## Flattened Device Tree blob at c400 > > Booting using the fdt blob at 0xc400 > > Loading Device Tree to cffef000, end c5e2 ... OK > > > > U-Boot SPL 2020.10-rc4 (Sep 20 2020 - 23:46:47 +) > > Model: STMicroelectronics STM32MP157C-DK2 Discovery Board
Re: Using USB Mass Storage on AM335X
Hi Lokesh, Otavio, > + Pratyush > > On 30/10/20 11:36 am, Heiko Schocher wrote: > > Hello Otavio, > > > > Am 29.10.2020 um 23:19 schrieb Otavio Salvador: > >> Hi, > >> > >> I am working on porting mainline U-Boot to a custom AM335X board > >> that only has eMMC as the boot medium. > >> > >> I can load U-Boot via serial boot and flash MLO and u-boot.img into > >> the eMMC using DFU. Then the board boots successfully via eMMC. > >> > >> Now I want to run the "ums" command to be able to mount the eMMC on > >> the host. The problem I am getting is that when I select > >> CONFIG_CMD_USB_MASS_STORAGE=y the board no longer boots. > >> > >> Does anyone know why selecting CONFIG_CMD_USB_MASS_STORAGE=y causes > >> the board to not boot anymore? > > > > Not really ... I cannot see, which impact activating this command > > has with not booting ... > > > > May some problem with image size? Early malloc space, some addresses > > which now overlap? > > Good point. Just to avoid this scenario, can you make sure UMS is > enabled only in U-Boot and not in SPL? or you can try with old MLO > with new U-Boot :). IIRC there were some attempts to port gadget infrastructure to SPL for the TI SoCs. As pointed out above - it may happen that CONFIG_CMD_USB_MASS_STORAGE implicitly enables some other option in Kconfig, which also enables some SPL initialization for gadgets. The other option would be to check if the SPL malloc space is enough to handle allocations for gargets (as pointed out above). > > As Heiko already asked, can you provide more details in the failing > scenario? And yes, JTAG debugger would help. > > Thanks and regards, > Lokesh Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de pgpRpr5E1ugsf.pgp Description: OpenPGP digital signature
Re: U-Boot i2c bus num 1 is broken on Nokia N900
Hello Ivaylo, Am 30.10.2020 um 08:00 schrieb Ivaylo Dimitrov: Hi, On 29.10.20 г. 11:32 ч., Heiko Schocher wrote: Hello Ivaylo, Am 29.10.2020 um 08:51 schrieb Ivaylo Dimitrov: Hi, On 28.10.20 г. 7:42 ч., Heiko Schocher wrote: Hello Pali, sorry for late response ... Am 26.10.2020 um 22:48 schrieb Pali Rohár: On Monday 27 April 2020 09:03:13 Heiko Schocher wrote: Hello Pali, Am 26.04.2020 um 01:54 schrieb Pali Rohár: Adding Hannes and Heiko to the loop, please look at this problem. On Saturday 25 April 2020 14:11:32 Pali Rohár wrote: On Saturday 25 April 2020 07:00:58 Adam Ford wrote: On Sat, Apr 25, 2020 at 6:50 AM Pali Rohár wrote: On Saturday 25 April 2020 06:36:58 Adam Ford wrote: On Sat, Apr 25, 2020 at 5:42 AM Pali Rohár wrote: On Thursday 02 April 2020 20:42:31 Pali Rohár wrote: On Wednesday 01 April 2020 12:32:29 Merlijn Wajer wrote: Hi, On 01/04/2020 00:42, Pali Rohár wrote: On Wednesday 01 April 2020 00:35:07 Pali Rohár wrote: This patch series contain fixes for Nokia RX-51 board (aka N900). After these changes it is possible to run U-Boot in qemu emulator again. And U-Boot can boot kernel image from RAM, eMMC or OneNAND memory without problem. But on real Nokia N900 device is U-Boot crashing in reboot loop. I do not have serial console for Nokia N900 to debug this issue, but seems that it is related to OMAP I2C and OMAP HS MMC code. Problem is that there is no crash and even no error in qemu emulator so I cannot debug this issue. First problem is around /* reset lp5523 led */ code in rx51.c. On real N900 device it generates repeating messages: Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= When I commented that few lines all these messages disappeared. So problem is with OMAP I2C. ... I remember that somebody had serial jig for Nokia N900, could somebody look at this reboot loop problem? And any idea how should be OMAP I2C configured in U-Boot to correctly work? Maybe I will try to find some time to git bisect which change broke U-Boot on real N900 hardware. Took latest u-boot master, applied patches and this is the result on serial (first part is NOLO booting, I think that can be ignored) [1]. ... U-Boot 2020.04-rc4-00033-g7dbafe0634-dirty (Apr 01 2020 - 12:15:47 +0200) OMAP3530-HS ES3.1, CPU-OPP2, L3-165MHz, Max CPU Clock 600 MHz Nokia RX-51 + LPDDR/OneNAND I2C: ready DRAM: 256 MiB NAND: 0 Bytes Looks like that something with NAND is broken. The board code in U-Boot is in a very old state... :-( :-( MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 In: vga Out: vga Err: vga Timed out in wait_for_event: status=0100 Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured i2c_read (addr phase): pads on bus probably not configured (status=0x10) How is that trace even possible? I built and tested u-boot here on my devices and I see the same message, but unless I am becoming blind, i2c_read() is never called from within i2c_write(). This is really suspicious. Puh.. i2c_write: timed out writig last byte! These i2c errors are caused by /* reset lp5523 led */ i2c_set_bus_num(1); deprecated ... the board code needs cleanup ... Yes, my first thought too! This board needs a complete cleanup. I converted code to CONFIG_DM_I2C and nothing was changed, issue is still there... Ok. state = 0xff; i2c_write(0x32, 0x3d, 1, , 1); i2c_set_bus_num(0); Is
Re: [PATCH] arm: mvebu: puzzle-m801: Add a maintainer
On 29.10.20 22:30, Luka Kovacic wrote: Add Luka Perkov to Puzzle-M801 BOARD MAINTAINERS. Signed-off-by: Luka Kovacic Cc: Luka Perkov Reviewed-by: Stefan Roese Thanks, Stefan
Re: [PATCH v7 00/17] efi_loader: add capsule update support
On 10/30/20 8:54 AM, Heinrich Schuchardt wrote:
On 10/29/20 5:47 AM, AKASHI Takahiro wrote:
Summary
===
'UpdateCapsule' is one of runtime services defined in UEFI specification
and its aim is to allow a caller (OS) to pass information to the
firmware,
i.e. U-Boot. This is mostly used to update firmware binary on devices by
instructions from OS.
While 'UpdateCapsule' is a runtime services function, it is, at least
initially, supported only before exiting boot services alike other
runtime
functions, [Get/]SetVariable. This is because modifying storage which may
be shared with OS must be carefully designed and there is no general
assumption that we can do it.
Therefore, we practically support only "capsule on disk"; any capsule can
be handed over to UEFI subsystem as a file on a specific file system.
In this patch series, all the related definitions and structures are
given
as UEFI specification describes, and basic framework for capsule support
is provided. Currently supported is
* firmware update (Firmware Management Protocol or simply FMP)
Most of functionality of firmware update is provided by FMP driver and
it can be, by nature, system/platform-specific. So you can and should
implement your own FMP driver(s) based on your system requirements.
Under the current implementation, we provide two basic but generic
drivers with two formats:
* FIT image format (as used in TFTP update and dfu)
* raw image format
It's totally up to users which one, or both, should be used on users'
system depending on user requirements.
Gitlab CI fails:
https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/jobs/172745
https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/jobs/172744
# Create signature database
# PK
check_call('cd %s; openssl req -x509 -sha256 -newkey
rsa:2048 -subj /CN=TEST_PK/ -keyout PK.key -out PK.crt -nodes -days 365'
% mnt_point, shell=True)
check_call('cd %s; %scert-to-efi-sig-list -g %s PK.crt
PK.esl; %ssign-efi-sig-list -t "2020-04-01" -c PK.crt -k PK.key PK
PK.esl PK.auth'
> % (mnt_point, EFITOOLS_PATH, GUID, EFITOOLS_PATH),
shell=True)
E NameError: name 'EFITOOLS_PATH' is not defined
test/py/tests/test_efi_secboot/conftest.py:50: NameError
To get the series merged, please, provide the necessary patches for
.azure-pipelines.yml, .gitlab-ci.yml, .travis.yml.
Possibly you will have to adjust
https://gitlab.denx.de/u-boot/gitlab-ci-runner
Best regards
Heinrich
Hello Lukasz,
I would like to get at least get the DFU part merged. So I suggest to
add the DFU patches to my next pull request for Tom.
Is that fine with you?
Best regards
Heinrich
[PATCH v2 13/21] pinctrl: mtmips: add support for MediaTek MT7620 SoC
This patch adds pinctrl support for MediaTek MT7620 SoC.
The MT7620 SoC supports only pinmux.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/pinctrl/mtmips/Kconfig | 9 ++
drivers/pinctrl/mtmips/Makefile | 1 +
drivers/pinctrl/mtmips/pinctrl-mt7620.c | 200
3 files changed, 210 insertions(+)
create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7620.c
diff --git a/drivers/pinctrl/mtmips/Kconfig b/drivers/pinctrl/mtmips/Kconfig
index 8482a38ebc..844d5b743f 100644
--- a/drivers/pinctrl/mtmips/Kconfig
+++ b/drivers/pinctrl/mtmips/Kconfig
@@ -3,6 +3,15 @@ config PINCTRL_MTMIPS
depends on ARCH_MTMIPS
bool
+config PINCTRL_MT7620
+ bool "MediaTek MT7620 pin control driver"
+ select PINCTRL_MTMIPS
+ depends on SOC_MT7620 && PINCTRL_GENERIC
+ help
+ Support pin multiplexing control on MediaTek MT7620.
+ The driver is controlled by a device tree node which contains
+ the pin mux functions for each available pin groups.
+
config PINCTRL_MT7628
bool "MediaTek MT7628 pin control driver"
select PINCTRL_MTMIPS
diff --git a/drivers/pinctrl/mtmips/Makefile b/drivers/pinctrl/mtmips/Makefile
index 3ba5c0c66d..ba945a89a7 100644
--- a/drivers/pinctrl/mtmips/Makefile
+++ b/drivers/pinctrl/mtmips/Makefile
@@ -4,4 +4,5 @@
obj-$(CONFIG_PINCTRL_MTMIPS) += pinctrl-mtmips-common.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
obj-$(CONFIG_PINCTRL_MT7628) += pinctrl-mt7628.o
diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7620.c
b/drivers/pinctrl/mtmips/pinctrl-mt7620.c
new file mode 100644
index 00..10a4fc6c19
--- /dev/null
+++ b/drivers/pinctrl/mtmips/pinctrl-mt7620.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+
+#include "pinctrl-mtmips-common.h"
+
+#define SUTIF_SHIFT30
+#define WDT_RST_SHIFT 21
+#define PA_G_SHIFT 20
+#define NAND_SD_SHIFT 18
+#define PERST_SHIFT16
+#define EPHY_LED_SHIFT 15
+#define WLED_SHIFT 13
+#define SPI_CS1_SHIFT 12
+#define SPI_SHIFT 11
+#define RGMII2_SHIFT 10
+#define RGMII1_SHIFT 9
+#define MDIO_SHIFT 7
+#define UARTL_SHIFT5
+#define UARTF_SHIFT2
+#define I2C_SHIFT 0
+
+#define GM4_MASK 3
+#define GM8_MASK 7
+
+#if CONFIG_IS_ENABLED(PINMUX)
+static const struct mtmips_pmx_func sutif_grp[] = {
+ FUNC("i2c", 2),
+ FUNC("uartl", 1),
+ FUNC("none", 0),
+};
+
+static const struct mtmips_pmx_func wdt_rst_grp[] = {
+ FUNC("gpio", 2),
+ FUNC("refclk", 1),
+ FUNC("wdt rst", 0),
+};
+
+static const struct mtmips_pmx_func pa_g_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("pa", 0),
+};
+
+static const struct mtmips_pmx_func nand_sd_grp[] = {
+ FUNC("gpio", 2),
+ FUNC("sd", 1),
+ FUNC("nand", 0),
+};
+
+static const struct mtmips_pmx_func perst_grp[] = {
+ FUNC("gpio", 2),
+ FUNC("refclk", 1),
+ FUNC("perst", 0),
+};
+
+static const struct mtmips_pmx_func ephy_led_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("led", 0),
+};
+
+static const struct mtmips_pmx_func wled_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("led", 0),
+};
+
+static const struct mtmips_pmx_func spi_cs1_grp[] = {
+ FUNC("refclk", 1),
+ FUNC("spi cs1", 0),
+};
+
+static const struct mtmips_pmx_func spi_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("spi", 0),
+};
+
+static const struct mtmips_pmx_func rgmii2_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("rgmii2", 0),
+};
+
+static const struct mtmips_pmx_func rgmii1_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("rgmii1", 0),
+};
+
+static const struct mtmips_pmx_func mdio_grp[] = {
+ FUNC("gpio", 2),
+ FUNC("refclk", 1),
+ FUNC("mdio", 0),
+};
+
+static const struct mtmips_pmx_func uartl_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("uartl", 0),
+};
+
+static const struct mtmips_pmx_func uartf_grp[] = {
+ FUNC("gpio", 7),
+ FUNC("i2s gpio", 6),
+ FUNC("uartf gpio", 5),
+ FUNC("gpio pcm", 4),
+ FUNC("i2s uartf", 3),
+ FUNC("i2s pcm", 2),
+ FUNC("uartf pcm", 1),
+ FUNC("uartf", 0),
+};
+
+static const struct mtmips_pmx_func i2c_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("i2c", 0),
+};
+
+static const struct mtmips_pmx_group mt7620_pinmux_data[] = {
+ GRP("sutif", sutif_grp, 0, SUTIF_SHIFT, GM4_MASK),
+ GRP("wdt rst", wdt_rst_grp, 0, WDT_RST_SHIFT, GM4_MASK),
+ GRP("pa", pa_g_grp, 0, PA_G_SHIFT, 1),
+ GRP("nand", nand_sd_grp, 0, NAND_SD_SHIFT, GM4_MASK),
+
[PATCH v2 14/21] watchdog: add watchdog driver for MediaTek MT7620 SoC
This patch adds watchdog support for the Mediatek MT7620 SoC
Signed-off-by: Weijie Gao
---
v2 changes: add expire_now
---
drivers/watchdog/Kconfig | 7 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/mt7620_wdt.c | 132 ++
3 files changed, 140 insertions(+)
create mode 100644 drivers/watchdog/mt7620_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 210d9f8093..35d078caa0 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -124,6 +124,13 @@ config WDT_MPC8xx
help
Select this to enable mpc8xx watchdog timer
+config WDT_MT7620
+ bool "MediaTek MT7620 watchdog timer support"
+ depends on WDT && SOC_MT7620
+ help
+ Select this to enable watchdog timer on MediaTek MT7620 and earlier
+ SoC chips.
+
config WDT_MT7621
bool "MediaTek MT7621 watchdog timer support"
depends on WDT && SOC_MT7628
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 01b8231f2b..825b50e626 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
+obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
diff --git a/drivers/watchdog/mt7620_wdt.c b/drivers/watchdog/mt7620_wdt.c
new file mode 100644
index 00..2643167f8f
--- /dev/null
+++ b/drivers/watchdog/mt7620_wdt.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao
+ *
+ * Watchdog timer for MT7620 and earlier SoCs
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct mt7620_wdt {
+ void __iomem *regs;
+ u64 timeout;
+};
+
+#define TIMER_FREQ 4000
+#define TIMER_MASK 0x
+#define TIMER_PRESCALE 65536
+
+#define TIMER_LOAD 0x00
+#define TIMER_CTL 0x08
+
+#define TIMER_ENABLE BIT(7)
+#define TIMER_MODE_SHIFT 4
+#define TIMER_MODE_WDT 3
+#define TIMER_PRESCALE_SHIFT 0
+#define TIMER_PRESCALE_65536 15
+
+static void mt7620_wdt_ping(struct mt7620_wdt *priv)
+{
+ u64 val;
+
+ val = (TIMER_FREQ / TIMER_PRESCALE) * priv->timeout;
+ do_div(val, 1000);
+
+ if (val > TIMER_MASK)
+ val = TIMER_MASK;
+
+ writel(val, priv->regs + TIMER_LOAD);
+}
+
+static int mt7620_wdt_start(struct udevice *dev, u64 ms, ulong flags)
+{
+ struct mt7620_wdt *priv = dev_get_priv(dev);
+
+ priv->timeout = ms;
+ mt7620_wdt_ping(priv);
+
+ writel(TIMER_ENABLE | (TIMER_MODE_WDT << TIMER_MODE_SHIFT) |
+ (TIMER_PRESCALE_65536 << TIMER_PRESCALE_SHIFT),
+ priv->regs + TIMER_CTL);
+
+ return 0;
+}
+
+static int mt7620_wdt_stop(struct udevice *dev)
+{
+ struct mt7620_wdt *priv = dev_get_priv(dev);
+
+ mt7620_wdt_ping(priv);
+
+ clrbits_32(priv->regs + TIMER_CTL, TIMER_ENABLE);
+
+ return 0;
+}
+
+static int mt7620_wdt_reset(struct udevice *dev)
+{
+ struct mt7620_wdt *priv = dev_get_priv(dev);
+
+ mt7620_wdt_ping(priv);
+
+ return 0;
+}
+
+static int mt7620_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct mt7620_wdt *priv = dev_get_priv(dev);
+
+ mt7620_wdt_start(dev, 1, flags);
+
+ /* 0 will disable the timer, so use 1 instead */
+ writel(1, priv->regs + TIMER_LOAD);
+
+ return 0;
+}
+
+static int mt7620_wdt_probe(struct udevice *dev)
+{
+ struct mt7620_wdt *priv = dev_get_priv(dev);
+ struct reset_ctl reset_wdt;
+ int ret;
+
+ ret = reset_get_by_index(dev, 0, _wdt);
+ if (!ret)
+ reset_deassert(_wdt);
+
+ priv->regs = dev_remap_addr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ mt7620_wdt_stop(dev);
+
+ return 0;
+}
+
+static const struct wdt_ops mt7620_wdt_ops = {
+ .start = mt7620_wdt_start,
+ .reset = mt7620_wdt_reset,
+ .stop = mt7620_wdt_stop,
+ .expire_now = mt7620_wdt_expire_now,
+};
+
+static const struct udevice_id mt7620_wdt_ids[] = {
+ { .compatible = "mediatek,mt7620-wdt" },
+ {}
+};
+
+U_BOOT_DRIVER(mt7620_wdt) = {
+ .name = "mt7620_wdt",
+ .id = UCLASS_WDT,
+ .of_match = mt7620_wdt_ids,
+ .probe = mt7620_wdt_probe,
+ .priv_auto_alloc_size = sizeof(struct mt7620_wdt),
+ .ops = _wdt_ops,
+};
--
2.17.1
[PATCH v2 12/21] reset: mtmips: add reset controller support for MediaTek MT7620 SoC
This patch adds reset controller bits definition header file for MediaTek MT7620 SoC Signed-off-by: Weijie Gao --- v2 changes: none --- include/dt-bindings/reset/mt7620-reset.h | 35 1 file changed, 35 insertions(+) create mode 100644 include/dt-bindings/reset/mt7620-reset.h diff --git a/include/dt-bindings/reset/mt7620-reset.h b/include/dt-bindings/reset/mt7620-reset.h new file mode 100644 index 00..3096b29cdb --- /dev/null +++ b/include/dt-bindings/reset/mt7620-reset.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7620_RESET_H_ +#define _DT_BINDINGS_MT7620_RESET_H_ + +#define PPE_RST31 +#define SDHC_RST 30 +#define MIPS_CNT_RST 28 +#define PCIE_RST 26 +#define UHST_RST 25 +#define EPHY_RST 24 +#define ESW_RST23 +#define UDEV_RST 22 +#define FE_RST 21 +#define WLAN_RST 20 +#define UARTL_RST 19 +#define SPI_RST18 +#define I2S_RST17 +#define I2C_RST16 +#define NAND_RST 15 +#define DMA_RST14 +#define PIO_RST13 +#define UARTF_RST 12 +#define PCM_RST11 +#define MC_RST 10 +#define INTC_RST 9 +#define TIMER_RST 8 +#define SYS_RST0 + +#endif /* _DT_BINDINGS_MT7620_RESET_H_ */ -- 2.17.1
[PATCH v2 15/21] gpio: add GPIO controller driver for MediaTek MT7620 SoC
This patch adds GPIO controller driver for MediaTek MT7620 SoC
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/mt7620_gpio.c | 146 +
3 files changed, 155 insertions(+)
create mode 100644 drivers/gpio/mt7620_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 202fcc6f47..7e94759a79 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -471,6 +471,14 @@ config MPC83XX_SPISEL_BOOT
This pin is typically used as spi chip select to a spi nor flash.
+config MT7620_GPIO
+ bool "MediaTek MT7620 GPIO driver"
+ depends on DM_GPIO && SOC_MT7620
+ default y
+ help
+ Device model driver for GPIO controller present in MediaTek MT7620
+ and earlier SoCs.
+
config MT7621_GPIO
bool "MediaTek MT7621 GPIO driver"
depends on DM_GPIO && SOC_MT7628
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index d3d0d3cacf..8541ba0b0a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
+obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
obj-$(CONFIG_NX_GPIO) += nx_gpio.o
diff --git a/drivers/gpio/mt7620_gpio.c b/drivers/gpio/mt7620_gpio.c
new file mode 100644
index 00..508851ea5f
--- /dev/null
+++ b/drivers/gpio/mt7620_gpio.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao
+ *
+ * GPIO controller driver for MediaTek MT7620 SoC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum mt7620_regs {
+ GPIO_REG_DATA,
+ GPIO_REG_DIR,
+ GPIO_REG_SET,
+ GPIO_REG_CLR,
+
+ __GPIO_REG_MAX
+};
+
+struct mt7620_gpio_priv {
+ void __iomem *base;
+ u32 regs[__GPIO_REG_MAX];
+ u32 count;
+};
+
+static int mt7620_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct mt7620_gpio_priv *priv = dev_get_priv(dev);
+
+ return !!(readl(priv->base + priv->regs[GPIO_REG_DATA]) & BIT(offset));
+}
+
+static int mt7620_gpio_set_value(struct udevice *dev, unsigned int offset,
+int value)
+{
+ struct mt7620_gpio_priv *priv = dev_get_priv(dev);
+ u32 reg;
+
+ reg = value ? priv->regs[GPIO_REG_SET] : priv->regs[GPIO_REG_CLR];
+
+ writel(BIT(offset), priv->base + reg);
+
+ return 0;
+}
+
+static int mt7620_gpio_direction_input(struct udevice *dev, unsigned int
offset)
+{
+ struct mt7620_gpio_priv *priv = dev_get_priv(dev);
+
+ clrbits_32(priv->base + priv->regs[GPIO_REG_DIR], BIT(offset));
+
+ return 0;
+}
+
+static int mt7620_gpio_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ struct mt7620_gpio_priv *priv = dev_get_priv(dev);
+
+ /* Set value first */
+ mt7620_gpio_set_value(dev, offset, value);
+
+ setbits_32(priv->base + priv->regs[GPIO_REG_DIR], BIT(offset));
+
+ return 0;
+}
+
+static int mt7620_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ struct mt7620_gpio_priv *priv = dev_get_priv(dev);
+
+ return (readl(priv->base + priv->regs[GPIO_REG_DIR]) & BIT(offset)) ?
+ GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops mt7620_gpio_ops = {
+ .direction_input= mt7620_gpio_direction_input,
+ .direction_output = mt7620_gpio_direction_output,
+ .get_value = mt7620_gpio_get_value,
+ .set_value = mt7620_gpio_set_value,
+ .get_function = mt7620_gpio_get_function,
+};
+
+static int mt7620_gpio_probe(struct udevice *dev)
+{
+ struct mt7620_gpio_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const char *name;
+
+ name = dev_read_string(dev, "mediatek,bank-name");
+ if (!name)
+ name = dev->name;
+
+ uc_priv->gpio_count = priv->count;
+ uc_priv->bank_name = name;
+
+ return 0;
+}
+
+static int mt7620_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mt7620_gpio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->base = dev_remap_addr_index(dev, 0);
+ if (!priv->base) {
+ dev_err(dev, "mt7620_gpio: unable to map registers\n");
+ return -EINVAL;
+ }
+
+ ret = dev_read_u32(dev, "mediatek,gpio-num", >count);
+ if (ret) {
+ dev_err(dev, "mt7620_gpio: failed to get GPIO count\n");
+
[PATCH v2 11/21] clk: add clock driver for MediaTek MT7620 SoC
This patch adds a clock driver for MediaTek MT7620 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/clk/mtmips/Makefile| 1 +
drivers/clk/mtmips/clk-mt7620.c| 159 +
include/dt-bindings/clock/mt7620-clk.h | 40 +++
3 files changed, 200 insertions(+)
create mode 100644 drivers/clk/mtmips/clk-mt7620.c
create mode 100644 include/dt-bindings/clock/mt7620-clk.h
diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile
index e1938418da..732e7f2545 100644
--- a/drivers/clk/mtmips/Makefile
+++ b/drivers/clk/mtmips/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
diff --git a/drivers/clk/mtmips/clk-mt7620.c b/drivers/clk/mtmips/clk-mt7620.c
new file mode 100644
index 00..44e4b53c21
--- /dev/null
+++ b/drivers/clk/mtmips/clk-mt7620.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* CLKCFG1 */
+#define CLKCFG1_REG0x30
+
+#define CLK_SRC_CPU-1
+#define CLK_SRC_CPU_D2 -2
+#define CLK_SRC_SYS-3
+#define CLK_SRC_XTAL -4
+#define CLK_SRC_PERI -5
+
+struct mt7620_clk_priv {
+ struct udevice *dev;
+ struct udevice *sysc;
+ struct mt7620_sysc_clks clks;
+};
+
+static const int mt7620_clks[] = {
+ [CLK_SYS] = CLK_SRC_SYS,
+ [CLK_CPU] = CLK_SRC_CPU,
+ [CLK_XTAL] = CLK_SRC_XTAL,
+ [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
+ [CLK_UARTF] = CLK_SRC_PERI,
+ [CLK_UARTL] = CLK_SRC_PERI,
+ [CLK_SPI] = CLK_SRC_SYS,
+ [CLK_I2C] = CLK_SRC_PERI,
+ [CLK_I2S] = CLK_SRC_PERI,
+};
+
+static ulong mt7620_clk_get_rate(struct clk *clk)
+{
+ struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id >= ARRAY_SIZE(mt7620_clks))
+ return 0;
+
+ switch (mt7620_clks[clk->id]) {
+ case CLK_SRC_CPU:
+ return priv->clks.cpu_clk;
+ case CLK_SRC_CPU_D2:
+ return priv->clks.cpu_clk / 2;
+ case CLK_SRC_SYS:
+ return priv->clks.sys_clk;
+ case CLK_SRC_XTAL:
+ return priv->clks.xtal_clk;
+ case CLK_SRC_PERI:
+ return priv->clks.peri_clk;
+ default:
+ return mt7620_clks[clk->id];
+ }
+}
+
+static int mt7620_clkcfg1_rmw(struct mt7620_clk_priv *priv, u32 clr, u32 set)
+{
+ u32 val;
+ int ret;
+
+ ret = misc_read(priv->sysc, CLKCFG1_REG, , sizeof(val));
+ if (ret) {
+ dev_err(priv->dev, "mt7620_clk: failed to read CLKCFG1\n");
+ return ret;
+ }
+
+ val &= ~clr;
+ val |= set;
+
+ ret = misc_write(priv->sysc, CLKCFG1_REG, , sizeof(val));
+ if (ret) {
+ dev_err(priv->dev, "mt7620_clk: failed to write CLKCFG1\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mt7620_clk_enable(struct clk *clk)
+{
+ struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 30)
+ return -1;
+
+ return mt7620_clkcfg1_rmw(priv, 0, BIT(clk->id));
+}
+
+static int mt7620_clk_disable(struct clk *clk)
+{
+ struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 30)
+ return -1;
+
+ return mt7620_clkcfg1_rmw(priv, BIT(clk->id), 0);
+}
+
+const struct clk_ops mt7620_clk_ops = {
+ .enable = mt7620_clk_enable,
+ .disable = mt7620_clk_disable,
+ .get_rate = mt7620_clk_get_rate,
+};
+
+static int mt7620_clk_probe(struct udevice *dev)
+{
+ struct mt7620_clk_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args sysc_args;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(dev->node, "mediatek,sysc", NULL,
+0, 0, _args);
+ if (ret) {
+ dev_err(dev, "mt7620_clk: sysc property not found\n");
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_MISC, sysc_args.node,
+ >sysc);
+ if (ret) {
+ dev_err(dev, "mt7620_clk: failed to sysc device\n");
+ return ret;
+ }
+
+ ret = misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_GET_CLK,
+>clks);
+ if (ret) {
+ dev_err(dev, "mt7620_clk: failed to get base clocks\n");
+ return ret;
+ }
+
+ priv->dev = dev;
+
+ return 0;
+}
+
+static const struct udevice_id mt7620_clk_ids[] = {
+ { .compatible = "mediatek,mt7620-clk" },
+ { }
+};
[PATCH v2 18/21] net: add ethernet driver for MediaTek MT7620 SoC
This patch adds ethernet driver for MediaTek MT7620 SoC. The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in 7-port switch and two xMII interfaces (can be MII/RMII/RGMII). The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be configured to connect to either the intergrited FE PHY, or the xMII. Port 5 always connects to the xMII. Port 6 is the CPU port. This driver supports MT7530 giga switch connects to port 5. Signed-off-by: Weijie Gao --- v2 changes: none --- drivers/net/Kconfig | 12 + drivers/net/Makefile |1 + drivers/net/mt7620-eth.c | 1222 ++ 3 files changed, 1235 insertions(+) create mode 100644 drivers/net/mt7620-eth.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 3a5e036880..d1a52c7264 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -399,6 +399,18 @@ config MACB_ZYNQ The Cadence MACB ethernet interface was used on Zynq platform. Say Y to enable support for the MACB/GEM in Zynq chip. +config MT7620_ETH + bool "MediaTek MT7620 Ethernet Interface" + depends on SOC_MT7620 + select PHYLIB + select DM_RESET + select DM_GPIO + select CLK + help + The MediaTek MT7620 ethernet interface is used on MT7620 based + boards. It has a built-in switch with two configurable ports which + can connect to external PHY/MACs. + config MT7628_ETH bool "MediaTek MT7628 Ethernet Interface" depends on SOC_MT7628 diff --git a/drivers/net/Makefile b/drivers/net/Makefile index e3bdda359d..f2a0df509d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o +obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVMDIO) += mvmdio.o diff --git a/drivers/net/mt7620-eth.c b/drivers/net/mt7620-eth.c new file mode 100644 index 00..2c148a3b35 --- /dev/null +++ b/drivers/net/mt7620-eth.c @@ -0,0 +1,1222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Frame Engine block */ +#define GDMA_BASE 0x600 +#define PDMA_BASE 0x800 + +/* GDMA registers */ +#define GDMA_FWD_CFG 0x00 +#define GDMA_DST_PORT GENMASK(2, 0) +#define GDMA_DST_PORT_CPU0 + +#define GDMA_MAC_ADRL 0x08 +#define GDMA_MAC_ADRH 0x0c + +/* PDMA registers */ +#define TX_BASE_PTR0 0x000 +#define TX_MAX_CNT00x004 +#define TX_CTX_IDX00x008 +#define TX_DTX_IDX00x00c +#define RX_BASE_PTR0 0x100 +#define RX_MAX_CNT00x104 +#define RX_CALC_IDX0 0x108 +#define RX_DRX_IDX00x10c + +#define PDMA_GLO_CFG 0x204 +#define TX_WB_DDONEBIT(6) +#define PDMA_BT_SIZE GENMASK(5, 4) +#define PDMA_BT_SIZE_32B 1 +#define RX_DMA_BUSYBIT(3) +#define RX_DMA_EN BIT(2) +#define TX_DMA_BUSYBIT(1) +#define TX_DMA_EN BIT(0) + +#define PDMA_RST_IDX 0x208 +#define RST_DRX_IDX0 BIT(16) +#define RST_DTX_IDX0 BIT(0) + +/* Built-in giga ethernet switch block */ + +/* ARL registers */ +#define GSW_MFC0x0010 +#define BC_FFP GENMASK(31, 24) +#define UNM_FFPGENMASK(23, 16) +#define UNU_FFPGENMASK(15, 8) +#define CPU_EN BIT(7) +#define CPU_PORT GENMASK(6, 4) + +/* Port registers */ +#define GSW_PCR(p) (0x2004 + (p) * 0x100) +#define PORT_MATRIXGENMASK(23, 16) + +#define GSW_PVC(p) (0x2010 + (p) * 0x100) +#define STAG_VPID GENMASK(31, 16) +#define VLAN_ATTR GENMASK(7, 6) +#define VLAN_ATTR_USER 0 + +/* MAC registers */ +#define GSW_PMCR(p)(0x3000 + (p) * 0x100) +#define IPG_CFGGENMASK(19, 18) +#define IPG_96BIT_WITH_SHORT_IPG 1 +#define MAC_MODE BIT(16) +#define FORCE_MODE BIT(15) +#define MAC_TX_EN BIT(14) +#define
[PATCH v2 17/21] phy: add USB PHY driver for MediaTek MT7620 SoC
This patch adds USB PHY driver for MediaTek MT7620 SoC
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/phy/Kconfig | 7 +++
drivers/phy/Makefile | 1 +
drivers/phy/mt7620-usb-phy.c | 113 +++
3 files changed, 121 insertions(+)
create mode 100644 drivers/phy/mt7620-usb-phy.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index d12a6b02ad..ab638f0e7d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -218,6 +218,13 @@ config KEYSTONE_USB_PHY
This PHY is found on some Keystone (K2) devices supporting USB.
+config MT7620_USB_PHY
+ bool "MediaTek MT7620 USB PHY support"
+ depends on PHY
+ depends on SOC_MT7620
+ help
+ Support the intergated USB PHY in MediaTek MT7620 SoC
+
config MT76X8_USB_PHY
bool "MediaTek MT76x8 (7628/88) USB PHY support"
depends on PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 45a7fe5b56..6b3761b8c8 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o
meson-g12a-usb3-pcie.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
+obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o
obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
diff --git a/drivers/phy/mt7620-usb-phy.c b/drivers/phy/mt7620-usb-phy.c
new file mode 100644
index 00..59ac32f327
--- /dev/null
+++ b/drivers/phy/mt7620-usb-phy.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct mt7620_usb_phy {
+ struct udevice *dev;
+ struct udevice *sysc;
+ struct clk_bulk clocks;
+ struct reset_ctl_bulk resets;
+};
+
+static int mt7620_usb_phy_power_on(struct phy *_phy)
+{
+ struct mt7620_usb_phy *phy = dev_get_priv(_phy->dev);
+ u32 mode = MT7620_SYSC_USB_HOST_MODE;
+ int ret;
+
+ reset_deassert_bulk(>resets);
+
+ clk_enable_bulk(>clocks);
+
+ mdelay(10);
+
+ ret = misc_ioctl(phy->sysc, MT7620_SYSC_IOCTL_SET_USB_MODE, );
+ if (ret) {
+ dev_err(phy->dev,
+ "mt7620_usbphy: failed to set USB host mode\n");
+ return ret;
+ }
+
+ mdelay(10);
+
+ return 0;
+}
+
+static int mt7620_usb_phy_power_off(struct phy *_phy)
+{
+ struct mt7620_usb_phy *phy = dev_get_priv(_phy->dev);
+
+ clk_disable_bulk(>clocks);
+
+ reset_assert_bulk(>resets);
+
+ return 0;
+}
+
+static int mt7620_usb_phy_probe(struct udevice *dev)
+{
+ struct mt7620_usb_phy *phy = dev_get_priv(dev);
+ struct ofnode_phandle_args sysc_args;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(dev->node, "mediatek,sysc", NULL,
+0, 0, _args);
+ if (ret) {
+ dev_err(dev, "mt7620_usbphy: sysc property not found\n");
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_MISC, sysc_args.node,
+ >sysc);
+ if (ret) {
+ dev_err(dev, "mt7620_usbphy: failed to sysc device\n");
+ return ret;
+ }
+
+ ret = clk_get_bulk(dev, >clocks);
+ if (ret) {
+ dev_err(dev, "mt7620_usbphy: failed to get clocks\n");
+ return ret;
+ }
+
+ ret = reset_get_bulk(dev, >resets);
+ if (ret) {
+ dev_err(dev, "mt7620_usbphy: failed to get reset control\n");
+ return ret;
+ }
+
+ phy->dev = dev;
+
+ return 0;
+}
+
+static struct phy_ops mt7620_usb_phy_ops = {
+ .power_on = mt7620_usb_phy_power_on,
+ .power_off = mt7620_usb_phy_power_off,
+};
+
+static const struct udevice_id mt7620_usb_phy_ids[] = {
+ { .compatible = "mediatek,mt7620-usbphy" },
+ { }
+};
+
+U_BOOT_DRIVER(mt7620_usb_phy) = {
+ .name = "mt7620_usb_phy",
+ .id = UCLASS_PHY,
+ .of_match = mt7620_usb_phy_ids,
+ .ops= _usb_phy_ops,
+ .probe = mt7620_usb_phy_probe,
+ .priv_auto_alloc_size = sizeof(struct mt7620_usb_phy),
+};
--
2.17.1
[PATCH v2 19/21] mmc: mtk-sd: add pad control settings for MediaTek MT7620/MT76x8 SoCs
The driver is missing pad control settings (pad delay and pad conf) for
the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
encounter CRC error on data transfers.
This patch adds default pad control settings for mt7620_compat.
Also a missing field .sclk_cycle_shift = 20 for mt7622 is added.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/mmc/mtk-sd.c | 122 +--
1 file changed, 119 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 4f9fa7d0ec..e30b16d56b 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -113,7 +113,51 @@
#define MSDC_PB2_RESPWAIT_M0x0c
#define MSDC_PB2_RESPWAIT_S2
+/* MSDC_PAD_CTRL0 */
+#define MSDC_PAD_CTRL0_CLKRDSEL_M 0xff00
+#define MSDC_PAD_CTRL0_CLKRDSEL_S 24
+#define MSDC_PAD_CTRL0_CLKTDSELBIT(20)
+#define MSDC_PAD_CTRL0_CLKIES BIT(19)
+#define MSDC_PAD_CTRL0_CLKSMT BIT(18)
+#define MSDC_PAD_CTRL0_CLKPU BIT(17)
+#define MSDC_PAD_CTRL0_CLKPD BIT(16)
+#define MSDC_PAD_CTRL0_CLKSR BIT(8)
+#define MSDC_PAD_CTRL0_CLKDRVP_M 0x70
+#define MSDC_PAD_CTRL0_CLKDRVP_S 4
+#define MSDC_PAD_CTRL0_CLKDRVN_M 0x7
+#define MSDC_PAD_CTRL0_CLKDRVN_S 0
+
+/* MSDC_PAD_CTRL1 */
+#define MSDC_PAD_CTRL1_CMDRDSEL_M 0xff00
+#define MSDC_PAD_CTRL1_CMDRDSEL_S 24
+#define MSDC_PAD_CTRL1_CMDTDSELBIT(20)
+#define MSDC_PAD_CTRL1_CMDIES BIT(19)
+#define MSDC_PAD_CTRL1_CMDSMT BIT(18)
+#define MSDC_PAD_CTRL1_CMDPU BIT(17)
+#define MSDC_PAD_CTRL1_CMDPD BIT(16)
+#define MSDC_PAD_CTRL1_CMDSR BIT(8)
+#define MSDC_PAD_CTRL1_CMDDRVP_M 0x70
+#define MSDC_PAD_CTRL1_CMDDRVP_S 4
+#define MSDC_PAD_CTRL1_CMDDRVN_M 0x7
+#define MSDC_PAD_CTRL1_CMDDRVN_S 0
+
+/* MSDC_PAD_CTRL2 */
+#define MSDC_PAD_CTRL2_DATRDSEL_M 0xff00
+#define MSDC_PAD_CTRL2_DATRDSEL_S 24
+#define MSDC_PAD_CTRL2_DATTDSELBIT(20)
+#define MSDC_PAD_CTRL2_DATIES BIT(19)
+#define MSDC_PAD_CTRL2_DATSMT BIT(18)
+#define MSDC_PAD_CTRL2_DATPU BIT(17)
+#define MSDC_PAD_CTRL2_DATPD BIT(16)
+#define MSDC_PAD_CTRL2_DATSR BIT(8)
+#define MSDC_PAD_CTRL2_DATDRVP_M 0x70
+#define MSDC_PAD_CTRL2_DATDRVP_S 4
+#define MSDC_PAD_CTRL2_DATDRVN_M 0x7
+#define MSDC_PAD_CTRL2_DATDRVN_S 0
+
/* PAD_TUNE */
+#define MSDC_PAD_TUNE_CLKTDLY_M0xf800
+#define MSDC_PAD_TUNE_CLKTDLY_S27
#define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c0
#define MSDC_PAD_TUNE_CMDRRDLY_S 22
#define MSDC_PAD_TUNE_CMD_SEL BIT(21)
@@ -129,6 +173,26 @@
#define PAD_CMD_TUNE_RX_DLY3 0x3E
#define PAD_CMD_TUNE_RX_DLY3_S 1
+/* PAD_TUNE0 */
+#define MSDC_PAD_TUNE0_DAT0RDDLY_M 0x1f00
+#define MSDC_PAD_TUNE0_DAT0RDDLY_S 24
+#define MSDC_PAD_TUNE0_DAT1RDDLY_M 0x1f
+#define MSDC_PAD_TUNE0_DAT1RDDLY_S 16
+#define MSDC_PAD_TUNE0_DAT2RDDLY_M 0x1f00
+#define MSDC_PAD_TUNE0_DAT2RDDLY_S 8
+#define MSDC_PAD_TUNE0_DAT3RDDLY_M 0x1f
+#define MSDC_PAD_TUNE0_DAT3RDDLY_S 0
+
+/* PAD_TUNE1 */
+#define MSDC_PAD_TUNE1_DAT4RDDLY_M 0x1f00
+#define MSDC_PAD_TUNE1_DAT4RDDLY_S 24
+#define MSDC_PAD_TUNE1_DAT5RDDLY_M 0x1f
+#define MSDC_PAD_TUNE1_DAT5RDDLY_S 16
+#define MSDC_PAD_TUNE1_DAT6RDDLY_M 0x1f00
+#define MSDC_PAD_TUNE1_DAT6RDDLY_S 8
+#define MSDC_PAD_TUNE1_DAT7RDDLY_M 0x1f
+#define MSDC_PAD_TUNE1_DAT7RDDLY_S 0
+
/* EMMC50_CFG0 */
#define EMMC50_CFG_CFCSTS_SEL BIT(4)
@@ -221,7 +285,10 @@ struct mtk_sd_regs {
u32 dat3_tune_crc;
u32 cmd_tune_crc;
u32 sdio_tune_wind;
- u32 reserved4[5];
+ u32 reserved4[2];
+ u32 pad_ctrl0;
+ u32 pad_ctrl1;
+ u32 pad_ctrl2;
u32 pad_tune;
u32 pad_tune0;
u32 pad_tune1;
@@ -263,6 +330,8 @@ struct msdc_compatible {
bool busy_check;
bool stop_clk_fix;
bool enhance_rx;
+ bool builtin_pad_ctrl;
+ bool default_pad_dly;
};
struct msdc_delay_phase {
@@ -1391,9 +1460,14 @@ static void msdc_init_hw(struct msdc_host *host)
{
u32 val;
void __iomem *tune_reg = >base->pad_tune;
+ void __iomem *rd_dly0_reg = >base->pad_tune0;
+ void __iomem *rd_dly1_reg = >base->pad_tune1;
- if (host->dev_comp->pad_tune0)
+ if (host->dev_comp->pad_tune0) {
tune_reg = >base->pad_tune0;
+ rd_dly0_reg = >base->dat_rd_dly[0];
+ rd_dly1_reg = >base->dat_rd_dly[1];
+ }
/* Configure to MMC/SD mode, clock free running */
setbits_le32(>base->msdc_cfg, MSDC_CFG_MODE);
@@ -1479,6 +1553,45 @@ static void msdc_init_hw(struct msdc_host *host)
setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
}
+
[PATCH v2 16/21] spi: add spi controller support for MediaTek MT7620 SoC
This patch adds spi controller support for MediaTek MT7620 SoC.
The SPI controller supports two chip selects. These two chip selects are
implemented as two separate register groups, but they share the same bus
(DI/DO/CLK), only CS pins are dedicated for each register group.
Appearently these two register groups cannot operates simulataneously so
they are implemented as one controller.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mt7620_spi.c | 277 +++
3 files changed, 285 insertions(+)
create mode 100644 drivers/spi/mt7620_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f7a9852565..ec50d843ef 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -202,6 +202,13 @@ config MSCC_BB_SPI
Enable MSCC bitbang SPI driver. This driver can be used on
MSCC SOCs.
+config MT7620_SPI
+ bool "MediaTek MT7620 SPI driver"
+ depends on SOC_MT7620
+ help
+ Enable the MT7620 SPI driver. This driver can be used to access
+ generic SPI devices on MediaTek MT7620 SoC.
+
config MT7621_SPI
bool "MediaTek MT7621 SPI driver"
depends on SOC_MT7628
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d9b5bd9b79..bfd142d153 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
+obj-$(CONFIG_MT7620_SPI) += mt7620_spi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
diff --git a/drivers/spi/mt7620_spi.c b/drivers/spi/mt7620_spi.c
new file mode 100644
index 00..c0b3d1d8eb
--- /dev/null
+++ b/drivers/spi/mt7620_spi.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao
+ *
+ * Generic SPI driver for MediaTek MT7620 SoC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MT7620_SPI_NUM_CS 2
+#define MT7620_SPI_MASTER1_OFF 0x00
+#define MT7620_SPI_MASTER2_OFF 0x40
+
+/* SPI_STAT */
+#define SPI_BUSY BIT(0)
+
+/* SPI_CFG */
+#define MSB_FIRSTBIT(8)
+#define SPI_CLK_POL BIT(6)
+#define RX_CLK_EDGE BIT(5)
+#define TX_CLK_EDGE BIT(4)
+#define SPI_CLK_S0
+#define SPI_CLK_MGENMASK(2, 0)
+
+/* SPI_CTL */
+#define START_WR BIT(2)
+#define START_RD BIT(1)
+#define SPI_HIGH BIT(0)
+
+#define SPI_ARB0xf0
+#define ARB_EN BIT(31)
+
+struct mt7620_spi_master_regs {
+ u32 stat;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 ctl;
+ u32 reserved1[2];
+ u32 data;
+};
+
+struct mt7620_spi {
+ void __iomem *regs;
+ struct mt7620_spi_master_regs *m[MT7620_SPI_NUM_CS];
+ unsigned int sys_freq;
+ u32 wait_us;
+ uint mode;
+ uint speed;
+};
+
+static void mt7620_spi_master_setup(struct mt7620_spi *ms, int cs)
+{
+ u32 rate, prescale, freq, tmo, cfg;
+
+ /* Calculate the clock divsior */
+ rate = DIV_ROUND_UP(ms->sys_freq, ms->speed);
+ rate = roundup_pow_of_two(rate);
+
+ prescale = ilog2(rate / 2);
+ if (prescale > 6)
+ prescale = 6;
+
+ /* Calculate the real clock, and usecs for one byte transaction */
+ freq = ms->sys_freq >> (prescale + 1);
+ tmo = DIV_ROUND_UP(8 * 100, freq);
+
+ /* 10 times tolerance plus 100us */
+ ms->wait_us = 10 * tmo + 100;
+
+ /* set SPI_CFG */
+ cfg = prescale << SPI_CLK_S;
+
+ switch (ms->mode & (SPI_CPOL | SPI_CPHA)) {
+ case SPI_MODE_0:
+ cfg |= TX_CLK_EDGE;
+ break;
+ case SPI_MODE_1:
+ cfg |= RX_CLK_EDGE;
+ break;
+ case SPI_MODE_2:
+ cfg |= SPI_CLK_POL | RX_CLK_EDGE;
+ break;
+ case SPI_MODE_3:
+ cfg |= SPI_CLK_POL | TX_CLK_EDGE;
+ break;
+ }
+
+ if (!(ms->mode & SPI_LSB_FIRST))
+ cfg |= MSB_FIRST;
+
+ writel(cfg, >m[cs]->cfg);
+
+ writel(SPI_HIGH, >m[cs]->ctl);
+}
+
+static void mt7620_spi_set_cs(struct mt7620_spi *ms, int cs, int enable)
+{
+ if (enable)
+ mt7620_spi_master_setup(ms, cs);
+
+ if (ms->mode & SPI_CS_HIGH)
+ enable = !enable;
+
+ if (enable)
+ clrbits_32(>m[cs]->ctl, SPI_HIGH);
+ else
+ setbits_32(>m[cs]->ctl, SPI_HIGH);
+}
+
+static int mt7620_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct mt7620_spi *ms = dev_get_priv(bus);
+
+ ms->mode = mode;
+
+ /* Mode 0 is
[PATCH v2 21/21] MAINTAINERS: add maintainer for MediaTek MIPS platform
Update maintainer for MediaTek MIPS platform Acked-by: Stefan Roese Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao --- v2 changes: none --- MAINTAINERS | 23 +++ 1 file changed, 23 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 857e236aa4..bcdc23c2e8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -800,6 +800,29 @@ F: drivers/mmc/ca_dw_mmc.c F: drivers/i2c/i2c-cortina.c F: drivers/i2c/i2c-cortina.h +MIPS MEDIATEK +M: Weijie Gao +R: GSS_MTK_Uboot_upstream +S: Maintained +F: arch/mips/mach-mtmips/ +F: arch/mips/dts/mt7620.dtsi +F: arch/mips/dts/mt7620-u-boot.dtsi +F: include/configs/mt7620.h +F: include/dt-bindings/clock/mt7620-clk.h +F: include/dt-bindings/clock/mt7628-clk.h +F: include/dt-bindings/reset/mt7620-reset.h +F: include/dt-bindings/reset/mt7628-reset.h +F: drivers/clk/mtmips/ +F: drivers/pinctrl/mtmips/ +F: drivers/gpio/mt7620_gpio.c +F: drivers/net/mt7620-eth.c +F: drivers/phy/mt7620-usb-phy.c +F: drivers/reset/reset-mtmips.c +F: drivers/serial/serial_mt7620.c +F: drivers/spi/mt7620_spi.c +F: drivers/sysreset/sysreset_resetctl.c +F: drivers/watchdog/mt7620_wdt.c + MIPS MSCC M: Gregory CLEMENT M: Lars Povlsen -- 2.17.1
[PATCH v2 20/21] reset: reset-mtmips: add DM_FLAG_PRE_RELOC flag
Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can
be probed before relocation even if u-boot,dm-pre-reloc is not present
in the dts.
Signed-off-by: Weijie Gao
---
v2 changes: new
---
drivers/reset/reset-mtmips.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c
index bc20e3335c..0d6a446465 100644
--- a/drivers/reset/reset-mtmips.c
+++ b/drivers/reset/reset-mtmips.c
@@ -82,4 +82,5 @@ U_BOOT_DRIVER(mtmips_reset) = {
.probe = mtmips_reset_probe,
.priv_auto_alloc_size = sizeof(struct mtmips_reset_priv),
.ops = _reset_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
--
2.17.1
Re: Using USB Mass Storage on AM335X
+ Pratyush On 30/10/20 11:36 am, Heiko Schocher wrote: > Hello Otavio, > > Am 29.10.2020 um 23:19 schrieb Otavio Salvador: >> Hi, >> >> I am working on porting mainline U-Boot to a custom AM335X board that >> only has eMMC as the boot medium. >> >> I can load U-Boot via serial boot and flash MLO and u-boot.img into >> the eMMC using DFU. Then the board boots successfully via eMMC. >> >> Now I want to run the "ums" command to be able to mount the eMMC on >> the host. The problem I am getting is that when I select >> CONFIG_CMD_USB_MASS_STORAGE=y the board no longer boots. >> >> Does anyone know why selecting CONFIG_CMD_USB_MASS_STORAGE=y causes >> the board to not boot anymore? > > Not really ... I cannot see, which impact activating this command > has with not booting ... > > May some problem with image size? Early malloc space, some addresses > which now overlap? Good point. Just to avoid this scenario, can you make sure UMS is enabled only in U-Boot and not in SPL? or you can try with old MLO with new U-Boot :). As Heiko already asked, can you provide more details in the failing scenario? Thanks and regards, Lokesh
[PATCH] fs/squashfs: Fix index off by 1 for inode SQFS_LDIR_TYPE
I've created a squashfs file system with Yocto (it use squashfs-tools)
and u-boot command sqfsls give the error:'Error while searching inode:
unknown type.'
After some digging in the code I found that the index is off by 1.
This patch fix this issue and I can successful use the sqfsls command.
After search for the squashfs format I found a link talk about a
similar issue but this time in the documentation. The link is:
https://github.com/AgentD/squashfs-tools-ng/commit/e6588526838caece9529
Signed-off-by: Gerard Koskamp
CC: Joao Marcos Costa
---
fs/squashfs/sqfs_inode.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/fs/squashfs/sqfs_inode.c b/fs/squashfs/sqfs_inode.c
index 14d70cf..0983974 100644
--- a/fs/squashfs/sqfs_inode.c
+++ b/fs/squashfs/sqfs_inode.c
@@ -49,7 +49,7 @@ int sqfs_inode_size(struct squashfs_base_inode *inode, u32
blk_size)
return sizeof(*ldir);
di = ldir->index;
- while (l < i_count + 1) {
+ while (l < i_count) {
sz = get_unaligned_le32(>size) + 1;
index_list_size += sz;
di = (void *)di + sizeof(*di) + sz;
@@ -57,7 +57,7 @@ int sqfs_inode_size(struct squashfs_base_inode *inode, u32
blk_size)
}
return sizeof(*ldir) + index_list_size +
- (i_count + 1) * SQFS_DIR_INDEX_BASE_LENGTH;
+ i_count * SQFS_DIR_INDEX_BASE_LENGTH;
}
case SQFS_LREG_TYPE: {
--
2.7.4
[RESEND PATCH v1] verdin-imx8mm: enable fdt overlays and env importing
From: Igor Opaniuk Enable CONFIG_CMD_IMPORTENV and CONFIG_OF_LIBFDT_OVERLAY needed for booting regular Toradex BSP images. Signed-off-by: Igor Opaniuk --- configs/verdin-imx8mm_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index d856e3a318..60e5b03290 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -41,7 +41,6 @@ CONFIG_SYS_PROMPT="Verdin iMX8MM # " # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y CONFIG_SYS_MEMTEST_START=0x4000 @@ -103,3 +102,4 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.17.1
Re: [patch v2 01/10] drivers/video/rockchip/rk_vop.c: Use endpoint compatible string to find VOP mode
Hi Arnaud,
Thanks for your patch.
Please use module name as subject prefix instead of a file name,
eg. "rockchip: video: vop".
On 2020/10/27 下午9:21, Arnaud Patard (Rtp) wrote:
The current code is using an hard coded enum and the of node reg value of
endpoint to find out if the endpoint is mipi/hdmi/lvds/edp/dp. The order
is different between rk3288, rk3399 vop little, rk3399 vop big.
A possible solution would be to make sure that the rk3288.dtsi and
rk3399.dtsi files have "expected" reg value or an other solution is
to find the kind of endpoint by comparing the endpoint compatible value.
This patch is implementing the more flexible second solution.
Signed-off-by: Arnaud Patard
Index: u-boot/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
===
--- u-boot.orig/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ u-boot/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
For the patch format, please make sure the u-boot is the root directory.
Thanks,
- Kever
@@ -85,26 +85,13 @@ enum {
LB_RGB_1280X8 = 0x5
};
-#if defined(CONFIG_ROCKCHIP_RK3399)
enum vop_modes {
VOP_MODE_EDP = 0,
VOP_MODE_MIPI,
VOP_MODE_HDMI,
- VOP_MODE_MIPI1,
- VOP_MODE_DP,
- VOP_MODE_NONE,
-};
-#else
-enum vop_modes {
- VOP_MODE_EDP = 0,
- VOP_MODE_HDMI,
VOP_MODE_LVDS,
- VOP_MODE_MIPI,
- VOP_MODE_NONE,
- VOP_MODE_AUTO_DETECT,
- VOP_MODE_UNKNOWN,
+ VOP_MODE_DP,
};
-#endif
/* VOP_VERSION_INFO */
#define M_FPGA_VERSION (0x << 16)
Index: u-boot/drivers/video/rockchip/rk_vop.c
===
--- u-boot.orig/drivers/video/rockchip/rk_vop.c
+++ u-boot/drivers/video/rockchip/rk_vop.c
@@ -235,12 +235,11 @@ static int rk_display_init(struct udevic
struct clk clk;
enum video_log2_bpp l2bpp;
ofnode remote;
+ const char *compat;
debug("%s(%s, %lu, %s)\n", __func__,
dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
- vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
- debug("vop_id=%d\n", vop_id);
ret = ofnode_read_u32(ep_node, "remote-endpoint", _phandle);
if (ret)
return ret;
@@ -282,6 +281,28 @@ static int rk_display_init(struct udevic
if (disp)
break;
};
+ compat = ofnode_get_property(remote, "compatible", NULL);
+ if (!compat) {
+ debug("%s(%s): Failed to find compatible property\n",
+ __func__, dev_read_name(dev));
+ return -EINVAL;
+ }
+ if (strstr(compat, "edp")) {
+ vop_id = VOP_MODE_EDP;
+ } else if (strstr(compat, "mipi")) {
+ vop_id = VOP_MODE_MIPI;
+ } else if (strstr(compat, "hdmi")) {
+ vop_id = VOP_MODE_HDMI;
+ } else if (strstr(compat, "cdn-dp")) {
+ vop_id = VOP_MODE_DP;
+ } else if (strstr(compat, "lvds")) {
+ vop_id = VOP_MODE_LVDS;
+ } else {
+ debug("%s(%s): Failed to find vop mode for %s\n",
+ __func__, dev_read_name(dev), compat);
+ return -EINVAL;
+ }
+ debug("vop_id=%d\n", vop_id);
disp_uc_plat = dev_get_uclass_platdata(disp);
debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
Re: [PATCH v1] verdinx-imx8mm: enable fdt overlays and env importing
On Fri, Oct 30, 2020 at 4:53 PM Igor Opaniuk wrote: > > From: Igor Opaniuk > > Enable CONFIG_CMD_IMPORTENV and CONFIG_OF_LIBFDT_OVERLAY needed > for booting regular Toradex BSP images. > > Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov > --- > > configs/verdin-imx8mm_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig > index d856e3a318..60e5b03290 100644 > --- a/configs/verdin-imx8mm_defconfig > +++ b/configs/verdin-imx8mm_defconfig > @@ -41,7 +41,6 @@ CONFIG_SYS_PROMPT="Verdin iMX8MM # " > # CONFIG_BOOTM_NETBSD is not set > CONFIG_CMD_ASKENV=y > # CONFIG_CMD_EXPORTENV is not set > -# CONFIG_CMD_IMPORTENV is not set > # CONFIG_CMD_CRC32 is not set > CONFIG_CMD_MEMTEST=y > CONFIG_SYS_MEMTEST_START=0x4000 > @@ -103,3 +102,4 @@ CONFIG_SYSRESET_PSCI=y > CONFIG_SYSRESET_WATCHDOG=y > CONFIG_DM_THERMAL=y > CONFIG_IMX_WATCHDOG=y > +CONFIG_OF_LIBFDT_OVERLAY=y > -- > 2.17.1 > -- Best regards Oleksandr Suvorov Toradex AG Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00
Re: [PATCH v1] verdinx-imx8mm: enable fdt overlays and env importing
On Fri, Oct 30, 2020 at 5:15 PM Oleksandr Suvorov wrote: > > On Fri, Oct 30, 2020 at 4:53 PM Igor Opaniuk wrote: > > > > From: Igor Opaniuk > > > > Enable CONFIG_CMD_IMPORTENV and CONFIG_OF_LIBFDT_OVERLAY needed > > for booting regular Toradex BSP images. > > > > Signed-off-by: Igor Opaniuk > > NOT :) Reviewed-by: Oleksandr Suvorov A wrong patch answered. > > > --- > > > > configs/verdin-imx8mm_defconfig | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/configs/verdin-imx8mm_defconfig > > b/configs/verdin-imx8mm_defconfig > > index d856e3a318..60e5b03290 100644 > > --- a/configs/verdin-imx8mm_defconfig > > +++ b/configs/verdin-imx8mm_defconfig > > @@ -41,7 +41,6 @@ CONFIG_SYS_PROMPT="Verdin iMX8MM # " > > # CONFIG_BOOTM_NETBSD is not set > > CONFIG_CMD_ASKENV=y > > # CONFIG_CMD_EXPORTENV is not set > > -# CONFIG_CMD_IMPORTENV is not set > > # CONFIG_CMD_CRC32 is not set > > CONFIG_CMD_MEMTEST=y > > CONFIG_SYS_MEMTEST_START=0x4000 > > @@ -103,3 +102,4 @@ CONFIG_SYSRESET_PSCI=y > > CONFIG_SYSRESET_WATCHDOG=y > > CONFIG_DM_THERMAL=y > > CONFIG_IMX_WATCHDOG=y > > +CONFIG_OF_LIBFDT_OVERLAY=y > > -- > > 2.17.1 > > > > > -- > Best regards > Oleksandr Suvorov > > Toradex AG > Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00 -- Best regards Oleksandr Suvorov Toradex AG Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00
Re: [RESEND PATCH v1] verdin-imx8mm: enable fdt overlays and env importing
On Fri, Oct 30, 2020 at 4:55 PM Igor Opaniuk wrote: > > From: Igor Opaniuk > > Enable CONFIG_CMD_IMPORTENV and CONFIG_OF_LIBFDT_OVERLAY needed > for booting regular Toradex BSP images. > > Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov > --- > > configs/verdin-imx8mm_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig > index d856e3a318..60e5b03290 100644 > --- a/configs/verdin-imx8mm_defconfig > +++ b/configs/verdin-imx8mm_defconfig > @@ -41,7 +41,6 @@ CONFIG_SYS_PROMPT="Verdin iMX8MM # " > # CONFIG_BOOTM_NETBSD is not set > CONFIG_CMD_ASKENV=y > # CONFIG_CMD_EXPORTENV is not set > -# CONFIG_CMD_IMPORTENV is not set > # CONFIG_CMD_CRC32 is not set > CONFIG_CMD_MEMTEST=y > CONFIG_SYS_MEMTEST_START=0x4000 > @@ -103,3 +102,4 @@ CONFIG_SYSRESET_PSCI=y > CONFIG_SYSRESET_WATCHDOG=y > CONFIG_DM_THERMAL=y > CONFIG_IMX_WATCHDOG=y > +CONFIG_OF_LIBFDT_OVERLAY=y > -- > 2.17.1 > -- Best regards Oleksandr Suvorov Toradex AG Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00
Re: [PATCH] video: rockchip: Add missing dpcd_write() call to link_train_ce()
On 2020/10/7 上午4:39, Alper Nebi Yasak wrote:
Found this by comparing it to the coreboot driver, a form of this call
was introduced there in their commit b9a7877568cf ("rockchip/*: refactor
edp driver"). This is copy-pasted from U-Boot's link_train_cr() slightly
above it.
Without this on a gru-kevin chromebook, I have:
clock recovery at voltage 0 pre-emphasis 0
requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
using signal parameters: voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
using signal parameters: voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
using signal parameters: voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
using signal parameters: voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
using signal parameters: voltage 0.4V pre_emph 3.5dB
channel eq failed, ret=-5
link train failed!
rk_vop_probe() Device failed: ret=-5
With this, it looks like training succeeds:
clock recovery at voltage 0 pre-emphasis 0
requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
using signal parameters: voltage 0.4V pre_emph 3.5dB
requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB
requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB
requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB
requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB
using signal parameters: voltage 0.4V pre_emph 6dB
requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB
requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB
requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB
requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB
using signal parameters: voltage 0.4V pre_emph 0dB
channel eq at voltage 0 pre-emphasis 0
config video failed
rk_vop_probe() Device failed: ret=-110
The "config video failed" error also goes away when I disable higher
log levels, and it claims to have successfully probed the device.
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Kever Yang
Thanks,
- Kever
---
I'm testing this with a lot of other patches to make the board work. The
actual tree I'm using is available here:
https://github.com/alpernebbi/u-boot/commits/rk3399-gru-kevin/wip
(currently at commit c0dc4b42afe770671ce7bb0dd519d894a3acdea0)
drivers/video/rockchip/rk_edp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 000bd48140..a032eb6889 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -559,6 +559,12 @@ static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
channel_eq = 0;
for (tries = 0; tries < 5; tries++) {
rk_edp_set_link_training(edp, edp->train_set);
+ ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
+ edp->train_set,
+ edp->link_train.lane_count);
+ if (ret)
+ return ret;
+
udelay(400);
if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
RE: [PATCH v4 2/3] armv8: lx2162a: Add Soc changes to support LX2162A
> -Original Message- > From: Tom Rini > Sent: Thursday, October 29, 2020 8:14 PM > To: Meenakshi Aggarwal > Cc: u-boot@lists.denx.de; Priyanka Jain ; Varun Sethi > > Subject: Re: [PATCH v4 2/3] armv8: lx2162a: Add Soc changes to support > LX2162A > > On Thu, Oct 29, 2020 at 07:16:16PM +0530, meenakshi.aggar...@nxp.com > wrote: > > > From: Meenakshi Aggarwal > > > > LX2162 is LX2160 based SoC, it has same die as of LX2160 with > > different packaging. > > > > LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, > > microSD card, eMMC support, serial console, qspi nor flash, qsgmii, > > sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes > > interface to support three PCIe gen3 interface. > > > > Signed-off-by: Meenakshi Aggarwal > > --- > > arch/arm/cpu/armv8/Kconfig | 2 +- > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +-- > > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 ++ > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 7 ++- > > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 > ++ > > A follow up to convert README.soc to rST and move it with the rest of our rST > documentation would be appreciated, thanks. [Meenakshi Aggarwal] We are planning this, but will be in a separate patch. > > -- > Tom
Re: [PATCH] ram: rockchip: px30: add a config-based ddr selection
> On 01.10.2020, at 20:40, Heiko Stuebner wrote: > > From: Heiko Stuebner > > The SRAM on the PX30 is not big enough to hold multiple DDR configs > so it needs to be selected during build. > > So far simply the DDR3 config was always selected and getting DDR4 > or LPDDR2/3 initialized would require a code modification. > > So add Kconfig options similar to RK3399 to allow selecting the DDR4 > and LPDDR2/3 options instead, while DDR3 stays the default as before. > > Signed-off-by: Heiko Stuebner Reviewed-by: Philipp Tomsich
[u-boot PATCH] configs: am65/j72x: Set CONFIG_LOGLEVEL to 7
By default CONFIG_LOGLEVEL seems to be set to 4 which is
too low and doesn't show dev_info/dev_notice/dev_warn
messages on console. This has been deliberately set low
globally to be conservative setting across the board due to
primary bootloader size limitations. It is best to tune
per board config as per user needs.
On K3 we have separate SPL and u-boot configs so we
can afford to set u-boot CONFIG_LOGLEVEL to 7.
On AM65 this patch causes u-boot.img size to change from
932KB to 940KB with 1 line additional print during
MMC boot. i.e. details of Net subsystem
"Net: K3 CPSW: nuss_ver: 0x6BA00102 cpsw_ver: 0x6BA80102 ale_ver: 0x00293904
Ports:1 mdio_freq:100"
Similar 8KB difference was seen on J721E.
Signed-off-by: Roger Quadros
Reviewed-by: Nishanth Menon
---
configs/am65x_evm_a53_defconfig| 1 +
configs/am65x_hs_evm_a53_defconfig | 1 +
configs/j7200_evm_a72_defconfig| 1 +
configs/j721e_evm_a72_defconfig| 1 +
configs/j721e_hs_evm_a72_defconfig | 1 +
5 files changed, 5 insertions(+)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 8a94ad1530..941073ce7f 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_LOGLEVEL=7
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
diff --git a/configs/am65x_hs_evm_a53_defconfig
b/configs/am65x_hs_evm_a53_defconfig
index 2c7217afb6..7d467c167e 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_LOGLEVEL=7
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 7c900b1d2e..1d2526b5f1 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 6de8666956..982e3df2f2 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
diff --git a/configs/j721e_hs_evm_a72_defconfig
b/configs/j721e_hs_evm_a72_defconfig
index acbc04359c..28bf56e7e1 100644
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Re: [PATCH] dm: soc: Add SoC id for attribute matching
Hi,
On 10/30/20 9:07 AM, Biju Das wrote:
Add SoC identification string for attribute matching.
Also changed the comments from "an SOC" to "a SoC".
This is not a correct change, "an" should be used if the word that
follows starts with a vowel sound, which "SoC" does.
"SOC" could be changed to "SoC", no strong feelings there.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
drivers/soc/soc-uclass.c | 19 ++-
drivers/soc/soc_sandbox.c | 8
include/soc.h | 39 +--
test/dm/soc.c | 8
4 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index c32d647864..a3f8be841b 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -46,6 +46,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int
size)
return ops->get_revision(dev, buf, size);
}
+int soc_get_soc_id(struct udevice *dev, char *buf, int size)
Is there any additional background here? Why is soc_id needed? Can
"machine" not meet the same purpose?
My thought was "family" would cover a range of parts and "machine" was
to be a specific SoC. Is a more specific ID needed?
+{
+ struct soc_ops *ops = soc_get_ops(dev);
+
+ if (!ops->get_soc_id)
+ return -ENOSYS;
+
+ return ops->get_soc_id(dev, buf, size);
+}
+
const struct soc_attr *
soc_device_match(const struct soc_attr *matches)
{
@@ -61,7 +71,7 @@ soc_device_match(const struct soc_attr *matches)
while (1) {
if (!(matches->machine || matches->family ||
- matches->revision))
+ matches->revision || matches->soc_id))
break;
match = true;
@@ -87,6 +97,13 @@ soc_device_match(const struct soc_attr *matches)
}
}
+ if (matches->soc_id) {
+ if (!soc_get_soc_id(soc, str, SOC_MAX_STR_SIZE)) {
+ if (strcmp(matches->soc_id, str))
+ match = false;
+ }
+ }
+
if (match)
return matches;
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 5c82ad84fc..1a81d3562a 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -31,10 +31,18 @@ int soc_sandbox_get_revision(struct udevice *dev, char
*buf, int size)
return 0;
}
+int soc_sandbox_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+ snprintf(buf, size, "r8a774a1");
+
+ return 0;
+}
+
static const struct soc_ops soc_sandbox_ops = {
.get_family = soc_sandbox_get_family,
.get_revision = soc_sandbox_get_revision,
.get_machine = soc_sandbox_get_machine,
+ .get_soc_id = soc_sandbox_get_soc_id,
};
int soc_sandbox_probe(struct udevice *dev)
diff --git a/include/soc.h b/include/soc.h
index a55eb1b572..ae7b36846f 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -20,18 +20,20 @@
* variants. Example: am33
* @machine - Name of a specific SoC. Example: am3352
* @revision - Name of a specific SoC revision. Example: SR1.1
+ * @soc_id - SoC identification String. Example: r8a774a1
* @data - A pointer to user data for the SoC variant
*/
struct soc_attr {
const char *family;
const char *machine;
const char *revision;
+ const char *soc_id;
const void *data;
};
struct soc_ops {
/**
-* get_machine() - Get machine name of an SOC
+* get_machine() - Get machine name of a SoC
*
* @dev:Device to check (UCLASS_SOC)
* @buf:Buffer to place string
@@ -41,7 +43,7 @@ struct soc_ops {
int (*get_machine)(struct udevice *dev, char *buf, int size);
/**
-* get_revision() - Get revision name of a SOC
+* get_revision() - Get revision name of a SoC
*
* @dev:Device to check (UCLASS_SOC)
* @buf:Buffer to place string
@@ -51,7 +53,7 @@ struct soc_ops {
int (*get_revision)(struct udevice *dev, char *buf, int size);
/**
-* get_family() - Get family name of an SOC
+* get_family() - Get family name of a SoC
*
* @dev:Device to check (UCLASS_SOC)
* @buf:Buffer to place string
@@ -59,6 +61,16 @@ struct soc_ops {
* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
*/
int (*get_family)(struct udevice *dev, char *buf, int size);
+
+ /**
+* get_soc_id() - Get SoC identification name of a SoC
+*
+* @dev:Device to check (UCLASS_SOC)
+* @buf:Buffer to place string
+* @size: Size of string space
+* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on
RE: [PATCH] dm: soc: Add SoC id for attribute matching
Hi Dave,
Thanks for the feedback.
> Subject: Re: [PATCH] dm: soc: Add SoC id for attribute matching
>
> Hi,
>
> On 10/30/20 9:07 AM, Biju Das wrote:
> > Add SoC identification string for attribute matching.
> > Also changed the comments from "an SOC" to "a SoC".
>
> This is not a correct change, "an" should be used if the word that follows
> starts with a vowel sound, which "SoC" does.
Agreed. Will change back to an SoC on V2.
The below one still uses "a SOC". Will change to "an SoC" as well.
-* get_revision() - Get revision name of a SOC
+* get_revision() - Get revision name of a SoC
> "SOC" could be changed to "SoC", no strong feelings there.
OK.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Lad Prabhakar lad...@bp.renesas.com>
> > ---
> > drivers/soc/soc-uclass.c | 19 ++-
> > drivers/soc/soc_sandbox.c | 8
> > include/soc.h | 39 +--
> > test/dm/soc.c | 8
> > 4 files changed, 67 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c index
> > c32d647864..a3f8be841b 100644
> > --- a/drivers/soc/soc-uclass.c
> > +++ b/drivers/soc/soc-uclass.c
> > @@ -46,6 +46,16 @@ int soc_get_revision(struct udevice *dev, char *buf,
> int size)
> > return ops->get_revision(dev, buf, size);
> > }
> >
> > +int soc_get_soc_id(struct udevice *dev, char *buf, int size)
> Is there any additional background here? Why is soc_id needed? Can
> "machine" not meet the same purpose?
Renesas SoC and other SoC vendors use SoC_ID for SoC identification.See the
details here [1]
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/renesas/renesas-soc.c?h=v5.10-rc1
Please see other SoC vendors as well [2] which uses SoC_ID for identification.
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/samsung/exynos-chipid.c?h=v5.10-rc1
> My thought was "family" would cover a range of parts and "machine" was to
> be a specific SoC. Is a more specific ID needed?
Yes, Please see above.
Family in over case is: RCar Gen3 SoC family or RZ/G2 SoC family
Machine is Name of machine for eg;- "HopeRun HiHope RZ/G2M with sub board"
SoC_ID is some thing SoC specific for eg:- r8a774a1
Revision is : ES x.y.
I think in your case, it is different??
>
> > +{
> > + struct soc_ops *ops = soc_get_ops(dev);
> > +
> > + if (!ops->get_soc_id)
> > + return -ENOSYS;
> > +
> > + return ops->get_soc_id(dev, buf, size); }
> > +
> > const struct soc_attr *
> > soc_device_match(const struct soc_attr *matches)
> > {
> > @@ -61,7 +71,7 @@ soc_device_match(const struct soc_attr *matches)
> >
> > while (1) {
> > if (!(matches->machine || matches->family ||
> > - matches->revision))
> > + matches->revision || matches->soc_id))
> > break;
> >
> > match = true;
> > @@ -87,6 +97,13 @@ soc_device_match(const struct soc_attr *matches)
> > }
> > }
> >
> > + if (matches->soc_id) {
> > + if (!soc_get_soc_id(soc, str, SOC_MAX_STR_SIZE)) {
> > + if (strcmp(matches->soc_id, str))
> > + match = false;
> > + }
> > + }
> > +
> > if (match)
> > return matches;
> >
> > diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
> > index 5c82ad84fc..1a81d3562a 100644
> > --- a/drivers/soc/soc_sandbox.c
> > +++ b/drivers/soc/soc_sandbox.c
> > @@ -31,10 +31,18 @@ int soc_sandbox_get_revision(struct udevice *dev,
> char *buf, int size)
> > return 0;
> > }
> >
> > +int soc_sandbox_get_soc_id(struct udevice *dev, char *buf, int size)
> > +{
> > + snprintf(buf, size, "r8a774a1");
> > +
> > + return 0;
> > +}
> > +
> > static const struct soc_ops soc_sandbox_ops = {
> > .get_family = soc_sandbox_get_family,
> > .get_revision = soc_sandbox_get_revision,
> > .get_machine = soc_sandbox_get_machine,
> > + .get_soc_id = soc_sandbox_get_soc_id,
> > };
> >
> > int soc_sandbox_probe(struct udevice *dev) diff --git
> > a/include/soc.h b/include/soc.h index a55eb1b572..ae7b36846f 100644
> > --- a/include/soc.h
> > +++ b/include/soc.h
> > @@ -20,18 +20,20 @@
> >* variants. Example: am33
> >* @machine - Name of a specific SoC. Example: am3352
> >* @revision - Name of a specific SoC revision. Example: SR1.1
> > + * @soc_id - SoC identification String. Example: r8a774a1
> >* @data - A pointer to user data for the SoC variant
> >*/
> > struct soc_attr {
> > const char *family;
> > const char *machine;
> > const char *revision;
> > + const char *soc_id;
> > const void *data;
> > };
> >
> > struct soc_ops {
> > /**
> > -* get_machine() - Get machine name of an SOC
[PATCH v1] verdinx-imx8mm: enable fdt overlays and env importing
From: Igor Opaniuk Enable CONFIG_CMD_IMPORTENV and CONFIG_OF_LIBFDT_OVERLAY needed for booting regular Toradex BSP images. Signed-off-by: Igor Opaniuk --- configs/verdin-imx8mm_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index d856e3a318..60e5b03290 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -41,7 +41,6 @@ CONFIG_SYS_PROMPT="Verdin iMX8MM # " # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y CONFIG_SYS_MEMTEST_START=0x4000 @@ -103,3 +102,4 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.17.1
Re: [PATCH 0/3] mmc support for QEMU
Hi, I didn't include changes in the defconfig because you need to manually add the device to the QEMU virt machine via the command line. On the other hand the u-boot binary size does not really matter for QEMU environments. For CI it will also be nice to ensure this set-up will build. I'll send in a patch for the config when this series has been merged! Kind regards, Harm -Original Message- From: Bin Meng To: Harm Berntsen Cc: u-boot@lists.denx.de Subject: Re: [PATCH 0/3] mmc support for QEMU Date: Fri, 30 Oct 2020 22:34:10 +0800 On Fri, Oct 30, 2020 at 6:56 PM Harm Berntsen wrote: > > Hi, > > This patch series allows you to use a mmc drive from within QEMU: > > 1. make qemu_arm_defconfig > 2. Enable the CONFIG_DM_MMC, CONFIG_MMC_PCI, CONFIG_MMC_SDHCI options > 3. Run quemu as follows: > > qemu-system-arm > -machine virt,highmem=off \ > -device sdhci-pci \ > -device sd-card,drive=mydrive \ > -drive id=mydrive,if=none,format=raw,file=mmcblk0.bin \ > -bios u-boot.bin I don't see changes made to qemu_arm_defconfig. Is that a future patch? > > The MMC image can now be used to boot :) > Regards, Bin
Re: [PATCH 3/4] video: rockchip: Support 4K resolution for rk3288, HDMI
On 2020/10/24 上午3:57, Jagan Teki wrote: Like, rk3399 the rk3288 also supports 4K resolution. So, enable it for rk3288 with HDMI platforms. Right now, rockchip video drivers are supporting for rk3288, rk3399 SoC families, so mark the 4K resolution by default if it's an HDMI video out. Signed-off-by: Jagan Teki Cc: Anatolij Gustschin Reviewed-by: Kever Yang Thanks, - Kever --- drivers/video/rockchip/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 5215a71f99..0ade631bd5 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -22,7 +22,7 @@ menuconfig VIDEO_ROCKCHIP config VIDEO_ROCKCHIP_MAX_XRES int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP - default 3840 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI + default 3840 if DISPLAY_ROCKCHIP_HDMI default 1920 help The maximum horizontal resolution to support for the framebuffer. @@ -32,7 +32,7 @@ config VIDEO_ROCKCHIP_MAX_XRES config VIDEO_ROCKCHIP_MAX_YRES int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP - default 2160 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI + default 2160 if DISPLAY_ROCKCHIP_HDMI default 1080 help The maximum vertical resolution to support for the framebuffer.
Re: [PATCH 4/4] rockchip: Enable Console MUX in ROCKPi N8
On 2020/10/24 上午3:57, Jagan Teki wrote: Enable Console multiplexing in ROCKPi N8 which would is required to video out the console buffer. Enable it. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- configs/rock-pi-n8-rk3288_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index e5bc035926..380a58c5c4 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -16,7 +16,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-rock-pi-n8.dtb" CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Re: [PATCH 2/4] arm64: dts: rockchip: Add chosen node for ROCK-Pi N8
On 2020/10/24 上午3:57, Jagan Teki wrote:
Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board.
This will help to get serial out messages.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
index e9d7404ed9..538607dd73 100644
--- a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi
@@ -5,6 +5,12 @@
#include "rk3288-u-boot.dtsi"
+/{
+ chosen {
+ stdout-path =
+ };
+};
+
{
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
Re: [PATCH 1/4] rockchip: Enable Console MUX in ROCKPi N10
On 2020/10/24 上午3:57, Jagan Teki wrote: Enable Console multiplexing in ROCKPi N10 which would is required to video out the console buffer. Enable it. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- configs/rock-pi-n10-rk3399pro_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 3255e01512..b1c7b9abe6 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10" CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" -# CONFIG_CONSOLE_MUX is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Re: [PATCH] km/arm: coding style clean up
On 30.10.20 12:45, Holger Brunck wrote:
Address most of the checkpatch issues we found in km_arm and common km
code.
CC: Stefan Roese
CC: Valentin Longchamp
Signed-off-by: Holger Brunck
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
board/keymile/common/common.c | 44 ---
board/keymile/common/ivm.c | 84 ++---
board/keymile/km_arm/fpga_config.c | 16 +++---
board/keymile/km_arm/km_arm.c | 41 +++---
include/configs/km/keymile-common.h | 4 +-
include/configs/km/km_arm.h | 2 +-
6 files changed, 96 insertions(+), 95 deletions(-)
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 03c7ce9da7..df507e2790 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -56,7 +56,7 @@ int set_km_env(void)
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
- if (p != NULL)
+ if (p)
strict_strtoul(p, 16, );
pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
CONFIG_KM_PNVRAM) / 0x400;
@@ -165,7 +165,7 @@ static int do_setboardid(struct cmd_tbl *cmdtp, int flag,
int argc,
char *p;
p = get_local_var("IVM_BoardId");
- if (p == NULL) {
+ if (!p) {
printf("can't get the IVM_Boardid\n");
return 1;
}
@@ -174,7 +174,7 @@ static int do_setboardid(struct cmd_tbl *cmdtp, int flag,
int argc,
printf("set boardid=%s\n", buf);
p = get_local_var("IVM_HWKey");
- if (p == NULL) {
+ if (!p) {
printf("can't get the IVM_HWKey\n");
return 1;
}
@@ -186,8 +186,8 @@ static int do_setboardid(struct cmd_tbl *cmdtp, int flag,
int argc,
return 0;
}
-U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid", "read out bid and "
-"hwkey from IVM and set in environment");
+U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid",
+ "read out bid and hwkey from IVM and set in environment");
/*
* command km_checkbidhwk
@@ -218,14 +218,14 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
* already stored in the local hush variables
*/
p = get_local_var("IVM_BoardId");
- if (p == NULL) {
+ if (!p) {
printf("can't get the IVM_Boardid\n");
return 1;
}
rc = strict_strtoul(p, 16, );
p = get_local_var("IVM_HWKey");
- if (p == NULL) {
+ if (!p) {
printf("can't get the IVM_HWKey\n");
return 1;
}
@@ -238,10 +238,10 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
/* now try to read values from environment if available */
p = env_get("boardid");
- if (p != NULL)
+ if (p)
rc = strict_strtoul(p, 16, );
p = env_get("hwkey");
- if (p != NULL)
+ if (p)
rc = strict_strtoul(p, 16, );
if (rc != 0) {
@@ -263,9 +263,8 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
if (verbose) {
printf("IVM_BoardId: %ld, IVM_HWKey=%ld\n",
- ivmbid, ivmhwkey);
- printf("boardIdHwKeyList: %s\n",
- bidhwklist);
+ ivmbid, ivmhwkey);
+ printf("boardIdHwKeyList: %s\n", bidhwklist);
}
while (!found) {
/* loop over each bid/hwkey pair in the list */
@@ -291,13 +290,13 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
while (*rest && !isxdigit(*rest))
rest++;
}
- if ((!bid) || (!hwkey)) {
+ if (!bid || !hwkey) {
/* end of list */
break;
}
if (verbose) {
printf("trying bid=0x%lX, hwkey=%ld\n",
- bid, hwkey);
+ bid, hwkey);
}
/*
* Compare the values of the found entry in the
@@ -305,7 +304,7 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
* in the inventory eeprom. If they are equal
* set the values in environment variables.
*/
-
Re: [PATCH v4 6/8] arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0
On 2020/10/28 下午9:33, Jagan Teki wrote: Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Reviewed-by: Kever Yang Thanks, - Kever --- Changes for v4: - none arch/arm/dts/px30-engicam-ctouch2.dtsi | 8 1 file changed, 8 insertions(+) create mode 100644 arch/arm/dts/px30-engicam-ctouch2.dtsi diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi new file mode 100644 index 00..58425b1e55 --- /dev/null +++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi"
Re: [PATCH v4 7/8] rockchip: Add Engicam PX30.Core C.TOUCH 2.0
On 2020/10/28 下午9:33, Jagan Teki wrote:
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Suniel Mahesh
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v4:
- none
arch/arm/dts/Makefile| 1 +
arch/arm/dts/px30-px30-core-ctouch2.dts | 22 +
arch/arm/mach-rockchip/px30/Kconfig | 7 ++
board/engicam/px30_core/MAINTAINERS | 6 ++
configs/px30-core-ctouch2-px30_defconfig | 108 +++
5 files changed, 144 insertions(+)
create mode 100644 arch/arm/dts/px30-px30-core-ctouch2.dts
create mode 100644 configs/px30-core-ctouch2-px30_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b87f4334a5..658617d4dc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
+ px30-px30-core-ctouch2.dtb \
px30-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-px30-core-ctouch2.dts
new file mode 100644
index 00..2da0128188
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core-ctouch2.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2.dtsi"
+#include "px30-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core C.TOUCH 2.0";
+ compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
+"rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
diff --git a/arch/arm/mach-rockchip/px30/Kconfig
b/arch/arm/mach-rockchip/px30/Kconfig
index 5d014f6561..16090f5b08 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -20,6 +20,13 @@ config TARGET_PX30_CORE
* PX30.Core needs to mount on top of EDIMM2.2 for creating complete
PX30.Core EDIMM2.2 Starter Kit.
+ PX30.Core CTOUCH2:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * CTOUCH2.0 is a general purpose Carrier board with capacitive
+ touch interface support.
+ * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
+ PX30.Core C.TOUCH Carrier board.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS
index f98a84450a..b87ca22207 100644
--- a/board/engicam/px30_core/MAINTAINERS
+++ b/board/engicam/px30_core/MAINTAINERS
@@ -1,3 +1,9 @@
+PX30-Core-CTOUCH2.0
+M: Jagan Teki
+M: Suniel Mahesh
+S: Maintained
+F: configs/px30-core-ctouch2-px30_defconfig
+
PX30-Core-EDIMM2.2
M:Jagan Teki
M:Suniel Mahesh
diff --git a/configs/px30-core-ctouch2-px30_defconfig
b/configs/px30-core-ctouch2-px30_defconfig
new file mode 100644
index 00..d64f05d8c0
--- /dev/null
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_TEXT_BASE=0x
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_PX30_CORE=y
+CONFIG_DEBUG_UART_CHANNEL=1
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_DEBUG_UART_BASE=0xFF16
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+#
Re: [PATCH v4 5/8] rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit
On 2020/10/28 下午9:33, Jagan Teki wrote:
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.
PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Suniel Mahesh
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v4:
- drop ram change
- on top of
https://patchwork.ozlabs.org/project/uboot/patch/20201001184003.3704604-1-he...@sntech.de/
arch/arm/dts/Makefile | 1 +
arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 +
arch/arm/mach-rockchip/px30/Kconfig | 10 ++
board/engicam/px30_core/Kconfig | 16
board/engicam/px30_core/MAINTAINERS | 7 ++
board/engicam/px30_core/Makefile | 7 ++
board/engicam/px30_core/px30_core.c | 4 +
configs/px30-core-edimm2.2-px30_defconfig | 108 ++
include/configs/px30_core.h | 15 +++
9 files changed, 189 insertions(+)
create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts
create mode 100644 board/engicam/px30_core/Kconfig
create mode 100644 board/engicam/px30_core/MAINTAINERS
create mode 100644 board/engicam/px30_core/Makefile
create mode 100644 board/engicam/px30_core/px30_core.c
create mode 100644 configs/px30-core-edimm2.2-px30_defconfig
create mode 100644 include/configs/px30_core.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b195723f16..b87f4334a5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
+ px30-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts
b/arch/arm/dts/px30-px30-core-edimm2.2.dts
new file mode 100644
index 00..c36280ce7f
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core-edimm2.2.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-edimm2.2.dtsi"
+#include "px30-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
+ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
+"rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
diff --git a/arch/arm/mach-rockchip/px30/Kconfig
b/arch/arm/mach-rockchip/px30/Kconfig
index 6cd65dfa97..5d014f6561 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -11,6 +11,15 @@ config TARGET_EVB_PX30
config TARGET_ODROID_GO2
bool "ODROID_GO2"
+config TARGET_PX30_CORE
+ bool "Engicam PX30.Core"
+ help
+ PX30.Core EDIMM2.2:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam.
+ * PX30.Core needs to mount on top of EDIMM2.2 for creating complete
+ PX30.Core EDIMM2.2 Starter Kit.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
@@ -44,6 +53,7 @@ config DEBUG_UART_CHANNEL
For using the UART for early debugging the route to use needs
to be declared (0 or 1).
+source "board/engicam/px30_core/Kconfig"
source "board/hardkernel/odroid_go2/Kconfig"
source "board/rockchip/evb_px30/Kconfig"
diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30_core/Kconfig
new file mode 100644
index 00..a03be78369
--- /dev/null
+++ b/board/engicam/px30_core/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_PX30_CORE
+
+config SYS_BOARD
+ default "px30_core"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "px30_core"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select RAM_PX30_DDR4
+
+endif
diff --git a/board/engicam/px30_core/MAINTAINERS
b/board/engicam/px30_core/MAINTAINERS
new file mode 100644
index 00..f98a84450a
--- /dev/null
+++ b/board/engicam/px30_core/MAINTAINERS
@@ -0,0 +1,7 @@
+PX30-Core-EDIMM2.2
+M: Jagan Teki
+M: Suniel Mahesh
+S: Maintained
+F: board/engicam/px30_core
+F: include/configs/px30_core.h
+F: configs/px30-core-edimm2.2-px30_defconfig
diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30_core/Makefile
new file mode 100644
index 00..321fdb0173
--- /dev/null
+++ b/board/engicam/px30_core/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2020 Amarula Solutions(India)
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += px30_core.o
diff --git a/board/engicam/px30_core/px30_core.c
Re: [PATCH v4 4/8] board: engicam: Attach i.MX6 common code
On 2020/10/28 下午9:33, Jagan Teki wrote: The existing common code for Engicam boards uses i.MX6, so attach that into i.MX6 Engicam boards so-that adding new SoC variants of Engicam boards become meaningful. Add support for it. Cc: Stefano Babic Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- Changes for v4: - none board/engicam/common/Kconfig | 8 board/engicam/common/Makefile | 7 +-- board/engicam/imx6q/Kconfig | 2 ++ board/engicam/imx6ul/Kconfig | 2 ++ 4 files changed, 17 insertions(+), 2 deletions(-) create mode 100644 board/engicam/common/Kconfig diff --git a/board/engicam/common/Kconfig b/board/engicam/common/Kconfig new file mode 100644 index 00..38328fd5ea --- /dev/null +++ b/board/engicam/common/Kconfig @@ -0,0 +1,8 @@ +config IMX6_ENGICAM_COMMON + bool "Engicam i.MX6 Common code" + depends on SPL && MX6 + default y if TARGET_MX6Q_ENGICAM || TARGET_MX6UL_ENGICAM + help + Common SPL and U-Boot proper code for Engicam i.MX6 targets. + + Enable it in board Kconfig if it uses i.MX6 variant Engicam boards. diff --git a/board/engicam/common/Makefile b/board/engicam/common/Makefile index b392bf6cb1..15f0eaa1ec 100644 --- a/board/engicam/common/Makefile +++ b/board/engicam/common/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2016 Amarula Solutions B.V. -obj-y := board.o -obj-$(CONFIG_SPL_BUILD) += spl.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX6_ENGICAM_COMMON) += spl.o +else +obj-$(CONFIG_IMX6_ENGICAM_COMMON) += board.o +endif diff --git a/board/engicam/imx6q/Kconfig b/board/engicam/imx6q/Kconfig index 48eb60c09a..fab8da0e73 100644 --- a/board/engicam/imx6q/Kconfig +++ b/board/engicam/imx6q/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6-engicam" +source "board/engicam/common/Kconfig" + endif diff --git a/board/engicam/imx6ul/Kconfig b/board/engicam/imx6ul/Kconfig index e91dd15970..58f25d0623 100644 --- a/board/engicam/imx6ul/Kconfig +++ b/board/engicam/imx6ul/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6-engicam" +source "board/engicam/common/Kconfig" + endif
[PATCH] dm: core: Add of_match_node helper function
Add of_match_node() helper function to iterate over the device tree
and tell if a device_node has a matching of_match structure.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
drivers/core/device.c | 21 +
include/dm/device.h | 13 +
2 files changed, 34 insertions(+)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index e90d70101c..79076d9c78 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -997,6 +997,27 @@ bool of_machine_is_compatible(const char *compat)
return !fdt_node_check_compatible(fdt, 0, compat);
}
+static
+const struct udevice_id *__of_match_node(const struct udevice_id *matches,
+const ofnode node)
+{
+ if (!matches)
+ return NULL;
+
+ for (; matches && matches->compatible; matches++) {
+ if (ofnode_device_is_compatible(node, matches->compatible))
+ return matches;
+ }
+
+ return NULL;
+}
+
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+ const ofnode node)
+{
+ return __of_match_node(matches, node);
+}
+
int dev_disable_by_path(const char *path)
{
struct uclass *uc;
diff --git a/include/dm/device.h b/include/dm/device.h
index ac3b6c1b8a..0e9c37e64e 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -740,6 +740,19 @@ bool device_is_compatible(const struct udevice *dev, const
char *compat);
*/
bool of_machine_is_compatible(const char *compat);
+/**
+ * of_match_node() - Tell if a device_node has a matching of_match structure
+ *
+ *
+ * Low level utility function used by device matching.
+ *
+ * @matches: array of of device match structures to search in
+ * @node: the of device structure to match against
+ * @return matching structure on success, NULL if the match is not found
+ */
+const struct udevice_id *of_match_node(const struct udevice_id *matches,
+ const ofnode node);
+
/**
* dev_disable_by_path() - Disable a device given its device tree path
*
--
2.17.1
[PATCH] dm: soc: Add SoC id for attribute matching
Add SoC identification string for attribute matching.
Also changed the comments from "an SOC" to "a SoC".
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
drivers/soc/soc-uclass.c | 19 ++-
drivers/soc/soc_sandbox.c | 8
include/soc.h | 39 +--
test/dm/soc.c | 8
4 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index c32d647864..a3f8be841b 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -46,6 +46,16 @@ int soc_get_revision(struct udevice *dev, char *buf, int
size)
return ops->get_revision(dev, buf, size);
}
+int soc_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+ struct soc_ops *ops = soc_get_ops(dev);
+
+ if (!ops->get_soc_id)
+ return -ENOSYS;
+
+ return ops->get_soc_id(dev, buf, size);
+}
+
const struct soc_attr *
soc_device_match(const struct soc_attr *matches)
{
@@ -61,7 +71,7 @@ soc_device_match(const struct soc_attr *matches)
while (1) {
if (!(matches->machine || matches->family ||
- matches->revision))
+ matches->revision || matches->soc_id))
break;
match = true;
@@ -87,6 +97,13 @@ soc_device_match(const struct soc_attr *matches)
}
}
+ if (matches->soc_id) {
+ if (!soc_get_soc_id(soc, str, SOC_MAX_STR_SIZE)) {
+ if (strcmp(matches->soc_id, str))
+ match = false;
+ }
+ }
+
if (match)
return matches;
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 5c82ad84fc..1a81d3562a 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -31,10 +31,18 @@ int soc_sandbox_get_revision(struct udevice *dev, char
*buf, int size)
return 0;
}
+int soc_sandbox_get_soc_id(struct udevice *dev, char *buf, int size)
+{
+ snprintf(buf, size, "r8a774a1");
+
+ return 0;
+}
+
static const struct soc_ops soc_sandbox_ops = {
.get_family = soc_sandbox_get_family,
.get_revision = soc_sandbox_get_revision,
.get_machine = soc_sandbox_get_machine,
+ .get_soc_id = soc_sandbox_get_soc_id,
};
int soc_sandbox_probe(struct udevice *dev)
diff --git a/include/soc.h b/include/soc.h
index a55eb1b572..ae7b36846f 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -20,18 +20,20 @@
*variants. Example: am33
* @machine - Name of a specific SoC. Example: am3352
* @revision - Name of a specific SoC revision. Example: SR1.1
+ * @soc_id - SoC identification String. Example: r8a774a1
* @data - A pointer to user data for the SoC variant
*/
struct soc_attr {
const char *family;
const char *machine;
const char *revision;
+ const char *soc_id;
const void *data;
};
struct soc_ops {
/**
-* get_machine() - Get machine name of an SOC
+* get_machine() - Get machine name of a SoC
*
* @dev:Device to check (UCLASS_SOC)
* @buf:Buffer to place string
@@ -41,7 +43,7 @@ struct soc_ops {
int (*get_machine)(struct udevice *dev, char *buf, int size);
/**
-* get_revision() - Get revision name of a SOC
+* get_revision() - Get revision name of a SoC
*
* @dev:Device to check (UCLASS_SOC)
* @buf:Buffer to place string
@@ -51,7 +53,7 @@ struct soc_ops {
int (*get_revision)(struct udevice *dev, char *buf, int size);
/**
-* get_family() - Get family name of an SOC
+* get_family() - Get family name of a SoC
*
* @dev:Device to check (UCLASS_SOC)
* @buf:Buffer to place string
@@ -59,6 +61,16 @@ struct soc_ops {
* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
*/
int (*get_family)(struct udevice *dev, char *buf, int size);
+
+ /**
+* get_soc_id() - Get SoC identification name of a SoC
+*
+* @dev:Device to check (UCLASS_SOC)
+* @buf:Buffer to place string
+* @size: Size of string space
+* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+*/
+ int (*get_soc_id)(struct udevice *dev, char *buf, int size);
};
#define soc_get_ops(dev)((struct soc_ops *)(dev)->driver->ops)
@@ -76,7 +88,7 @@ struct soc_ops {
int soc_get(struct udevice **devp);
/**
- * soc_get_machine() - Get machine name of an SOC
+ * soc_get_machine() - Get machine name of a SoC
* @dev: Device to check (UCLASS_SOC)
* @buf: Buffer to place string
* @size: Size of string
Re: [PATCH] rockchip: mkimage: Remove host endianness dependency
On 2020/10/25 上午12:43, Samuel Holland wrote:
The Rockchip boot ROM expects little-endian values in the image header.
When running mkimage on a big-endian machine, these values need to be
byteswapped before writing or verifying the header.
This change fixes cross-compiling U-Boot SPL for the RK3399 SoC from a
big-endian ppc64 host machine.
Signed-off-by: Samuel Holland
Reviewed-by: Kever Yang
Thanks,
- Kever
---
tools/rkcommon.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 61c392e27d5..d55cd2c2d5a 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -221,12 +221,13 @@ bool rkcommon_need_rc4_spl(struct image_tool_params
*params)
static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
{
struct header0_info *hdr = buf;
+ uint32_t init_boot_size;
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
- hdr->signature = RK_SIGNATURE;
- hdr->disable_rc4 = !rkcommon_need_rc4_spl(params);
- hdr->init_offset = RK_INIT_OFFSET;
- hdr->init_size = spl_params.init_size / RK_BLK_SIZE;
+ hdr->signature = cpu_to_le32(RK_SIGNATURE);
+ hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params));
+ hdr->init_offset = cpu_to_le16(RK_INIT_OFFSET);
+ hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE);
/*
* init_boot_size needs to be set, as it is read by the BootROM
@@ -237,11 +238,10 @@ static void rkcommon_set_header0(void *buf, struct
image_tool_params *params)
* for a more detailed explanation by Andy Yan
*/
if (spl_params.boot_file)
- hdr->init_boot_size =
- hdr->init_size + spl_params.boot_size / RK_BLK_SIZE;
+ init_boot_size = spl_params.init_size + spl_params.boot_size;
else
- hdr->init_boot_size =
- hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE;
+ init_boot_size = spl_params.init_size + RK_MAX_BOOT_SIZE;
+ hdr->init_boot_size = cpu_to_le16(init_boot_size / RK_BLK_SIZE);
rc4_encode(buf, RK_BLK_SIZE, rc4_key);
}
@@ -294,14 +294,14 @@ static int rkcommon_parse_header(const void *buf, struct
header0_info *header0,
memcpy((void *)header0, buf, sizeof(struct header0_info));
rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key);
- if (header0->signature != RK_SIGNATURE)
+ if (le32_to_cpu(header0->signature) != RK_SIGNATURE)
return -EPROTO;
/* We don't support RC4 encoded image payloads here, yet... */
- if (header0->disable_rc4 == 0)
+ if (le32_to_cpu(header0->disable_rc4) == 0)
return -ENOSYS;
- hdr1_offset = header0->init_offset * RK_BLK_SIZE;
+ hdr1_offset = le16_to_cpu(header0->init_offset) * RK_BLK_SIZE;
hdr1_sdmmc = (struct header1_info *)(buf + hdr1_offset);
hdr1_spi = (struct header1_info *)(buf +
rkcommon_offset_to_spi(hdr1_offset));
@@ -359,7 +359,7 @@ void rkcommon_print_header(const void *buf)
struct header0_info header0;
struct spl_info *spl_info;
uint8_t image_type;
- int ret, boot_size;
+ int ret, boot_size, init_size;
ret = rkcommon_parse_header(buf, , _info);
@@ -377,9 +377,10 @@ void rkcommon_print_header(const void *buf)
printf("Image Type: Rockchip %s (%s) boot image\n",
spl_info->spl_hdr,
(image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI");
- printf("Init Data Size: %d bytes\n", header0.init_size * RK_BLK_SIZE);
+ init_size = le16_to_cpu(header0.init_size) * RK_BLK_SIZE;
+ printf("Init Data Size: %d bytes\n", init_size);
- boot_size = (header0.init_boot_size - header0.init_size) * RK_BLK_SIZE;
+ boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE -
init_size;
if (boot_size != RK_MAX_BOOT_SIZE)
printf("Boot Data Size: %d bytes\n", boot_size);
}
Re: [PATCH v1 5/7] apalis-imx8: add implementation for board_mem_get_layout
On Thu, Oct 22, 2020 at 11:22 AM Igor Opaniuk wrote:
>
> From: Igor Opaniuk
>
> Add implementation of board_mem_get_layout for overriding the memory
> layout.
>
> Signed-off-by: Igor Opaniuk
Acked-by: Oleksandr Suvorov
> ---
>
> board/toradex/apalis-imx8/apalis-imx8.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/board/toradex/apalis-imx8/apalis-imx8.c
> b/board/toradex/apalis-imx8/apalis-imx8.c
> index 9263b0f51f..2ed66261d2 100644
> --- a/board/toradex/apalis-imx8/apalis-imx8.c
> +++ b/board/toradex/apalis-imx8/apalis-imx8.c
> @@ -37,6 +37,29 @@ static void setup_iomux_uart(void)
> imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> }
>
> +void board_mem_get_layout(u64 *phys_sdram_1_start,
> + u64 *phys_sdram_1_size,
> + u64 *phys_sdram_2_start,
> + u64 *phys_sdram_2_size)
> +{
> + u32 is_quadplus = 0, val = 0;
> + sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, );
> +
> + if (scierr == SC_ERR_NONE) {
> + /* QP has one A72 core disabled */
> + is_quadplus = ((val >> 4) & 0x3) != 0x0;
> + }
> +
> + *phys_sdram_1_start = PHYS_SDRAM_1;
> + *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
> + *phys_sdram_2_start = PHYS_SDRAM_2;
> + if (is_quadplus)
> + /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */
> + *phys_sdram_2_size = 0x0UL;
> + else
> + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
> +}
> +
> int board_early_init_f(void)
> {
> sc_pm_clock_rate_t rate = SC_80MHZ;
> --
> 2.17.1
>
--
Best regards
Oleksandr Suvorov
Toradex AG
Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00
Re: [PATCH v4 8/8] doc: rockchip: Document Rockchip miniloader flashing
On 2020/10/28 下午9:33, Jagan Teki wrote:
This would be useful and recommended boot flow for new boards
which has doesn't have the DDR support yet in mainline.
Sometimes it is very useful for debugging mainline DDR support.
Documen it for px30 boot flow.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v4:
- none
doc/board/rockchip/rockchip.rst | 40 -
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 8c92de0c92..955e6858f2 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -123,6 +123,9 @@ To build rk3399 boards::
Flashing
+1. Package the image with U-Boot TPL/SPL
+-
+
SD Card
^^^
@@ -187,6 +190,39 @@ Copy SPI boot images into SD card and boot from SD::
sf erase 0x6 +$filesize
sf write $kernel_addr_r 0x6 ${filesize}
+2. Package the image with Rockchip miniloader
+-
+
+Image package with Rockchip miniloader requires robin [1].
+
+Create idbloader.img
+
+.. code-block:: none
+
+ cd u-boot
+ ./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin
idbloader.img
+ cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img
+ sudo dd if=idbloader.img of=/dev/sda seek=64
+
+Create trust.img
+
+.. code-block:: none
+
+ cd rkbin
+ ./tools/trust_merger RKTRUST/PX30TRUST.ini
+ sudo dd if=trust.img of=/dev/sda seek=24576
+
+Create uboot.img
+
+.. code-block:: none
+
+ rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x20
+ sudo dd if=uboot.img of=/dev/sda seek=16384
+
+Note:
+1. 0x20 is load address and it's an optional in some platforms.
+2. rkbin binaries are kept on updating, so would recommend to use the latest
versions.
+
TODO
@@ -195,5 +231,7 @@ TODO
- Document SPI flash boot
- Add missing SoC's with it boards list
+[1] https://github.com/rockchip-linux/rkbin
+
.. Jagan Teki
-.. Tuesday 02 June 2020 12:18:57 AM IST
+.. Wednesday 28 October 2020 06:47:26 PM IST
Re: [PATCH 0/3] mmc support for QEMU
On Fri, Oct 30, 2020 at 6:56 PM Harm Berntsen wrote: > > Hi, > > This patch series allows you to use a mmc drive from within QEMU: > > 1. make qemu_arm_defconfig > 2. Enable the CONFIG_DM_MMC, CONFIG_MMC_PCI, CONFIG_MMC_SDHCI options > 3. Run quemu as follows: > >qemu-system-arm >-machine virt,highmem=off \ >-device sdhci-pci \ >-device sd-card,drive=mydrive \ >-drive id=mydrive,if=none,format=raw,file=mmcblk0.bin \ >-bios u-boot.bin I don't see changes made to qemu_arm_defconfig. Is that a future patch? > > The MMC image can now be used to boot :) > Regards, Bin
Re: [PATCH] configs: meson64_android: don't show logo on ROM USB boot
On 30/10/2020 16:03, Mattijs Korpershoek wrote:
> From: Guillaume La Roque
>
> When booting from rom usb, skip the boot logo logic as it's possible
> that the partition containing the logo does not exist yet.
>
> Signed-off-by: Neil Armstrong
> Signed-off-by: Guillaume La Roque
> Signed-off-by: Mattijs Korpershoek
> ---
> include/configs/meson64_android.h | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/include/configs/meson64_android.h
> b/include/configs/meson64_android.h
> index 8fff915b50a4..c47d51c85368 100644
> --- a/include/configs/meson64_android.h
> +++ b/include/configs/meson64_android.h
> @@ -98,11 +98,14 @@
> func(SYSTEM, system, na) \
>
> #define PREBOOT_LOAD_LOGO \
> - "mmc dev ${mmcdev};" \
> - "part start mmc ${mmcdev} ${logopart} boot_start;" \
> - "part size mmc ${mmcdev} ${logopart} boot_size;" \
> - "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \
> + "if test \"${boot_source}\" != \"usb\" && " \
> + "gpt verify mmc ${mmcdev} ${partitions}; then; " \
> + "mmc dev ${mmcdev};" \
> + "part start mmc ${mmcdev} ${logopart} boot_start;" \
> + "part size mmc ${mmcdev} ${logopart} boot_size;" \
> + "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \
> "bmp display ${loadaddr} m m;" \
> + "fi;" \
> "fi;"
>
> #define CONFIG_EXTRA_ENV_SETTINGS \
>
Applied to u-boot-amlogic
Re: [PATCH] rockchip: Rock960: fix up USB support
Hi Peter, Could you add you signature for this patch? Thanks, - Kever On 2020/9/29 下午9:06, Peter Robinson wrote: Fix up USB config options so keyboards and other USB devices work. --- configs/rock960-rk3399_defconfig | 9 ++--- include/configs/rock960_rk3399.h | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 1d997847c2..a5a50785c5 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -3,12 +3,12 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x0020 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -41,6 +41,8 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_NVME=y CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -54,10 +56,11 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_DM_KEYBOARD=y CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index c6f9122154..2edad71028 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -15,4 +15,6 @@ #define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif
Re: [PATCH] video: rockchip: Add missing dpcd_write() call to link_train_ce()
Hi,
On 2020/10/16 上午2:29, Tom Rini wrote:
On Wed, Oct 14, 2020 at 11:39:40PM +0300, Alper Nebi Yasak wrote:
On 14/10/2020 22:31, Tom Rini wrote:
On Wed, Oct 14, 2020 at 09:58:28PM +0300, Alper Nebi Yasak wrote:
On 14/10/2020 18:24, Tom Rini wrote:
Ugh. In so far as anything can be re-licensed, who did it all
originally? I suspect coreboot isn't interested in 2.0+ but we can do
2.0-only.
For this patch, coreboot commit b9a7877568cf ("rockchip/*: refactor edp
driver") introduces the related change to src/soc/rockchip/common/edp.c
renamed from .../rk3288/edp.c, which was introduced at coreboot commit
40f558e8f4f7 ("rockchip: support display").
Right, sorry. I mean, on the U-Boot side, where did things come from?
I wonder how we got a different license text, and perhaps if we
shouldn't just re-port the coreboot code over as a clean/clear way to
re-license it to GPL-2.0-only.
I'm not sure re-porting is a great idea from the technical perspective.
I've been reading both drivers to compare them, there are also things in
U-Boot that're missing from coreboot. Things like DM integration are
also not there as they're U-Boot specific.
I checked some files with git log and checked the first commit that
showed up for each.
Simon Glass added:
- drivers/video/rockchip/rk_edp.c
- drivers/video/rockchip/rk_hdmi.c
- drivers/video/rockchip/rk_vop.c
- arch/arm/include/asm/arch-rockchip/vop_rk3288.h
- arch/arm/include/asm/arch-rockchip/edp_rk3288.h
as Copyright (c) 2015 Google, Inc
Copyright 2014 Rockchip Inc.
Philipp Tomsich added:
- drivers/video/rockchip/rk3288_hdmi.c
- drivers/video/rockchip/rk3399_hdmi.c
- drivers/video/rockchip/rk_hdmi.h
- drivers/video/rockchip/rk_vop.h
as Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
- drivers/video/rockchip/rk3288_vop.c
- drivers/video/rockchip/rk3399_vop.c
as Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
Copyright (c) 2015 Google, Inc
Copyright 2014 Rockchip Inc.
Eric Gao added:
- drivers/video/rockchip/rk3288_mipi.c
- drivers/video/rockchip/rk3399_mipi.c
- drivers/video/rockchip/rk_mipi.c
- drivers/video/rockchip/rk_mipi.h
- arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
as Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
Jacob Chen added:
- drivers/video/rockchip/rk_lvds.c
- arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
as Copyright 2016 Rockchip Inc.
Probably then the best "I am not a lawyer" answer is to have Philipp
Tomsich, Eric Gao and Jacob Chen all acked-by a patch to mark our driver
as GPL-2.0-only so that it's very clear that we can take improvements
from other GPL-2.0-only sources.
It's OK for Rockchip to make this change update license to GPL-2.0+.
Thanks,
- Kever
Re: [PATCH 1/3] rockchip: efuse: add support for RK3288 non-secure efuse
Hi Jonas,
Could you help to format the coding style as required so that we
can merge this patch to the mainline?
Thanks,
- Kever
On 2020/10/14 上午4:21, Jonas Karlman wrote:
From: Francis Fan
Extend rockchip efuse driver with support for RK3288 non-secure efuse.
Signed-off-by: Francis Fan
Signed-off-by: Cody Xie
Signed-off-by: Jonas Karlman
---
drivers/misc/rockchip-efuse.c | 91 +--
1 file changed, 87 insertions(+), 4 deletions(-)
diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
index 46ce6305fe..20423544d9 100644
--- a/drivers/misc/rockchip-efuse.c
+++ b/drivers/misc/rockchip-efuse.c
@@ -27,6 +27,17 @@
#define RK3399_STROBE BIT(1)
#define RK3399_CSB BIT(0)
+#define RK3288_A_SHIFT 6
+#define RK3288_A_MASK 0x3ff
+#define RK3288_NFUSES 32
+#define RK3288_BYTES_PER_FUSE 1
+#define RK3288_PGENBBIT(3)
+#define RK3288_LOAD BIT(2)
+#define RK3288_STROBE BIT(1)
+#define RK3288_CSB BIT(0)
+
+typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int
size);
+
struct rockchip_efuse_regs {
u32 ctrl; /* 0x00 efuse control register */
u32 dout; /* 0x04 efuse data out register */
@@ -53,7 +64,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
*/
struct udevice *dev;
- u8 fuses[128];
+ u8 fuses[128] = {0};
int ret;
/* retrieve the device */
@@ -77,7 +88,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
}
U_BOOT_CMD(
- rk3399_dump_efuses, 1, 1, dump_efuses,
+ rockchip_dump_efuses, 1, 1, dump_efuses,
"Dump the content of the efuses",
""
);
@@ -127,10 +138,59 @@ static int rockchip_rk3399_efuse_read(struct udevice
*dev, int offset,
return 0;
}
+static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
+ struct rockchip_efuse_regs *efuse =
+ (struct rockchip_efuse_regs *)plat->base;
+ u8 *buffer = buf;
+ int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE;
+
+ if (size > (max_size - offset))
+ size = max_size - offset;
+
+ /* Switch to read mode */
+ writel(RK3288_LOAD | RK3288_PGENB, >ctrl);
+ udelay(1);
+
+ while (size--) {
+ writel(readl(>ctrl) &
+ (~(RK3288_A_MASK << RK3288_A_SHIFT)),
+ >ctrl);
+ /* set addr */
+ writel(readl(>ctrl) |
+ ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
+ >ctrl);
+ udelay(1);
+ /* strobe low to high */
+ writel(readl(>ctrl) |
+ RK3288_STROBE, >ctrl);
+ ndelay(60);
+ /* read data */
+ *buffer++ = readl(>dout);
+ /* reset strobe to low */
+ writel(readl(>ctrl) &
+ (~RK3288_STROBE), >ctrl);
+ udelay(1);
+ }
+
+ /* Switch to standby mode */
+ writel(RK3288_PGENB | RK3288_CSB, >ctrl);
+
+ return 0;
+}
+
static int rockchip_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
- return rockchip_rk3399_efuse_read(dev, offset, buf, size);
+ EFUSE_READ efuse_read = NULL;
+
+ efuse_read = (EFUSE_READ)dev_get_driver_data(dev);
+ if (!efuse_read)
+ return -ENOSYS;
+
+ return (*efuse_read)(dev, offset, buf, size);
}
static const struct misc_ops rockchip_efuse_ops = {
@@ -146,7 +206,30 @@ static int rockchip_efuse_ofdata_to_platdata(struct
udevice *dev)
}
static const struct udevice_id rockchip_efuse_ids[] = {
- { .compatible = "rockchip,rk3399-efuse" },
+ {
+ .compatible = "rockchip,rk3066a-efuse",
+ .data = (ulong)_rk3288_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3188-efuse",
+ .data = (ulong)_rk3288_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3228-efuse",
+ .data = (ulong)_rk3288_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3288-efuse",
+ .data = (ulong)_rk3288_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3368-efuse",
+ .data = (ulong)_rk3288_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3399-efuse",
+ .data = (ulong)_rk3399_efuse_read,
+ },
{}
};
Re: U-Boot i2c bus num 1 is broken on Nokia N900
Hi, On 29.10.20 г. 11:32 ч., Heiko Schocher wrote: Hello Ivaylo, Am 29.10.2020 um 08:51 schrieb Ivaylo Dimitrov: Hi, On 28.10.20 г. 7:42 ч., Heiko Schocher wrote: Hello Pali, sorry for late response ... Am 26.10.2020 um 22:48 schrieb Pali Rohár: On Monday 27 April 2020 09:03:13 Heiko Schocher wrote: Hello Pali, Am 26.04.2020 um 01:54 schrieb Pali Rohár: Adding Hannes and Heiko to the loop, please look at this problem. On Saturday 25 April 2020 14:11:32 Pali Rohár wrote: On Saturday 25 April 2020 07:00:58 Adam Ford wrote: On Sat, Apr 25, 2020 at 6:50 AM Pali Rohár wrote: On Saturday 25 April 2020 06:36:58 Adam Ford wrote: On Sat, Apr 25, 2020 at 5:42 AM Pali Rohár wrote: On Thursday 02 April 2020 20:42:31 Pali Rohár wrote: On Wednesday 01 April 2020 12:32:29 Merlijn Wajer wrote: Hi, On 01/04/2020 00:42, Pali Rohár wrote: On Wednesday 01 April 2020 00:35:07 Pali Rohár wrote: This patch series contain fixes for Nokia RX-51 board (aka N900). After these changes it is possible to run U-Boot in qemu emulator again. And U-Boot can boot kernel image from RAM, eMMC or OneNAND memory without problem. But on real Nokia N900 device is U-Boot crashing in reboot loop. I do not have serial console for Nokia N900 to debug this issue, but seems that it is related to OMAP I2C and OMAP HS MMC code. Problem is that there is no crash and even no error in qemu emulator so I cannot debug this issue. First problem is around /* reset lp5523 led */ code in rx51.c. On real N900 device it generates repeating messages: Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= When I commented that few lines all these messages disappeared. So problem is with OMAP I2C. ... I remember that somebody had serial jig for Nokia N900, could somebody look at this reboot loop problem? And any idea how should be OMAP I2C configured in U-Boot to correctly work? Maybe I will try to find some time to git bisect which change broke U-Boot on real N900 hardware. Took latest u-boot master, applied patches and this is the result on serial (first part is NOLO booting, I think that can be ignored) [1]. ... U-Boot 2020.04-rc4-00033-g7dbafe0634-dirty (Apr 01 2020 - 12:15:47 +0200) OMAP3530-HS ES3.1, CPU-OPP2, L3-165MHz, Max CPU Clock 600 MHz Nokia RX-51 + LPDDR/OneNAND I2C: ready DRAM: 256 MiB NAND: 0 Bytes Looks like that something with NAND is broken. The board code in U-Boot is in a very old state... :-( :-( MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 In: vga Out: vga Err: vga Timed out in wait_for_event: status=0100 Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status= Check if pads/pull-ups of bus are properly configured i2c_read (addr phase): pads on bus probably not configured (status=0x10) How is that trace even possible? I built and tested u-boot here on my devices and I see the same message, but unless I am becoming blind, i2c_read() is never called from within i2c_write(). This is really suspicious. i2c_write: timed out writig last byte! These i2c errors are caused by /* reset lp5523 led */ i2c_set_bus_num(1); deprecated ... the board code needs cleanup ... Yes, my first thought too! This board needs a complete cleanup. I converted code to CONFIG_DM_I2C and nothing was changed, issue is still there... Ok. state = 0xff; i2c_write(0x32, 0x3d, 1, , 1); i2c_set_bus_num(0); Is there anything which needs to be done to initialize
[PATCH 0/3] mmc support for QEMU
Hi, This patch series allows you to use a mmc drive from within QEMU: 1. make qemu_arm_defconfig 2. Enable the CONFIG_DM_MMC, CONFIG_MMC_PCI, CONFIG_MMC_SDHCI options 3. Run quemu as follows: qemu-system-arm -machine virt,highmem=off \ -device sdhci-pci \ -device sd-card,drive=mydrive \ -drive id=mydrive,if=none,format=raw,file=mmcblk0.bin \ -bios u-boot.bin The MMC image can now be used to boot :) Regards, Harm Harm Berntsen (3): gpio: do not include on ARCH_QEMU acpi: Only include asm table when available mmc: Only retrieve cd pin when GPIO is enabled arch/arm/include/asm/gpio.h | 3 ++- drivers/mmc/pci_mmc.c | 2 ++ include/acpi/acpi_table.h | 2 ++ 3 files changed, 6 insertions(+), 1 deletion(-)
[PATCH 2/3] acpi: Only include asm header when available
The only platforms with an asm/acpi_table.h file are X86 and Sandbox. Some drivers, i.e. pci_mmc.c, can generate ACPI info and therefore include asm/acpi_table.h by proxy. This commit ensures that the platforms wishing to use such driver and do not have ACPI support do not fail on this include. The if defined structure is also used in other places to conditionally include asm headers, i.e. arch/arm/include/asm/gpio.h Signed-off-by: Harm Berntsen CC: Simon Glass --- include/acpi/acpi_table.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index abbca6530d..8d9d0f8d19 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -690,6 +690,8 @@ void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start); #endif /* !__ACPI__*/ +#if defined(CONFIG_X86) || defined(CONFIG_SANDBOX) #include +#endif #endif /* __ACPI_TABLE_H__ */
[PATCH 1/3] gpio: do not include on ARCH_QEMU
As no gpio.h is defined for this architecture, to avoid compilation failure, do not include for QEMU. Signed-off-by: Harm Berntsen --- arch/arm/include/asm/gpio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 6ecb876eda..7609367884 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -3,7 +3,8 @@ !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \ - !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) + !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \ + !defined(CONFIG_ARCH_QEMU) #include #endif #include
[PATCH 3/3] mmc: Only retrieve cd pin when GPIO is enabled
The driver only needs to retrieve the pin for the ACPI info. The driver
itself works without depending on GPIO.
Signed-off-by: Harm Berntsen
CC: Simon Glass
---
drivers/mmc/pci_mmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 0c45e1b893..dba6324247 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -52,9 +52,11 @@ static int pci_mmc_probe(struct udevice *dev)
static int pci_mmc_ofdata_to_platdata(struct udevice *dev)
{
+#if defined(CONFIG_DM_GPIO)
struct pci_mmc_priv *priv = dev_get_priv(dev);
gpio_request_by_name(dev, "cd-gpios", 0, >cd_gpio, GPIOD_IS_IN);
+#endif
return 0;
}
Re: [PATCH] ram: rockchip: px30: add a config-based ddr selection
On 2020/10/2 上午2:40, Heiko Stuebner wrote:
From: Heiko Stuebner
The SRAM on the PX30 is not big enough to hold multiple DDR configs
so it needs to be selected during build.
So far simply the DDR3 config was always selected and getting DDR4
or LPDDR2/3 initialized would require a code modification.
So add Kconfig options similar to RK3399 to allow selecting the DDR4
and LPDDR2/3 options instead, while DDR3 stays the default as before.
Signed-off-by: Heiko Stuebner
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/ram/rockchip/Kconfig | 21 +
drivers/ram/rockchip/sdram_px30.c | 8
2 files changed, 29 insertions(+)
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index 8e97c2f49e..c459bbf5e2 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -22,6 +22,27 @@ config RAM_ROCKCHIP_DEBUG
This is an option for developers to understand the ram drivers
initialization, configurations and etc.
+config RAM_PX30_DDR4
+ bool "DDR3 support for Rockchip PX30"
+ depends on RAM_ROCKCHIP && ROCKCHIP_PX30
+ help
+ This enables DDR4 sdram support instead of the default DDR3 support
+ on Rockchip PC30 SoCs.
+
+config RAM_PX30_LPDDR2
+ bool "LPDDR2 support for Rockchip PX30"
+ depends on RAM_ROCKCHIP && ROCKCHIP_PX30
+ help
+ This enables LPDDR2 sdram support instead of the default DDR3 support
+ on Rockchip PC30 SoCs.
+
+config RAM_PX30_LPDDR3
+ bool "LPDDR3 support for Rockchip PX30"
+ depends on RAM_ROCKCHIP && ROCKCHIP_PX30
+ help
+ This enables LPDDR3 sdram support instead of the default DDR3 support
+ on Rockchip PC30 SoCs.
+
config RAM_RK3399_LPDDR4
bool "LPDDR4 support for Rockchip RK3399"
depends on RAM_ROCKCHIP && ROCKCHIP_RK3399
diff --git a/drivers/ram/rockchip/sdram_px30.c
b/drivers/ram/rockchip/sdram_px30.c
index fd5763d0a0..2f1f6e9c0c 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -125,7 +125,15 @@ u32 addrmap[][8] = {
struct dram_info dram_info;
struct px30_sdram_params sdram_configs[] = {
+#if defined(CONFIG_RAM_PX30_DDR4)
+#include "sdram-px30-ddr4-detect-333.inc"
+#elif defined(CONFIG_RAM_PX30_LPDDR2)
+#include "sdram-px30-lpddr2-detect-333.inc"
+#elif defined(CONFIG_RAM_PX30_LPDDR3)
+#include "sdram-px30-lpddr3-detect-333.inc"
+#else
#include "sdram-px30-ddr3-detect-333.inc"
+#endif
};
struct ddr_phy_skew skew = {
[PATCH] km/arm: coding style clean up
Address most of the checkpatch issues we found in km_arm and common km
code.
CC: Stefan Roese
CC: Valentin Longchamp
Signed-off-by: Holger Brunck
---
board/keymile/common/common.c | 44 ---
board/keymile/common/ivm.c | 84 ++---
board/keymile/km_arm/fpga_config.c | 16 +++---
board/keymile/km_arm/km_arm.c | 41 +++---
include/configs/km/keymile-common.h | 4 +-
include/configs/km/km_arm.h | 2 +-
6 files changed, 96 insertions(+), 95 deletions(-)
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 03c7ce9da7..df507e2790 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -56,7 +56,7 @@ int set_km_env(void)
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
- if (p != NULL)
+ if (p)
strict_strtoul(p, 16, );
pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
CONFIG_KM_PNVRAM) / 0x400;
@@ -165,7 +165,7 @@ static int do_setboardid(struct cmd_tbl *cmdtp, int flag,
int argc,
char *p;
p = get_local_var("IVM_BoardId");
- if (p == NULL) {
+ if (!p) {
printf("can't get the IVM_Boardid\n");
return 1;
}
@@ -174,7 +174,7 @@ static int do_setboardid(struct cmd_tbl *cmdtp, int flag,
int argc,
printf("set boardid=%s\n", buf);
p = get_local_var("IVM_HWKey");
- if (p == NULL) {
+ if (!p) {
printf("can't get the IVM_HWKey\n");
return 1;
}
@@ -186,8 +186,8 @@ static int do_setboardid(struct cmd_tbl *cmdtp, int flag,
int argc,
return 0;
}
-U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid", "read out bid and
"
-"hwkey from IVM and set in environment");
+U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid",
+ "read out bid and hwkey from IVM and set in environment");
/*
* command km_checkbidhwk
@@ -218,14 +218,14 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
* already stored in the local hush variables
*/
p = get_local_var("IVM_BoardId");
- if (p == NULL) {
+ if (!p) {
printf("can't get the IVM_Boardid\n");
return 1;
}
rc = strict_strtoul(p, 16, );
p = get_local_var("IVM_HWKey");
- if (p == NULL) {
+ if (!p) {
printf("can't get the IVM_HWKey\n");
return 1;
}
@@ -238,10 +238,10 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
/* now try to read values from environment if available */
p = env_get("boardid");
- if (p != NULL)
+ if (p)
rc = strict_strtoul(p, 16, );
p = env_get("hwkey");
- if (p != NULL)
+ if (p)
rc = strict_strtoul(p, 16, );
if (rc != 0) {
@@ -263,9 +263,8 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
if (verbose) {
printf("IVM_BoardId: %ld, IVM_HWKey=%ld\n",
- ivmbid, ivmhwkey);
- printf("boardIdHwKeyList: %s\n",
- bidhwklist);
+ ivmbid, ivmhwkey);
+ printf("boardIdHwKeyList: %s\n", bidhwklist);
}
while (!found) {
/* loop over each bid/hwkey pair in the list */
@@ -291,13 +290,13 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
while (*rest && !isxdigit(*rest))
rest++;
}
- if ((!bid) || (!hwkey)) {
+ if (!bid || !hwkey) {
/* end of list */
break;
}
if (verbose) {
printf("trying bid=0x%lX, hwkey=%ld\n",
- bid, hwkey);
+ bid, hwkey);
}
/*
* Compare the values of the found entry in the
@@ -305,7 +304,7 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int
flag, int argc,
* in the inventory eeprom. If they are equal
* set the values in environment variables.
*/
- if ((bid == ivmbid) && (hwkey == ivmhwkey)) {
+
[PATCH] log: typo logl_pref in documentation
The name of structure element logl_prev is not matched by the
documentation.
%s/logl_pref/logl_prev/
Signed-off-by: Heinrich Schuchardt
---
include/asm-generic/global_data.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index 0157af1aa4..0e8843b478 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -378,7 +378,7 @@ struct global_data {
*/
int logc_prev;
/**
-* @logl_pref: logging level of the previous message
+* @logl_prev: logging level of the previous message
*
* This value is used as logging level for continuation messages.
*/
--
2.28.0
Re: [PATCH 00/33] stm32: enable logging features
Hi Patrick, On Wed, 28 Oct 2020 at 05:52, Patrick DELAUNAY wrote: > > Hi Simon, > > > From: Simon Glass > > Sent: lundi 26 octobre 2020 20:23 > > > > Hi Patrick, > > > > On Thu, 15 Oct 2020 at 09:59, Patrick DELAUNAY > > wrote: > > > > > > Hi Simon, > > > > > > > From: Simon Glass > > > > Sent: jeudi 15 octobre 2020 17:06 > > > > > > > > Hi Patrick, > > > > > > > > On Wed, 14 Oct 2020 at 03:16, Patrick Delaunay > > > > > > > > wrote: > > > > > > > > > > > > > > > This patch-set migrates several stm32 drivers to API compatible > > > > > with logging features (use dev_...() or log_...() function) and > > > > > activate the logging features in STM32MP15 boards. > > > > > > > > > > The size of U-Boot increased by 19kB (933026 to 952830 on > > > > > STM32MP157C-EV1 board for basic defconfig) but the boot time don't > > > > > change > > > > drastically. > > > > > > > > > > > (...) > > > > > > For information even with all trace embbeded in U-Boot but not > > > > > activated, MAX_LOG_LEVEL=8 and LOG_DEFAULT_LEVEL=6 > > > > > > > > > > Size increase by 190KB (952830 to 1147918) but boot time is stable > > > > > (1,748s vs 1,696s). > > > > > > > > This seems pretty bad. Is this because of console output, or > > > > something else? I understand the size increase, but not the boot time > > increase. > > > > > > For this last point I just execute STM32MP157C-EV1 boot with a patch > > > in configs/stm32mp15_basic_defconfig > > > > > > +CONFIG_LOGLEVEL=8 > > > +CONFIG_LOG_MAX_LEVEL=8 > > > +CONFIG_LOG_DEFAULT_LEVEL=6 > > > +CONFIG_LOGF_FILE=y > > > +CONFIG_LOGF_LINE=y > > > +CONFIG_LOGF_FUNC=y > > > > > > And execute "bootstage report" after the second boot (the first boot > > > is pertubated by env save) > > > > > > I think the delta is linked to > > > 1/ size of U-Boot (SPL spent more time to load U-Boot) > > > end of SPL 987,579 => 996,117 > > > > OK. > > > > > > > > 2/ time to check for each debug trace: because I increase the log level > > >(gd->default_log_level = 6 < MAX_LOG_LEVEL=8) > > > > This might be the biggest part. If you look at _log() it always does the > > vsprintf() > > even if in fact log_dispatch() does not dispatch it to anything. > > Yes, log_dispatch / log_passes_filter are called after vsnprintf > > > I suspect that could be refactored to move the checking to a separate > > function, > > and then call it before doing the expensive vsprintf(). > > Or save va_list, fmt in log_rec and call vsnprintf allow when needed in > log_dispatch, just before emit Yes that sounds better to me. > > > > > > > 3/ treatment added in log_console_emit (some printf) and > > > log_dispatch (processing_msg / gd->loghead) > > > > Likely this is fast. > > > > > > > > 4/ lower cache performancy as trace code are pesent in memory even > > > they are not used > > > > > > Can I do some check/experimentation on my side ? > > > > Yes, if you can use the bootstage_start() and bootstage_accum() within the > > _log() > > function to measure the total time take in the run. > > Ok, I add it in my TODO list OK. We really should make logging add the least overhead possible. Regards, SImon
Re: [PATCH] Makefile: Correctly propagate failure when removing target
Hi Paul,
On Tue, 27 Oct 2020 at 20:25, Pali Rohár wrote:
>
> On Tuesday 27 October 2020 20:10:37 Simon Glass wrote:
> > Hi Paul,
> >
> > On Mon, 26 Oct 2020 at 07:11, Pali Rohár wrote:
> > >
> > > On more places is used pattern 'command > $@ || rm -f $@'. But it does not
> > > propagate failure from 'command' as 'rm -f' returns success.
> > >
> > > Fix it by calling 'false' to correctly propagate failure after 'rm -f'.
> > >
> > > Signed-off-by: Pali Rohár
> > > ---
> > > Makefile | 12 ++--
> > > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > Reviewed-by: Simon Glass
> >
> > But I'm not sure about the use of {}. I would normally use ()
>
> ( ... ) spawns new shell and run commands in that new shell
> { ... ; } groups command together and runs them in the current shell
>
> So { ... ; } should be more efficient as it spawns less processes. But
> result should be same, return value from 'false', which returns 1.
>
> I'm using { ... ; } when it is not needed to spawns new processes and
> running commands in current shell is fine. I think that writing ( ... )
> should be equivalent to sh -c '...' (with correctly exported variables).
OK thank you.
Regards,
Simon
Re: [PATCH 16/25] binman: Avoid reporting image-pos with compression
Hi Alper,
On Mon, 26 Oct 2020 at 17:20, Alper Nebi Yasak wrote:
>
> On 26/10/2020 22:22, Simon Glass wrote:
> > Hi Alper,
> >
> > On Mon, 19 Oct 2020 at 15:29, Alper Nebi Yasak
> > wrote:
> >>
> >> On 19/10/2020 05:41, Simon Glass wrote:
> >>> When a section is compressed, all entries within it are grouped together
> >>> into a compressed block of data. This obscures the start of each
> >>> individual child entry.
> >>>
> >>> Avoid reporting bogus 'image-pos' properties in this case, since it is
> >>> not possible to access the entry at the location provided. The entire
> >>> section must be decompressed first.
> >>>
> >>> CBFS does not support compressing whole sections, only individual files,
> >>> so needs no special handling here.
> >>>
> >>> Signed-off-by: Simon Glass
> >>> ---
> >>
> >> Maybe instead of this, 'image-pos' could be overloaded to a list of
> >> recursive relative positions within compressed archives? Something like:
> >>
> >> section {
> >> offset = <1000>;
> >> compress = "lz4";
> >> /* image-pos = <1000>; */
> >>
> >> blob {
> >> filename = "foo";
> >> offset = <100>;
> >> /* image-pos = <1000>, <100>; */
> >> };
> >> };
> >>
> >> cbfs {
> >> offset = <2000>;
> >> /* image-pos = <2000>; */
> >>
> >> blob {
> >> filename = "bar";
> >> cbfs-compress = "lz4";
> >> cbfs-offset = <200>;
> >> /* image-pos = <2200>, <0>; */
> >> };
> >>
> >> blob2 {
> >> filename = "baz";
> >> cbfs-offset = <800>;
> >> /* image-pos = <2800>; */
> >> };
> >> };
> >>
> >
> > What do these values actually mean though? What would we use them for?
>
> What I meant is using pairs of ,
> to avoid losing position information of
> compressed entries, but honestly I'm not sure if any of this will be
> necessary. I think the single use would be to avoid parsing uncompressed
> data containing multiple entries to identify what is where.
>
> To get to an entry in a compressed section we could get "size" bytes of
> data starting from "image-pos[0]", decompress that to somewhere, then
> get "uncomp-size" bytes of data starting from decompression address +
> "image-pos[1]". I think it can even be extended to multiple layers of
> compression (, , , ...).
>
> > Note that CBFS compresses its data on a per-entry basis so the
> > image-pos is actually supported.
>
> On the compressed cbfs example, I assume the data we currently get at
> image-pos = <2200> is compressed data and still needs to be decompressed
> for it to be useable (technically bogus?). If so, I'd go a level deeper
> by adding a <0> indicating the start of the uncompressed data is the
> actual position of the entry contents.
For the CBFS case there isn't anything needed I think.
We already have an offset field which tells you where something is in
the compressed data. For the case where a compressed section has just
other entries in it, the offset is enough.
For the case where the compressed section has other uncompressed
sections, we need to add together the offsets (uncompressed section +
its entry) to get to the compressed location. It certainly has some
benefits.
But I wonder if instead we should have a properly like comp-pos that
tells you the absolute offset within the compressed section? I'm not a
big fan of making image-pos a multi-cell value.
Regards,
Simon
Re: [PATCH 08/18] serial: add uart driver for MediaTek MT7620 SoC
Hi Weijie, On Thu, 29 Oct 2020 at 21:21, Weijie Gao wrote: > > On Thu, 2020-10-29 at 08:30 -0600, Simon Glass wrote: > > Hi Weijie, > > > > On Thu, 29 Oct 2020 at 03:47, Weijie Gao wrote: > > > > > > On Mon, 2020-10-26 at 22:51 -0600, Simon Glass wrote: > > > > Hi Weijie, > > > > > > > > On Fri, 16 Oct 2020 at 01:36, Weijie Gao > > > > wrote: > > > > > > > > > > This patch adds uart support for MediaTek MT7620 and earlier SoCs. > > > > > > > > > > The UART used by MT7620 is incompatible with the ns16550a driver. > > > > > All registers of this UART have different addresses. A special 16-bit > > > > > register for Divisor Latch is used to set the baudrate instead of the > > > > > original two 8-bit registers (DLL and DLM). > > > > > > > > > > The driver can be built without DM which is useful for tiny SPL. > > > > > > > > > > Signed-off-by: Weijie Gao > > > > > --- > > > > > drivers/serial/Kconfig | 20 ++ > > > > > drivers/serial/Makefile| 1 + > > > > > drivers/serial/serial.c| 2 + > > > > > drivers/serial/serial_mt7620.c | 350 > > > > > + > > > > > 4 files changed, 373 insertions(+) > > > > > create mode 100644 drivers/serial/serial_mt7620.c > > > > > > > > Why do you need to build without DM? We have of-platdata which > > > > provides for smaller images. What is the SRAM size available? > > > > > > > > > > Actually it's the total size (spl+u-boot-lzma.img) that matters. > > > mt7620_rfb_defconfig is configured to be compatible with the original > > > u-boot from MTK SDK, and the maximum size is 192KiB. > > > > What is lzma.img ? > > The u-boot.bin is compressed to reduce it's size (395KiB -> 150KiB), and > the SPL is responsible to decompress it. > > > > > > > > > Currently without SPL_DM, the final image u-boot-with-spl.bin is about > > > 170KiB, the u-boot-spl.bin is only 20KiB. > > > > That is definitely huge. > > Without the decompression code, the size of SPL will be reduced to 9KiB. OK...so is it possible to have SPL load U-Boot, instead of including it in SRAM? That is normally what is done. > > > > > > If SPL_DM is enabled, the total size is 189KiB, which is very close to > > > the limit 192KiB, and the size of spl is almost doubled, 39KiB. > > > (Without DM, only serial_mt7620 is needed. However with DM, both > > > serial_mt7620, clk-mt7620 and misc are needed) > > > > > > Considering that we may still add some feature to mt7620_rfb_defconfig > > > in the future, only 3KiB left is not enough. Building without DM is > > > apparently better. > > > > > > I believe using of-platdata can only reduce few KiBs of SPL, because the > > > DM itself is the largest overhead. > > > > That's not my experience. The core DM overhead is fairly small, > > perhaps 3-4KB. The device tree itself is typically at least another > > 3KB, depending on how many nodes you mark for inclusion in SPL. > > > > With of-platdata the overhead of DM is not that terrible. You can see > > some stats here: > > I have tried to optimize drivers and configs used in SPL, and managed to > reduce the size of SPL to 22KiB with of-platdata (without DM, the size > is 17KiB. So it's only 5KiB used by DM). > > I'll switch this driver to of-platdata in the next series. Gosh that was quick, nice work! > > > > > http://u-boot.10912.n7.nabble.com/RFC-PATCH-v2-0-3-RFC-tiny-dm-Proposal-for-using-driver-model-in-SPL-td418552.html Regards, Simon
Re: [PATCH v4 20/22] test: Add a test for log filter-*
On Tue, Oct 27, 2020 at 07:55:39PM -0400, Sean Anderson wrote: > This exercises a few success and failure modes of the log filter-* > commands. log filter-list is not tested because it's purely informational. > I don't think there's a good way to test it except by testing if the output > of the command exactly matches a sample run. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 17/22] lib: Add getopt
On Tue, Oct 27, 2020 at 07:55:36PM -0400, Sean Anderson wrote:
> Some commands can get very unweildy if they have too many positional
> arguments. Adding options makes them easier to read, remember, and
> understand.
>
> This implementation of getopt has been taken from barebox, which has had
> option support for quite a while. I have made a few modifications to their
> version, such as the removal of opterr in favor of a separate getopt_silent
> function. In addition, I have moved all global variables into struct
> getopt_context.
>
> The getopt from barebox also re-orders the arguments passed to it so that
> non-options are placed last. This allows users to specify options anywhere.
> For example, `ls -l foo/ -R` would be re-ordered to `ls -l -R foo/` as
> getopt parsed the options. However, this feature conflicts with the const
> argv in cmd_tbl->cmd. This was originally added in 54841ab50c ("Make sure
> that argv[] argument pointers are not modified."). The reason stated in
> that commit is that hush requires argv to stay unmodified. Has this
> situation changed? Barebox also uses hush, and does not have this problem.
> Perhaps we could use their fix?
>
> I have assigned maintenance of getopt to Simon Glass, as it is currently
> only used by the log command. I would also be fine maintaining it.
>
> Signed-off-by: Sean Anderson
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v4 14/22] cmd: log: Split off log level parsing
On Tue, Oct 27, 2020 at 07:55:33PM -0400, Sean Anderson wrote: > Move parsing of log level into its own function so it can be re-used. This > also adds support for using log level names instead of just the integer > equivalent. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 16/22] cmd: log: Make "log level" print all log levels
On Tue, Oct 27, 2020 at 07:55:35PM -0400, Sean Anderson wrote: > This makes the log level command print all valid log levels. The default > log level is annotated. This provides an easy way to see which log levels > are compiled-in. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 18/22] test: Add a test for getopt
On Tue, Oct 27, 2020 at 07:55:37PM -0400, Sean Anderson wrote: > A few of these tests were inspired by those in glibc. The syntax for > invoking test_getopt is a bit funky, but it's necessary so that the CPP can > parse the arguments correctly. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 21/22] doc: Add log kerneldocs to documentation
On Tue, Oct 27, 2020 at 07:55:40PM -0400, Sean Anderson wrote: > The functions in log.h are already mostly documented, so add them to the > generated documentation. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 22/22] doc: Update logging documentation
On Tue, Oct 27, 2020 at 07:55:41PM -0400, Sean Anderson wrote: > This updates logging documentation with some examples of the new commands > added in the previous commits. It also removes some items from the to-do > list which have been implemented. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Please note I accepted the newer wording to include describing the log continuation support. If this should be called out specifically again, please do a follow-up. Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 19/22] cmd: log: Add commands to manipulate filters
On Tue, Oct 27, 2020 at 07:55:38PM -0400, Sean Anderson wrote: > This adds several commands to add, list, and remove log filters. Due to the > complexity of adding a filter, `log filter-list` uses options instead of > positional arguments. > > These commands have been added as subcommands to log by using a dash to > join the subcommand and subsubcommand. This is stylistic, and they could be > converted to proper subsubcommands if it is wished. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [maemo-leste] [PATCH] nokia_rx51: disable obsolete VIDEO config
On Thursday 29 October 2020 14:06:30 Lokesh Vutla wrote: > On 24/10/20 5:49 pm, Tom Rini wrote: > > On Sat, Oct 24, 2020 at 12:46:45PM +0200, Merlijn Wajer wrote: > >> Hi, > >> > >> On 24/10/2020 12:06, Pali Rohár wrote: > >>> On Wednesday 21 October 2020 08:47:02 Tom Rini wrote: > On Wed, Oct 21, 2020 at 11:08:37AM +0200, Pali Rohár wrote: > > On Tuesday 20 October 2020 10:17:07 Tom Rini wrote: > >> On Tue, Oct 20, 2020 at 11:30:51AM +0200, Pali Rohár wrote: > >> > > Yes, there is mmc issue, I have found which commit caused it and > > because nobody was able to debug / understand what is happening I have > > sent revert patch, which fixes that issue, until somebody solve issue in > > original patch. > > > > But I do not see any progress on either applying revert patch or fixing > > original patch. > > > > And I do not like to have custom patch in my local branch (and > > periodically rebasing it) as it just another layer of complication. > > > > Could we move somehow in this issue? > > No, it's probably stuck until you can fix the problem or otherwise add a > "quirk" for your platform. What does Linux do in this case? > >>> > >>> Well, I provided all requested information, just I'm lacking any new > >>> response from developers / maintainers of particular code. > >>> > >>> I have already identified problematic place / commit and I have already > >>> sent revert patch which fixing this issue. > >>> > >>> Tom, what else do you need? > >>> > >>> I see the main issue now that nobody reviewed / merged patch and nobody > >>> responded to emails which I have sent more then 2 months ago. > >> > >> I would like to add my voice for reverting the patches that break the > >> support, and work from that point to improve support and eventually > >> migrate to DT. > >> > >> Maemo Leste has a lot of Nokia N900 users, and this is blocking us from > >> moving to mainline u-boot. Is it possible to get the opinion of the > >> original patch authors on this? > >> > >> I am set up with a serial module on the Nokia N900, so I can help > >> provide specific debug info. > > > > Let me add in the TI folks that might be able to look in to any of this > > today. But the next problem is that the rx51 needs to be converted to > > use DM in U-Boot. It's throwing up a ton of "you need to convert to X > > by or this board may be removed" warnings at > > build. I really really want to see some of this start to be addressed. > > > IIUC, the breakage is happening in non-DM code. No, this code is not non-DM specific. It is used also for DM builds.
Re: [PATCH 1/1] env: typo enougth
On Fri, Oct 30, 2020 at 12:11 AM Heinrich Schuchardt wrote: > > %s/enougth/enough/ > > Signed-off-by: Heinrich Schuchardt Acked-by: Joe Hershberger
[PATCH] configs: meson64_android: don't show logo on ROM USB boot
From: Guillaume La Roque
When booting from rom usb, skip the boot logo logic as it's possible
that the partition containing the logo does not exist yet.
Signed-off-by: Neil Armstrong
Signed-off-by: Guillaume La Roque
Signed-off-by: Mattijs Korpershoek
---
include/configs/meson64_android.h | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/include/configs/meson64_android.h
b/include/configs/meson64_android.h
index 8fff915b50a4..c47d51c85368 100644
--- a/include/configs/meson64_android.h
+++ b/include/configs/meson64_android.h
@@ -98,11 +98,14 @@
func(SYSTEM, system, na) \
#define PREBOOT_LOAD_LOGO \
- "mmc dev ${mmcdev};" \
- "part start mmc ${mmcdev} ${logopart} boot_start;" \
- "part size mmc ${mmcdev} ${logopart} boot_size;" \
- "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \
+ "if test \"${boot_source}\" != \"usb\" && " \
+ "gpt verify mmc ${mmcdev} ${partitions}; then; " \
+ "mmc dev ${mmcdev};" \
+ "part start mmc ${mmcdev} ${logopart} boot_start;" \
+ "part size mmc ${mmcdev} ${logopart} boot_size;" \
+ "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \
"bmp display ${loadaddr} m m;" \
+ "fi;" \
"fi;"
#define CONFIG_EXTRA_ENV_SETTINGS \
--
2.25.1
Re: [PATCH v4 15/22] cmd: log: Add commands to list categories and drivers
On Tue, Oct 27, 2020 at 07:55:34PM -0400, Sean Anderson wrote: > This allows users to query which categories and drivers are available on > their system. This allows them to construct filter-add commands without > (e.g.) adjusting the log format to show categories and drivers. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 12/22] test: Add test for LOGFF_MIN
On Tue, Oct 27, 2020 at 07:55:31PM -0400, Sean Anderson wrote: > This tests log filters matching on a minimum level. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 10/22] test: Add tests for LOGFF_DENY
On Tue, Oct 27, 2020 at 07:55:29PM -0400, Sean Anderson wrote: > This adds some tests for log filters which deny if they match. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 13/22] cmd: log: Use sub-commands for log
On Tue, Oct 27, 2020 at 07:55:32PM -0400, Sean Anderson wrote: > This reduces duplicate code, and makes adding new sub-commands easier. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 07/22] log: Add filter flag to deny on match
On Tue, Oct 27, 2020 at 07:55:26PM -0400, Sean Anderson wrote: > Without this flag, log filters can only explicitly accept messages. > Allowing denial makes it easier to filter certain subsystems. Unlike > allow-ing filters, deny-ing filters are added to the beginning of the > filter list. This should do the Right Thing most of the time, but it's > less-universal than allowing filters to be inserted anywhere. If this > becomes a problem, then perhaps log_filter_add* should take a filter number > to insert before/after. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 09/22] test: log: Give tests names instead of numbers
On Tue, Oct 27, 2020 at 07:55:28PM -0400, Sean Anderson wrote: > Now that the log test command is no more, we can give the log tests proper > names. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 11/22] log: Add filter flag to match greater than a log level
On Tue, Oct 27, 2020 at 07:55:30PM -0400, Sean Anderson wrote: > This is the complement of the existing behavior to match only messages with > a log level less than a threshold. This is primarily useful in conjunction > with LOGFF_DENY. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 08/22] test: log: Convert log_test from python to C
On Tue, Oct 27, 2020 at 07:55:27PM -0400, Sean Anderson wrote: > When rebasing this series I had to renumber all my log tests because > someone made another log test in the meantime. This involved updaing a > number in several places (C and python), and it wasn't checked by the > compiler. So I though "how hard could it be to just rewrite in C?" And > though it wasn't hard, it *was* tedious. Tests are numbered the same as > before to allow for easier review. > > A note that if a test fails, everything after it will probably also fail. > This is because that test won't clean up its filters. There's no easy way > to do the cleanup, except perhaps removing all filters in a wrapper > function. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [patch v2 01/10] drivers/video/rockchip/rk_vop.c: Use endpoint compatible string to find VOP mode
Kever Yang writes: > Hi Arnaud, > > Thanks for your patch. > > Please use module name as subject prefix instead of a file name, > eg. "rockchip: video: vop". > ok. will fix. > On 2020/10/27 下午9:21, Arnaud Patard (Rtp) wrote: >> The current code is using an hard coded enum and the of node reg value of >> endpoint to find out if the endpoint is mipi/hdmi/lvds/edp/dp. The order >> is different between rk3288, rk3399 vop little, rk3399 vop big. >> >> A possible solution would be to make sure that the rk3288.dtsi and >> rk3399.dtsi files have "expected" reg value or an other solution is >> to find the kind of endpoint by comparing the endpoint compatible value. >> >> This patch is implementing the more flexible second solution. >> >> Signed-off-by: Arnaud Patard >> >> Index: u-boot/arch/arm/include/asm/arch-rockchip/vop_rk3288.h >> === >> --- u-boot.orig/arch/arm/include/asm/arch-rockchip/vop_rk3288.h >> +++ u-boot/arch/arm/include/asm/arch-rockchip/vop_rk3288.h > > For the patch format, please make sure the u-boot is the root directory. > Can you please explain this point ? It's a valid patch which can be applied with patch -p1. I've been generating patches with quilt for ages and patches got merged in various projects including in the kernel even before git, so I fail to get what's wrong with it. Or are you telling me that uboot is accepting only patches generated with git ? Arnaud
Re: [PATCH v4 2/3] env: Access Environment in SPI flashes before relocation
On Sat, Oct 10, 2020 at 10:28:05AM +0200, Heiko Schocher wrote: > Enable the new Kconfig option ENV_SPI_EARLY if you want > to use Environment in SPI flash before relocation. > Call env_init() and than you can use env_get_f() for > accessing Environment variables. > > Signed-off-by: Heiko Schocher > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 3/3] imx6: enable early spi environment access on aristainetos boards
On Sat, Oct 10, 2020 at 10:28:06AM +0200, Heiko Schocher wrote: > On aristianetos boards the display type is detected > through "panel" environment variable. Dependend on the > display type we detect the board type and this decides which > DTB we have to use for the board. > > So we need early spi environment access. > > Signed-off-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Please pull u-boot-marvell/master
On Thu, Oct 29, 2020 at 03:31:27PM +0100, Stefan Roese wrote: > Hi Tom, > > please pull an update of Marvell Armada & Octeon TX/TX2 related > patches. Here the summary log: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 1/3] env: split env_import_redund() into 2 functions
On Sat, Oct 10, 2020 at 10:28:04AM +0200, Heiko Schocher wrote: > split from env_import_redund() the part which checks > which Environment is valid into a separate function > called env_check_redund() and call it from env_import_redund(). > > So env_check_redund() can be used from places which also > need to do this checks. > > Signed-off-by: Heiko Schocher > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
