This series add support for Macronix octal DTR flash, add flag for
Softreset with "INVERT" command extension type on boot and follow
linux kernel to enable 4byte opcode when possible.
v8:
Correct spi nor flash information in IDs table.
v7:
Correct title and description of patchworks.
Follow patch (Allow using Micron
mt35xu512aba
in Octal DTR mode).
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency for adding Macronix flash in Octal DTR mode.
Parse SCCR 22nd dword and check DTR Octal Mode Enable
Volatile bit for Octal DTR enable
Signed-off-by: JaimeLiao
---
drivers/mtd/spi/spi-nor-core.c | 52 ++
include/linux/mtd/spi-nor.h| 1 +
2 files changed, 53 insertions(+)
diff --git
Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
in the begging of probe.
Command extension type is not standardized across flash vendors in DTR mode.
For suiting different vendor flash devices, adding a flag to seperate types for
soft reset on boot.
On 03.07.22 12:48, Pali Rohár wrote:
PCIe config space has address range 0-4095. So do not allow reading from
addresses outside of this range. Lot of U-Boot drivers do not expect that
passed value is not in this range. PCI DM read function is exetended to
s/exetended/extended
fill read value
Adding Macronix Octal flash for Octal DTR support.
The octaflash series can be divided into the following types:
MX25 series : Serial NOR Flash.
MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW
Hi Heinrich,
On Sun, Jul 3, 2022 at 8:09 PM Heinrich Schuchardt
wrote:
>
>
>
> On 7/3/22 13:28, Heinrich Schuchardt wrote:
> > Consider which boot devices are enabled in the definition of the
> > BOOT_TARGET_DEVICES() macro.
> >
> > Signed-off-by: Heinrich Schuchardt
>
> Hello Bin,
>
> With the
El Tue, Jun 21, 2022 at 10:07:29AM +, Lee Jones deia:
> Currently the default initialisation frequency is 50MHz. Although
> this does appear to be suitable for some LPDDR4 RAM chips, training at
> this low frequency has been seen to cause Column errors, leading to
> Capacity check errors on
On 7/4/22 11:55, Bin Meng wrote:
Hi Heinrich,
On Sun, Jul 3, 2022 at 8:09 PM Heinrich Schuchardt
wrote:
On 7/3/22 13:28, Heinrich Schuchardt wrote:
Consider which boot devices are enabled in the definition of the
BOOT_TARGET_DEVICES() macro.
Signed-off-by: Heinrich Schuchardt
Hello
To reduce code duplication, let the stm32 based DH boards use the common
code for setting up their mac addresses.
Signed-off-by: Philip Oberfichtner
---
board/dhelectronics/dh_stm32mp1/board.c | 104 +++-
1 file changed, 47 insertions(+), 57 deletions(-)
diff --git
To reduce code duplication, let the imx8 based DH boards use the common
code for setting up their mac addresses.
Signed-off-by: Philip Oberfichtner
---
.../dh_imx8mp/imx8mp_dhcom_pdk2.c | 121 +++---
1 file changed, 48 insertions(+), 73 deletions(-)
diff --git
To reduce code duplication, let the imx6 based DH boards use the common
code for setting up their mac addresses.
Signed-off-by: Philip Oberfichtner
---
board/dhelectronics/dh_imx6/dh_imx6.c | 47 ---
1 file changed, 14 insertions(+), 33 deletions(-)
diff --git
Hello!
On Thursday 30 June 2022 08:46:59 Alexander Dahl wrote:
> Hello,
>
> Am Mittwoch, 29. Juni 2022, 15:55:27 CEST schrieb Pali Rohár:
> > Hello!
> >
> > On Wednesday 29 June 2022 15:36:57 Alexander Dahl wrote:
> > > Hello Pali,
> > >
> > > had a look at this patch, and have some questions.
On 7/4/22 09:58, Joel Stanley wrote:
From: Samuel Mendoza-Jonas
Add the handling of NC-SI ethernet frames, and add a check at the start
of net_loop() to configure NC-SI before starting other network commands.
This also adds an "ncsi" command to manually start NC-SI configuration.
On 7/4/22 09:58, Joel Stanley wrote:
Aspeed BMCs are commonly used with NC-SI. A system indicates the driver
should configure the link over NC-SI using the device tree.
Add it to the defconfig so we get compile coverage of the driver, even
if the EVBs do not normally use it.
Signed-off-by:
On 7/4/22 09:58, Joel Stanley wrote:
From: Samuel Mendoza-Jonas
Update the ftgmac100 driver to support NC-SI instead of an mdio phy
where available. This is a common setup for Aspeed AST2x00 platforms.
NC-SI mode is determined from the device-tree if either phy-mode sets it
or the use-ncsi
On Sun, Jul 03, 2022 at 06:26:22PM -0500, Samuel Holland wrote:
> Hi Michal,
>
> On 7/3/22 2:20 PM, Michal Suchanek wrote:
> >
> > Hello,
> >
> > many ARM SoCs have a mask rom feature that provides interface for
> > downloading firmware over USB.
> >
> > Downstream rockchip u-boot has 'brom'
Increase HUB_DEBOUNCE_TIMEOUT to 2000 because some usb device
needs around 1.5s or more to make the hub port status to be
connected steadily after being powered off and powered on.
These value is aligned with Linux driver and avoids to configure
"usb_pgood_delay" as a workaround for connection
Introduce define for connection timeout, named HUB_DEBOUNCE_TIMEOUT
as in linux kernel drivers/usb/core/hub.c
Signed-off-by: Patrick Delaunay
---
common/usb_hub.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index
On Tue, 7 Jun 2022 at 13:22, Etienne Carriere
wrote:
>
> Removes local variable child in optee_probe() that is not used.
>
> Cc: Patrick Delaunay
> Signed-off-by: Etienne Carriere
> ---
> No change since v2.
>
> New change not in v1 series.
> ---
> drivers/tee/optee/core.c | 3 +--
> 1 file
Aspeed BMCs are commonly used with NC-SI. A system indicates the driver
should configure the link over NC-SI using the device tree.
Add it to the defconfig so we get compile coverage of the driver, even
if the EVBs do not normally use it.
Signed-off-by: Joel Stanley
---
On 7/4/22 11:50, Bin Meng wrote:
On Sun, Jul 3, 2022 at 7:28 PM Heinrich Schuchardt
wrote:
Consider which boot devices are enabled in the definition of the
BOOT_TARGET_DEVICES() macro.
Signed-off-by: Heinrich Schuchardt
---
include/configs/qemu-riscv.h | 25 ++---
1
On Mon, Jul 4, 2022 at 6:07 PM Heinrich Schuchardt
wrote:
>
> On 7/4/22 11:50, Bin Meng wrote:
> > On Sun, Jul 3, 2022 at 7:28 PM Heinrich Schuchardt
> > wrote:
> >>
> >> Consider which boot devices are enabled in the definition of the
> >> BOOT_TARGET_DEVICES() macro.
> >>
> >> Signed-off-by:
Hi Fabio and Marek
Trying to understand the reason why I can boot using imx_usb loader
and not the uuu tool
If I do:
./imx_usb SPL
./imx_usb u-boot-dtb.img
It works
U-Boot SPL 2022.07-rc5-00075-g01d253835a-dirty (Jul 04 2022 - 12:39:
11 +0200)
>>SPL: board_init_r()
spl_init
Trying to boot
On 01/07/2022 21.25, Tom Rini wrote:
> On Fri, Jul 01, 2022 at 09:27:59AM +0200, Rasmus Villemoes wrote:
>> When trying to use the exact same device tree source to build the dtbs
>> used with U-Boot and linux, one often runs into various problems. For
>> example, files under include/dt-bindings/
On Friday 01 July 2022 09:21:34 Stefan Roese wrote:
> On 23.06.22 14:13, Pali Rohár wrote:
> > Commit d293759d55cc ("serial: ns16550: Add support for
> > SPL_DEBUG_UART_BASE") fixed support for setting correct early debug UART
> > base address in SPL.
> >
> > But after this commit, output from
Hello,
On Sun, Jul 03, 2022 at 11:23:26PM +0100, Andre Przywara wrote:
> On Sun, 3 Jul 2022 21:20:22 +0200
> Michal Suchanek wrote:
>
> Hi Michal,
>
> > p-boot uses RTC GPR 1 value 0xb0010fe1 to flag FEL boot on A64
> >
> > Default to the same.
>
> Please don't add any more #ifdef's to
El Tue, Jun 21, 2022 at 10:07:27AM +, Lee Jones deia:
> Functions pointed to by this op pointer can return non-zero values
> indicating an error. Ensure any error value is propagated back up the
> call-chain.
>
> Signed-off-by: Lee Jones
My board doesn't suffer with the issue resolved by
This series unifies common mac address code for imx6, imx8 and stm32
based boards by DH. It is thought of as a starting point for more
deduplication in the future.
Philip Oberfichtner (4):
board: dhelectronics: Implement common mac address functions
ARM: imx6: DH: Use common mac address
This is a starting point for unifying duplicate code in the DH board
files. The functions for setting up the mac address are very similar for
the i.MX6, i.MX8 and stm32mp1 based boards.
All pre-existing implementations follow the same logic:
(1) Check if ethaddr is already set in the environment
From: Samuel Mendoza-Jonas
Update the ftgmac100 driver to support NC-SI instead of an mdio phy
where available. This is a common setup for Aspeed AST2x00 platforms.
NC-SI mode is determined from the device-tree if either phy-mode sets it
or the use-ncsi property exists. If set then normal mdio
From: Samuel Mendoza-Jonas
Add the handling of NC-SI ethernet frames, and add a check at the start
of net_loop() to configure NC-SI before starting other network commands.
This also adds an "ncsi" command to manually start NC-SI configuration.
Signed-off-by: Samuel Mendoza-Jonas
Signed-off-by:
Back in 2019 Sam submitted NC-SI support. The NC-SI PHY driver was
merged (patches 1 and 2), but we never got around to merging patches 3
and 4:
https://lore.kernel.org/u-boot/20190618013720.2823-1-...@mendozajonas.com/
Sam as long since moved on from working on the Aspeed BMCs, but the code
On Sun, Jul 03, 2022 at 11:22:51PM +0100, Andre Przywara wrote:
> On Sun, 3 Jul 2022 21:20:20 +0200
> Michal Suchanek wrote:
>
> Hi,
>
> > many ARM SoCs have a mask rom feature that provides interface for
> > downloading firmware over USB.
> >
> > Downstream rockchip u-boot has 'brom' or
On Sun, Jul 3, 2022 at 7:28 PM Heinrich Schuchardt
wrote:
>
> Consider which boot devices are enabled in the definition of the
> BOOT_TARGET_DEVICES() macro.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> include/configs/qemu-riscv.h | 25 ++---
> 1 file changed, 22
El Tue, Jun 21, 2022 at 10:07:28AM +, Lee Jones deia:
> Frequency changes to 400MHz are presently reported as:
>
> lpddr4_set_rate_0: change freq to 4 mhz 0, 1
>
> This is obviously wrong by 6 orders of magnitude.
>
> Ensure frequency changes are reported accurately.
>
Not
[ Adding Joel ]
On 7/3/22 11:00, Chin-Ting Kuo wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Sent: Friday, July 1, 2022 7:51 PM
Subject: Re: [v4 04/12] configs: aspeed: Enable SPI flash features
On 7/1/22 11:28, Cédric Le Goater wrote:
On 5/24/22 07:56, Chin-Ting Kuo
On Fri, 01 Jul 2022, Kever Yang wrote:
> Hi Lee Jones,
>
>
> On 2022/6/27 16:39, Lee Jones wrote:
> > On Tue, 21 Jun 2022, Lee Jones wrote:
> >
> > > Functions pointed to by this op pointer can return non-zero values
> > > indicating an error. Ensure any error value is propagated back up the
Hi
On 2022/7/4 17:23, Lee Jones wrote:
On Fri, 01 Jul 2022, Kever Yang wrote:
Hi Lee Jones,
On 2022/6/27 16:39, Lee Jones wrote:
On Tue, 21 Jun 2022, Lee Jones wrote:
Functions pointed to by this op pointer can return non-zero values
indicating an error. Ensure any error value is
On Mon, 04 Jul 2022, Kever Yang wrote:
> Hi
>
> On 2022/7/4 17:23, Lee Jones wrote:
> > On Fri, 01 Jul 2022, Kever Yang wrote:
> >
> > > Hi Lee Jones,
> > >
> > >
> > > On 2022/6/27 16:39, Lee Jones wrote:
> > > > On Tue, 21 Jun 2022, Lee Jones wrote:
> > > >
> > > > > Functions pointed to
Hi,
On 6/30/22 19:20, Christopher Bowman wrote:
Greetings,
I have a board (Diligent Arty-Z7) for which I have a working U-boot. I’m not
sure I’ve done it right but it does work on my board. I’d like to contribute
this back and get it in U-boot.
Ok. One thing is contributing it back and
On Sat, Jul 02, 2022 at 03:23:42PM +0200, Heinrich Schuchardt wrote:
> CONFIG_SYS_64BIT_LBA is defined in common.h and used to define the size of
> lbaint_t in blk.h. On 32-bit system not including common.h first will lead
> to differences in the size of lbaint_t between modules.
>
> common.h
On Sat, Jul 02, 2022 at 03:28:32PM +0200, Heinrich Schuchardt wrote:
> The size of lbaint_t depends on CONFIG_SYS_64BIT_LBA defined in common.h.
> common.h should always be included as first include.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> common/avb_verify.c | 1 +
> 1 file changed, 1
On Sat, Jul 02, 2022 at 01:45:10AM +0100, Andre Przywara wrote:
> Commit 81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks
> optional") improved the error check to cover the reset property being
> optional. However this was using the wrong error variable for the
> check, so would now
Hi,
I did a test to do overlay for U-Boot runtime dtb, but after overlay
finish, U-Boot DM driver not work properly because the of_node
pointer is changed in a device.
So I am thinking whether this is valid to overlay to runtime U-Boot
dtb or not. The reason I try this is that I wanna overlay
On Mon, Jul 04, 2022 at 06:28:41PM +0530, Sumit Garg wrote:
> diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi
> b/arch/arm/dts/dragonboard845c-uboot.dtsi
> new file mode 100644
> index 00..8b5a7ee573
> --- /dev/null
> +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
> @@ -0,0 +1,37 @@
>
Add support for Qualcomm QCS404 SoC based evaluation board.
Features:
- Qualcomm Snapdragon QCS404 SoC
- 1GiB RAM
- 8GiB eMMC, uSD slot
U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/qcs404.rst.
For SDCC version 5.0.0, MCI registers are removed from SDCC interface
and some registers are moved to HC. So add support to use the new
compatible string "qcom,sdhci-msm-v5". Based on this new msm variant,
pick the relevant variant data and use it to detect MCI presence thereby
configuring
Currently its a dummy clock driver as clocks for UART and eMMC have been
already enabled by ABL. Along with this import "qcom,gcc-qcs404.h" header
from Linux mainline to support DT bindings.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/clock-qcs404.c | 30
Currently this pinctrl driver only supports BLSP UART2 specific pin
configuration.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/Makefile | 1 +
arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 +++
arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 +
On Mon, Jul 04, 2022 at 03:27:26PM +0200, Heinrich Schuchardt wrote:
> On 7/4/22 14:51, Peter Robinson wrote:
> > Hi Peng,
> >
> > > I did a test to do overlay for U-Boot runtime dtb, but after overlay
> > > finish, U-Boot DM driver not work properly because the of_node
> > > pointer is changed
A common external watchdog circuit is kept alive by triggering a short
pulse on the reset pin. This patch adds support for this use case, while
making the algorithm configurable in the devicetree.
The "linux,wdt-gpio" driver being modified is based off the equivalent
driver in the Linux kernel,
Some setups do not use Xen hypervisor console for logging, e.g. they
use emulated PL011 hardware or shared peripherals (real UART). In such
cases Xen HVC will be disabled on a build time and will cause issues in
current driver implementation.
This commit fixes build issues in Xen event channel
I am trying to build the host tools on Windows, and I have hit a road
block. Specifically, I get the output:
HOSTCC tools/mkeficapsule
tools/mkeficapsule.c:18:10: fatal error: uuid/uuid.h: No such file or
directory
18 | #include
Steps so far:
Download latest msys
Double upgrade with
On Mon, Jul 04, 2022 at 06:28:38PM +0530, Sumit Garg wrote:
> U-boot specific DT properties belong to *-uboot.dtsi
... and are already included in starqltechn-uboot.dtsi (which is the
only current consumer of sdm845.dtsi).
Adding fuller comments, such as the above, makes things much easier to
Rather than using magic numbers as clock ids for peripherals import
qcom,gcc-sdm845.h from Linux to be used standard macros for clock ids.
So start using corresponding clk-id macro for debug UART.
Signed-off-by: Sumit Garg
---
arch/arm/dts/sdm845.dtsi| 3 +-
Add support for 96Boards Dragonboard 845C aka Robotics RB3 development
platform. This board complies with 96Boards Open Platform Specifications.
Features:
- Qualcomm Snapdragon SDA845 SoC
- 4GiB RAM
- 64GiB UFS drive
U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed
Add support for two new boards db845c and qcs404-evb:
- db845c is a 96boards compliant platform aka RB3 based on Qualcomm
SDM845 SoC.
- qcs404-evb is an evaluation board from Qualcomm based on QCS404 SoC.
Both these platforms have one thing in common that u-boot is chain-loaded
in 64-bit mode
Configure debug UART pins as function: "qup9" rather than being regular
gpios. It fixes a hang seen during pinmux setting.
Signed-off-by: Sumit Garg
---
arch/arm/dts/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/sdm845.dtsi
U-boot specific DT properties belong to *-uboot.dtsi, so remove
corresponding redundant properties.
Signed-off-by: Sumit Garg
---
arch/arm/dts/sdm845.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 6f2fb20d68..88030156d9
On 7/4/22 14:51, Peter Robinson wrote:
Hi Peng,
I did a test to do overlay for U-Boot runtime dtb, but after overlay
finish, U-Boot DM driver not work properly because the of_node
pointer is changed in a device.
So I am thinking whether this is valid to overlay to runtime U-Boot
dtb or not.
Add a usage document for the 'rng' u-boot command.
Reviewed-by: Ilias Apalodimas
Reviewed-by: Simon Glass
Signed-off-by: Sughosh Ganu
---
Changes since V5: None
doc/usage/cmd/rng.rst | 26 ++
doc/usage/index.rst | 1 +
2 files changed, 27 insertions(+)
create mode
The 'rng' command dumps a number of random bytes on the console. Add a
set of tests for the 'rng' command. The test function performs basic
sanity testing of the command.
Since a unit test is being added for the command, enable it by default
in the sandbox platforms.
Reviewed-by: Simon Glass
Hello Chin-Ting,
On 7/3/22 10:47, Chin-Ting Kuo wrote:
Hi Cédric,
Thanks for the review.
-Original Message-
From: Cédric Le Goater
Sent: Friday, July 1, 2022 5:28 PM
To: Chin-Ting Kuo ; ChiaWei Wang
; lu...@denx.de; sean...@gmail.com;
Ryan Chen ; BMC-SW
; ja...@amarulasolutions.com;
On Mon, Jul 4, 2022 at 9:50 PM Martin Bonner wrote:
>
> I am trying to build the host tools on Windows, and I have hit a road
> block. Specifically, I get the output:
> HOSTCC tools/mkeficapsule
> tools/mkeficapsule.c:18:10: fatal error: uuid/uuid.h: No such file or
> directory
>18 |
Hey all,
So it should be final release day. However, given the large number of
pull requests that came in at the end of last week, I think it's
better to do one more -rc today and release next Monday, the 11th.
The -next branch is open, so if you had been preparing a PR for once the
release was
Hi Peng,
> I did a test to do overlay for U-Boot runtime dtb, but after overlay
> finish, U-Boot DM driver not work properly because the of_node
> pointer is changed in a device.
>
> So I am thinking whether this is valid to overlay to runtime U-Boot
> dtb or not. The reason I try this is that I
> Add support for two new boards db845c and qcs404-evb:
> - db845c is a 96boards compliant platform aka RB3 based on Qualcomm
> SDM845 SoC.
> - qcs404-evb is an evaluation board from Qualcomm based on QCS404 SoC.
>
> Both these platforms have one thing in common that u-boot is chain-loaded
> in
Hi Peter,
On Mon, 4 Jul 2022 at 18:35, Peter Robinson wrote:
>
> > Add support for two new boards db845c and qcs404-evb:
> > - db845c is a 96boards compliant platform aka RB3 based on Qualcomm
> > SDM845 SoC.
> > - qcs404-evb is an evaluation board from Qualcomm based on QCS404 SoC.
> >
> >
On 7/4/22 15:39, Tom Rini wrote:
On Mon, Jul 04, 2022 at 03:27:26PM +0200, Heinrich Schuchardt wrote:
On 7/4/22 14:51, Peter Robinson wrote:
Hi Peng,
I did a test to do overlay for U-Boot runtime dtb, but after overlay
finish, U-Boot DM driver not work properly because the of_node
pointer is
This device is used on SOM CCs that's why enable it by default.
Signed-off-by: Michal Simek
---
configs/xilinx_zynqmp_virt_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/xilinx_zynqmp_virt_defconfig
b/configs/xilinx_zynqmp_virt_defconfig
index 855a1c97731a..2763346f785f
This is a preliminary documentation introducing different
boot sequences, and notably the recovery mode.
Signed-off-by: Neil Armstrong
---
doc/board/amlogic/boot-flow.rst | 147
doc/board/amlogic/index.rst | 1 +
2 files changed, 148 insertions(+)
create
From: Simon Glass
These functions should really be available outside the TPM code, so that
other callers can find out which version the TPM is. Rename them to have
a tpm_ prefix() and add them to the header file.
Signed-off-by: Simon Glass
---
Changes since V5: None
include/tpm_api.h | 10
The 'rng' u-boot command is used for printing a select number of
random bytes on the console. Currently, the RNG device from which the
random bytes are read is fixed. However, a platform can have multiple
RNG devices, one example being qemu, which has a virtio RNG device and
the RNG pseudo device
Use a statically allocated buffer on stack instead of using malloc for
reading the random bytes. Using a local array is faster than
allocating heap memory on every initiation of the command.
Signed-off-by: Sughosh Ganu
---
Changes since V5: None
cmd/rng.c | 17 +++--
1 file
The TPM device has a builtin random number generator(RNG)
functionality. Expose the RNG functions of the TPM device to the
driver model so that they can be used by the EFI_RNG_PROTOCOL if the
protocol is installed.
Also change the function arguments and return type of the random
number functions
The TPM device comes with the random number generator(RNG)
functionality which is built into the TPM device. Add logic to add the
RNG child device in the TPM uclass post probe callback.
The RNG device can then be used to pass a set of random bytes to the
linux kernel, need for address space
The TPM device provides the random number generator(RNG)
functionality, whereby sending a command to the TPM device results in
the TPM device responding with random bytes.
There was a discussion on the mailing list earlier[1], where it was
explained that platforms with a TPM device can install
On 5/25/22 07:17, Ashok Reddy Soma wrote:
Add support for various flashes from below manufacturers which are tested
by xilinx for years.
EON:
en25q128b
GIGA:
gd25lx256e
ISSI:
is25lp008
is25lp016
is25lp01g
is25wp008
is25wp016
On 5/12/22 12:05, Ashok Reddy Soma wrote:
This patch series does the following:
* Move macros from cadence driver to cadence header file
* Add new versal specific cadence ospi driver
* Reset qspi flash in when driver probed
* Enable/Disable apb linear mode based on dma usage
* Fix
On Mon, Jul 04, 2022 at 08:37:48PM +0200, Heinrich Schuchardt wrote:
>
>
> On 7/4/22 14:19, Tom Rini wrote:
> > On Sat, Jul 02, 2022 at 03:28:32PM +0200, Heinrich Schuchardt wrote:
> >
> > > The size of lbaint_t depends on CONFIG_SYS_64BIT_LBA defined in common.h.
> > > common.h should always
On 7/4/22 14:19, Tom Rini wrote:
On Sat, Jul 02, 2022 at 03:28:32PM +0200, Heinrich Schuchardt wrote:
The size of lbaint_t depends on CONFIG_SYS_64BIT_LBA defined in common.h.
common.h should always be included as first include.
Signed-off-by: Heinrich Schuchardt
---
common/avb_verify.c
On 7/4/22 14:19, Tom Rini wrote:
On Sat, Jul 02, 2022 at 03:23:42PM +0200, Heinrich Schuchardt wrote:
CONFIG_SYS_64BIT_LBA is defined in common.h and used to define the size of
lbaint_t in blk.h. On 32-bit system not including common.h first will lead
to differences in the size of lbaint_t
Hi Fabio
I have managed to boot with this lts
uuu_version 1.2.39
# @_flash.bin| bootloader
# @_uboot.bin| uboot.dtb
# @_image [_flash.bin] | image burn to nand, default is the same as bootloader
# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ
SDP: boot -f
On 7/4/2022 7:00 PM, Michael Nazzareno Trimarchi wrote:
Hi Fabio and Marek
Trying to understand the reason why I can boot using imx_usb loader
and not the uuu tool
How do you use uuu? uuu -b sd flash.bin?
Regards,
Peng.
If I do:
./imx_usb SPL
./imx_usb u-boot-dtb.img
It works
U-Boot
Hi Tom,
Please pull fsl-qoriq-2022-7-3 based on your next branch for 2022.10
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/12603
--
Several patches from Pali
- fsl_elbc detection fix
- sort p2020 dts node, drop duplicated node
-
On 6/29/2022 6:09 PM, Frieder Schrempf wrote:
Am 27.06.22 um 05:24 schrieb Peng Fan (OSS):
From: Peng Fan
The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
set to 0x7E1000.
Signed-off-by: Peng Fan
---
common/spl/Kconfig| 1 +
On 7/5/2022 9:35 AM, Peng Fan (OSS) wrote:
On 6/29/2022 6:09 PM, Frieder Schrempf wrote:
Am 27.06.22 um 05:24 schrieb Peng Fan (OSS):
From: Peng Fan
The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
set to 0x7E1000.
Signed-off-by: Peng Fan
---
On Mon, Jul 04, 2022 at 10:46:45AM +0530, Sughosh Ganu wrote:
>
> The patchset adds support for the FWU Multi Bank Update[1]
> feature. Certain aspects of the Dependable Boot[2] specification have
> also been implemented.
>
> The FWU multi bank update feature is used for supporting multiple
>
From: Peng Fan
V4:
Rebased on Tom's next branch
Include kontron-sl-mx8mm_defconfig in patch 1
Address comments from net maintainers and add R-b
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/12617
V3:
Fix issue reported by CI build
- Enlarge SPL_MAX_SIZE for
From: Ye Li
The SPL SDP is configured as BOOT_DEVICE_BOARD, so when booting from
USB, change its type to BOOT_DEVICE_BOARD, so we can use SDP.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Peng Fan
The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
set to 0x7E1000.
Signed-off-by: Peng Fan
---
common/spl/Kconfig| 1 +
configs/imx8mm-cl-iot-gate-optee_defconfig| 1 -
configs/imx8mm-cl-iot-gate_defconfig | 1 -
From: Peng Fan
All the SoCs use mach-imx has CONFIG_MACH_IMX selected, so
the macro could be the gate to build arch/arm/mach-imx to simplify
the rules.
Signed-off-by: Peng Fan
---
arch/arm/Makefile | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git
From: Ye Li
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/Kconfig | 4 +
arch/arm/include/asm/global_data.h
From: Ye Li
Add TRDC driver to iMX9. The TRDC init splits to two phases:
1. Early init phase will release TRDC from Sentinel and open write
permission to the memory where SPL image runs. Sentinel will set
the memory to RX only after ROM authentication for the OEM
closed part.
2. Init
From: Peng Fan
Add new API to get sentinel FW status and SoC chip info
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 13 +
drivers/misc/sentinel/s400_api.c | 61
2 files changed, 74 insertions(+)
diff --git
From: Peng Fan
Support iMX93 communicate with Sentinel
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 30 +++
drivers/misc/sentinel/s4mu.c | 1 +
2 files changed, 31 insertions(+)
diff --git
From: Ye Li
To support more RDC instances on i.MX93, update API to latest
definition.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
drivers/misc/sentinel/s400_api.c | 21 +
2 files changed, 18 insertions(+), 5
From: Peng Fan
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function
prototype common and usable by i.MX9.
Also include mmc env functions that use ROM API.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 4 --
From: Peng Fan
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel
release M33 trout and make sure M33 could boot.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 1 +
drivers/misc/sentinel/s400_api.c | 25
2 files
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